SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 8678h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | STRATEGY_2TICK_COUNT | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | DISABLE_MEMORY_MASKED_WRITE | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TDFI_WRDATA_DELAY | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TDFI_PARIN_LAT | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:27 | RESERVED | NONE | 0h | Reserved |
| 26:24 | STRATEGY_2TICK_COUNT | R/W | 0h | NEED TO FiLL IN . Reset Source: ctl_amod_g_rst_n |
| 23:17 | RESERVED | NONE | 0h | Reserved |
| 16 | DISABLE_MEMORY_MASKED_WRITE | R/W | 0h | Restricts the controller from masked write commands. Set to 1 to not issue these commands. Only used if connected to an LPDDR4 device. Reset Source: ctl_amod_g_rst_n |
| 15:8 | TDFI_WRDATA_DELAY | R/W | 0h | Defines the tWRDATA_DELAY timing parameter [in DFI PHY clocks], the maximum cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. Reset Source: ctl_amod_g_rst_n |
| 7:3 | RESERVED | NONE | 0h | Reserved |
| 2:0 | TDFI_PARIN_LAT | R/W | 0h | Defines the DFI tPARIN_LAT timing parameter [in DFI PHY clocks], the maximum cycles between a DFI command and a dfi_parity_in signal assertion. Reset Source: ctl_amod_g_rst_n |