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A Power Glitch Detect (PGD) circuit is used to detect short duration “glitches” on the core and MPU power supplies. The PGD provides a low output when no glitch is detected and a high output when a glitch is detected.
Table 5-309 shows PGD modules allocation within device domains.
| Module Instance | Domain | ||
| WKUP | MCU | MAIN | |
| PGD0 | - | - | ✓ |
Figure 5-147 shows the PGD block diagram.
Figure 5-147 PGD Block DiagramTable 5-310 summarize the PGD integration.
| Module Instance | Monitored Voltage | PGD Control Register | PGD Status Register |
| PGD0 | VDD_CORE | CTRLMMR_MCU_VDD_CORE_GLDTC_CTRL | CTRLMMR_MCU_VDD_CORE_GLDTC_STAT |
| Interrupt Requests | |||||
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
| PGD0 | VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG_IPCFG | ESM_LVL_EVENT_IN_101 | ESM0 | PGD0 Threshold High flag level interrupt | Level |
| VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG | ESM_LVL_EVENT_IN_102 | ESM0 | PGD0 Threshold Low flag level interrupt | Level | |
For more information on the interconnects, see System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Device Configuration.
For more information on the device interrupt controllers, see Interrupt Controllers.