SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 85E0h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | RW2MRW_DLY_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 8h | ||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | RW2MRW_DLY_F0 | ||||||
| NONE | R/W | ||||||
| 0h | 8h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RD_TO_ODTH_F2 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | RD_TO_ODTH_F1 | ||||||
| NONE | R/W | ||||||
| 0h | 0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:29 | RESERVED | NONE | 0h | Reserved |
| 28:24 | RW2MRW_DLY_F1 | R/W | 8h | Additional delay to insert between read or write and mode_reg_write. Allowed programming dependent on memory system. FC=1 Reset Source: ctl_amod_g_rst_n |
| 23:21 | RESERVED | NONE | 0h | Reserved |
| 20:16 | RW2MRW_DLY_F0 | R/W | 8h | Additional delay to insert between read or write and mode_reg_write. Allowed programming dependent on memory system. FC=0 Reset Source: ctl_amod_g_rst_n |
| 15:14 | RESERVED | NONE | 0h | Reserved |
| 13:8 | RD_TO_ODTH_F2 | R/W | 0h | Defines the delay from a read command to ODT assertion. FC=2 Reset Source: ctl_amod_g_rst_n |
| 7:6 | RESERVED | NONE | 0h | Reserved |
| 5:0 | RD_TO_ODTH_F1 | R/W | 0h | Defines the delay from a read command to ODT assertion. FC=1 Reset Source: ctl_amod_g_rst_n |