SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
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| Instance Name | Physical Address |
|---|---|
| DDR16SS0 | 0F30 866Ch |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| DLL_RST_DELAY | |||||||
| R/W | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| DLL_RST_DELAY | |||||||
| R/W | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| TDFI_PHY_WRLAT_F2 | |||||||
| R/W | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TDFI_WRCSLAT_F2 | |||||||
| R/W | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:16 | DLL_RST_DELAY | R/W | 0h | Minimum cycles required for DLL reset signal dll_rst_n to be held. If this signal is not being used by the PHY, this parameter may be ignored. Reset Source: ctl_amod_g_rst_n |
| 15:8 | TDFI_PHY_WRLAT_F2 | R/W | 0h | DFI tPHY_WRLAT timing parameter. This is the number of DFI data phases between a write command and the first assertion of dfi_wrdata_en_pN. FC=2 Reset Source: ctl_amod_g_rst_n |
| 7:0 | TDFI_WRCSLAT_F2 | R/W | 0h | Defines the DFI tPHY_WRCSLAT timing parameter [in DFI PHY clocks], the maximum cycles between a write command and a dfi_wrdata_cs_n assertion. FC=2 Reset Source: ctl_amod_g_rst_n |