SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This section describes PCIe subsystem integration in the device MAIN domain, including information about clocks, resets, and hardware requests.
There is one PCIe subsystem integrated in the device MAIN domain - PCIE0. Figure 12-140 shows the integration of PCIE0.
Figure 12-140 PCIe
Subsystem IntegrationTable 12-191 through Table 12-194 summarize the integration of PCIE0 in the device MAIN domain.
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
|---|---|---|---|---|
| PCIE0 | PSC0 | PD0 | LPSC16 | CBASS0 |
| Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
|---|---|---|---|---|
| PCIE0 | PCIE0_FICLK | SYSCLK0 / 2 | PLLCTRL0 | PCIE0 interface bus clock (CBA_CLK). |
| PCIE0_PM_CLK | CLK_12M_RC | RCOSC | PCIE0 core free-running clock used for low power
state transitions and clock control generation. Used only if L1s power state is supported (see PCIe Subsystem Features). |
|
| MAIN_PLL2_HSDIV5_CLKOUT | PLL2_HSDIV5 | PCIE0 CPTS reference clock
(RCLK). Up to 250 MHz. The CPTS RCLK clock frequency should be greater than or equal to the PCIE CBA_CLK clock frequency. Otherwise, the software will have to add some wait cycles before a correct event is generated by the CPTS module. Additionally, the CPTS RCLK should be set to same frequency as the PCIe core clock. The selection of the source signal (see PCIe Subsystem Integration) can be done via the CTRLMMR_PCIE0_CLKSEL[2-0] CPTS_CLKSEL register field in the device Control Module. |
||
| MAIN_PLL0_HSDIV6_CLKOUT | PLL0_HSDIV6 | |||
| CP_GEMAC_CPTS_RFT_CLK | I/O pin | |||
| PCIE0_CPTS_RCLK | CPTS_RFT_CLK | I/O pin | ||
| MCU_EXT_REFCLK0 | I/O pin | |||
| EXT_REFCLK1 | I/O pin | |||
| SERDES0_IP1_LN0_TXMCLK | SERDES0 | |||
| PCIE0_LANE0_TXMCLK | SERDES0_IP1_LN0_TXMCLK | SERDES0 | PCIE0 core clock (CORE_CLK) driven by SERDES via lane 0. | |
| PCIE0_LANE0_RXCLK | SERDES0_IP1_LN0_RXCLK | SERDES0 | PCIE0 PIPE interface clock driven by SERDES via lane 0. | |
| SERDES0 | SERDES0_IP1_LN0_TXCLK | PCIE1_LANE0_TXCLK | PCIE0 | PCIE0 lane 0 PIPE/RAW TX return clock. |
| Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
|---|---|---|---|---|
| PCIE0 | PCIE0_RST | MOD_G_RST | LPSC16 | PCIE0 reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Type | Description |
|---|---|---|---|---|---|
| PCIE0 | PCIE0_DOWNSTREAM_PULSE_0 | GIC500_SPI_IN_230 | GICSS0 | Pulse | PCIE0 downstream interrupt |
| R5FSS0_CORE0_INTR_IN_230 | R5FSS0_CORE0 | Pulse | |||
| R5FSS0_CORE1_INTR_IN_230 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_230 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_230 | R5FSS1_CORE1 | Pulse | |||
| PCIE0_ERROR_PULSE_0 | GIC500_SPI_IN_179 | GICSS0 | Pulse | PCIE0 error interrupt | |
| R5FSS0_CORE0_INTR_IN_232 | R5FSS0_CORE0 | Pulse | |||
| R5FSS0_CORE1_INTR_IN_232 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_232 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_232 | R5FSS1_CORE1 | Pulse | |||
| PCIE0_FLR_PULSE_0 | GIC500_SPI_IN_231 | GICSS0 | Pulse | PCIE0 function level interrupt | |
| R5FSS0_CORE0_INTR_IN_231 | R5FSS0_CORE0 | Pulse | |||
| R5FSS0_CORE1_INTR_IN_231 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_231 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_231 | R5FSS1_CORE1 | Pulse | |||
| PCIE0_HOT_RESET_PULSE_0 | GIC500_SPI_IN_233 | GICSS0 | Pulse | PCIE0 hot reset interrupt | |
| R5FSS0_CORE0_INTR_IN_233 | R5FSS0_CORE0 | Pulse | |||
| R5FSS0_CORE1_INTR_IN_233 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_233 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_233 | R5FSS1_CORE1 | Pulse | |||
| PCIE0_LEGACY_PULSE_0 | GIC500_SPI_IN_234 | GICSS0 | Pulse | PCIE0 legacy interrupt | |
| R5FSS0_CORE0_INTR_IN_234 | R5FSS0_CORE0 | Pulse | |||
| R5FSS0_CORE1_INTR_IN_234 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_234 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_234 | R5FSS1_CORE1 | Pulse | |||
| PCIE0_LINK_STATE_PULSE_0 | GIC500_SPI_IN_235 | GICSS0 | Pulse | PCIE0 link state interrupt | |
| R5FSS0_CORE0_INTR_IN_235 | R5FSS0_CORE0 | Pulse | |||
| R5FSS0_CORE1_INTR_IN_235 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_235 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_235 | R5FSS1_CORE1 | Pulse | |||
| PCIE0_LOCAL_LEVEL_0 | GIC500_SPI_IN_236 | GICSS0 | Level | PCIE0 local interrupt | |
| R5FSS0_CORE0_INTR_IN_236 | R5FSS0_CORE0 | Level | |||
| R5FSS0_CORE1_INTR_IN_236 | R5FSS0_CORE1 | Level | |||
| R5FSS1_CORE0_INTR_IN_236 | R5FSS1_CORE0 | Level | |||
| R5FSS1_CORE1_INTR_IN_236 | R5FSS1_CORE1 | Level | |||
| PCIE0_PWR_STATE_PULSE_0 | GIC500_SPI_IN_178 | GICSS0 | Pulse | PCIE0 power state interrupt | |
| R5FSS0_CORE0_INTR_IN_197 | R5FSS0_CORE0 | Pulse | |||
| R5FSS0_CORE1_INTR_IN_197 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_197 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_197 | R5FSS1_CORE1 | Pulse | |||
| PCIE0_PHY_LEVEL_0 | GIC500_SPI_IN_237 | GICSS0 | Level | PCIE0 PHY interrupt | |
| R5FSS0_CORE0_INTR_IN_237 | R5FSS0_CORE0 | Level | |||
| R5FSS0_CORE1_INTR_IN_237 | R5FSS0_CORE1 | Level | |||
| R5FSS1_CORE0_INTR_IN_237 | R5FSS1_CORE0 | Level | |||
| R5FSS1_CORE1_INTR_IN_237 | R5FSS1_CORE1 | Level | |||
| GIC500_SPI_IN_238 | GICSS0 | Pulse | |||
| PCIE0_PTM_VALID_PULSE_0 | R5FSS0_CORE0_INTR_IN_238 | R5FSS0_CORE0 | Pulse | PCIE0 PTM valid interrupt | |
| R5FSS0_CORE1_INTR_IN_238 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_238 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_238 | R5FSS1_CORE1 | Pulse | |||
| PCIE0_ECC0_CORR_LEVEL_0 | ESM0_LVL_IN_27 | Level | PCIE0 ECC AGGR 0 correctable error interrupt | ||
| PCIE0_ECC0_UNCORR_LEVEL_0 | ESM0_LVL_IN_86 | ESM0 | Level | PCIE0 ECC AGGR 0 uncorrectable error interrupt | |
| PCIE0_ECC1_UNCORR_LEVEL_0 | ESM0_LVL_IN_87 | Level | PCIE0 ECC AGGR 1 uncorrectable error interrupt | ||
| GIC500_SPI_IN_229 | GICSS0 | Level | |||
| PCIE0_CPTS_PEND_0 | R5FSS0_CORE0_INTR_IN_229 | R5FSS0_CORE0 | Level | PCIE0 timesync interrupt | |
| R5FSS0_CORE1_INTR_IN_229 | R5FSS0_CORE1 | Level | |||
| R5FSS1_CORE0_INTR_IN_229 | R5FSS1_CORE0 | Level | |||
| R5FSS1_CORE1_INTR_IN_229 | R5FSS1_CORE1 | Level | |||
| GIC500_SPI_IN_232 | GICSS0 | Pulse | |||
| PCIE0_DPA_PULSE_0 | R5FSS0_CORE0_INTR_IN_103 | R5FSS0_CORE0 | Pulse | PCIE0 dynamic power allocation interrupt | |
| R5FSS0_CORE1_INTR_IN_103 | R5FSS0_CORE1 | Pulse | |||
| R5FSS1_CORE0_INTR_IN_103 | R5FSS1_CORE0 | Pulse | |||
| R5FSS1_CORE1_INTR_IN_103 | R5FSS1_CORE1 | Pulse |
| Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Type | Description |
|---|---|---|---|---|---|
| PCIE0 | - | - | - | - | The PCIe subsystem does not provide built-in DMA capabilities |
| Module Instance | Module Event | Destination Event Input | Destination | Type | Description |
|---|---|---|---|---|---|
| PCIE0 | PCIE0_CPTS_HW1_PUSH_0 | TIMESYNC_INTRTR0_IN_37 | TIMESYNC_INTRTR0 | Level | PCIE0 CPTS hardware push event (HW1_TS_PUSH) |
| PCIE0_CPTS_COMP_0 | CMPEVENT_INTRTR0_IN_81 | CMPEVENT_INTRTR0 | Pulse | PCIE0 CPTS compare output interrupt | |
| PCIE0_CPTS_SYNC_0 | TIMESYNC_INTRTR0_IN_33 | TIMESYNC_INTRTR0 | Level | PCIE0 CPTS sync output interrupt | |
| PCIE0_CPTS_GENF0_0 | TIMESYNC_INTRTR0_IN_23 | TIMESYNC_INTRTR0 | Level | PCIE0 CPTS GENF0 output interrupt | |
| PCIE0_PTM_VALID_PULSE_0 | TIMESYNC_INTRTR0_IN_38 | TIMESYNC_INTRTR0 | Level | PCIE0 PTM valid interrupt |
| Module Instance | Module Event | Source Event Output | Source | Type | Description |
|---|---|---|---|---|---|
| PCIE0 | PCIE0_CPTS_HW2_PUSH_0 | TIMESYNC_INTRTR0_OUTL_29 | TIMESYNC_INTRTR0 | Level | PCIE0 CPTS hardware time stamp push event (HW2_TS_PUSH) |