SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
There is one FSS integrated in the device MAIN domain - FSS0. Figure 14-5777 shows the integration of FSS0.
Figure 12-153 FSS0 IntegrationTable 12-225 through Table 12-228 summarize the integration of FSS0 in the device MAIN domain.
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
|---|---|---|---|---|
| FSS0 | PSC0 | PD0 | LPSC0 | CBASS0 |
| Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
|---|---|---|---|---|
| FSS0 | FSS0_ICLK | MAIN_SYSCLK0 | PLLCTRL0 | FSS0 interface clock |
| Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
|---|---|---|---|---|
| FSS0 | FSS0_RST | MOD_G_RST | LPSC0 | FSS0 system reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| For more information, see Table 12-236, FSS0_OSPI Hardware Requests. | |||||
For more information on the OSPI Integration, see Section 12.3.2.3, OSPI Integration.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.