Write the [23-0]MAC_VERIFY_CNT bit field in the
Ethernet port CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IET_VERIFY_REG
register to set the verify/response timeout count. The default is 10ms for
Gigabit mode. For other time values or link speeds the verify count should
be updated. If CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IET_CONTROL_REG[2]
MAC_DISABLEVERIFY bit is to be set (this is forced mode) then this step is
unneeded.
The receive FIFO block allocation is insufficient
if CPSW3_CPSW_NU_CPSW_NU_STAT_RX_BOTTOM_OF_FIFO_DROP_j [31-0] COUNT
is nonzero, indicating that receive packets are being dropped due to FIFO
block allocation.
The CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IET_CONTROL_REG[0]
MAC_PENABLE bit can be set as desired. No effect will occur until
IET_ENABLE is set. This bit enables premptable packets to be
prempted by express traffic but does not preclude packets from being
sent to the prempt queue.
If verify/response is
desired then CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IET_CONTROL_REG[3]
MAC_LINKFAIL should be cleared by software to enable verify and
response packets. Otherwise, MAC_DISABLEVERIFY bit should be set for
forced mode. Verification and response will occur immediately after
clearing this bit.
Set the IET_ENABLE bit in the CPSW3_CONTROL_REG register to enable IET operations.
After preemption has been verified, the CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IET_CONTROL_REG[23-16]
MAC_PREMPT field is written to configure the FIFO priorities to be sent to
the prempt queue (the other priorities with cleared bits go to the express
queue). The hardware switch for each queue from express to prempt happens
only when there are no packets queued on the priority.