SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Register Description: These registers are used to control functionality of CPUs without JTAG ports. There can be upto 32 of these registers
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| Instance Name | Physical Address |
|---|---|
| DEBUGSS_WRAP0_pwrap_cfg_1 | 7400 02300h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RETENTION | RST_OCCURED | PWR_LOSS_DET | INHIBIT_SLEEP | DEBUG_POWER | UNNAT_RESET | IN_RESET_RLS_WIR | RESET_MODE |
| R | R/W | R/W | R/W | R/W | R | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESET_MODE | DEBUG_ENABLE | RSV11_12 | EXEC_ACTION_DEBUG_ATTEN | RSV8_9 | |||
| R/W | R/W | R | R/W | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PWRDOWNDSRD | RSV6 | POWERED | CLKDOWNDSRD | FORCE_ACTIVE | CLOCKED | SECURITY | PRESENT |
| R | R | R | R | R/W | R | R | R |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:24 | RESERVED | R | 0h | Reserved, returns 0 |
| 23 | RETENTION | R | 0h | Core is in retention mode |
| 22 | RST_OCCURED | R/W | 0h | Sticky bit indicating a reset has occured Write 1 to clear this bit |
| 21 | PWR_LOSS_DET | R/W | 0h | Power Loss Detected Sticky bit, write a 1 to clear this bit |
| 20 | INHIBIT_SLEEP | R/W | 0h | Inhinit Sleep Block core from entering sleep mode |
| 19 | DEBUG_POWER | R/W | 0h | Core debug logic is powered |
| 18 | UNNAT_RESET | R | 0h | Unnatural Reset Device reset state is being affected by debug logic |
| 17 | IN_RESET_RLS_WIR | R/W | 0h | Writing a 1 releases the WIR When read this returns the reset status, 1 indicates core is in reset |
| 16:14 | RESET_MODE | R/W | 0h | Reset Mode 0=normal, 1=WIR, 2=Blk Rst, 3=Blk Assert, 4=Halt on Rst, 5=Cancel, 6=Halt and Block, 7=Halt-Blk-assert |
| 13 | DEBUG_ENABLE | R/W | 0h | Debug Enabled signal to the core |
| 12:11 | RSV11_12 | R | 0h | Reserved, return 0 |
| 10 | EXEC_ACTION_DEBUG_ATTEN | R/W | 0h | Writing this bit causes Execution Read will return the Debug Attention input value |
| 9:8 | RSV8_9 | R | 0h | Reserved, returns 0 when read |
| 7 | PWRDOWNDSRD | R | 0h | The core wants to turn off it's power when high |
| 6 | RSV6 | R | 0h | Reserved, returns 0 when read |
| 5 | POWERED | R | 0h | Core is powered up when high |
| 4 | CLKDOWNDSRD | R | 0h | The core wants to turn off it's clock when high |
| 3 | FORCE_ACTIVE | R/W | 0h | Force core active Turn on power and clocks |
| 2 | CLOCKED | R | 0h | When high the core clock is active |
| 1 | SECURITY | R | 0h | Security bit When high security is allowing access |
| 0 | PRESENT | R | 0h | The core controlled by this register exists when 1 |