SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The PRU_ICSSG UART0 transmitter section includes a transmitter hold register (THR), memory mapped in the register ICSS_G_PR1_ICSS_UART_UART_SLV_THR[7-80] DATA bitfield and a transmitter shift register (TSR), which is NOT memory mapped. When the PRU_ICSSG UART0 is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a function of the PRU_ICSSG UART0 line control register ICSS_G_PR1_ICSS_UART_UART_SLV_LCR. Based on the settings chosen in this register, the PRU_ICSSG UART0 transmitter sends the following to the receiving device:
THR receives data from the internal data bus, and when TSR (transmitter shift register) is ready, the PRU_ICSSG UART0 moves the data from THR to TSR. The PRU_ICSSG UART0 serializes the data in TSR and transmits the data on the UART0_TXD pin.
In the non-FIFO mode, if THR is empty and the Transmitter Holding Register Empty interrupt (THRE) is enabled in the interrupt enable register (ICSS_G_PR1_ICSS_UART_UART_SLV_IER[1] ETBEI), an interrupt is generated. This interrupt is cleared when a character is loaded into THR or the interrupt identification register ICSS_G_PR1_ICSS_UART_UART_SLV_IIR bitfield [3-1] IIR_INTID is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or ICSS_G_PR1_ICSS_UART_UART_SLV_IIR[3-1] IIR_INTID bitfield is read.