SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0451 A288h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| MAIN_CLKGATE_CTRL0_MAIN_DMSC_NOGATE_PROXY | RESERVED | MAIN_CLKGATE_CTRL0_MAIN_DBG_CBA_NOGATE_PROXY | RESERVED | MAIN_CLKGATE_CTRL0_MAIN_R5FSS1_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_R5FSS0_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_TIMERMGR_NOGATE_PROXY | |
| R/W | NONE | R/W | NONE | R/W | R/W | R/W | |
| X | 0h | X | 0h | X | X | X | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | MAIN_CLKGATE_CTRL0_MAIN_ICSSG1_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_ICSSG0_NOGATE_PROXY | RESERVED | MAIN_CLKGATE_CTRL0_MAIN_PDMA1_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_PDMA0_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_DMSS_NOGATE_PROXY | |
| NONE | R/W | R/W | NONE | R/W | R/W | R/W | |
| 0h | X | X | 0h | X | X | X | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MAIN_CLKGATE_CTRL0_MAIN_GIC500_NOGATE_PROXY | RESERVED | MAIN_CLKGATE_CTRL0_MAIN_A53_0_DBG_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_A53_0_CFG_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_A53_0_ACP_NOGATE_PROXY | |||
| R/W | NONE | R/W | R/W | R/W | |||
| X | 0h | X | X | X | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| MAIN_CLKGATE_CTRL0_MAIN_A53_0_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_CBA_ECC_AGG_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_FW_CBA_NOGATE_PROXY | MAIN_CLKGATE_CTRL0_MAIN_CBA_NOGATE_PROXY | RESERVED | MAIN_CLKGATE_CTRL0_MAIN_INFRA_ECC_AGG_NOGATE_PROXY | RESERVED | MAIN_CLKGATE_CTRL0_MAIN_INFRA_CBA_NOGATE_PROXY |
| R/W | R/W | R/W | R/W | NONE | R/W | NONE | R/W |
| X | X | X | X | 0h | X | 0h | X |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | MAIN_CLKGATE_CTRL0_MAIN_DMSC_NOGATE_PROXY | R/W | X | MAIN domain DMSC (pwr_dis_nogate) clock gate deactivate. Reset Source: mod_por_rst_n |
| 30:29 | RESERVED | NONE | 0h | Reserved |
| 28 | MAIN_CLKGATE_CTRL0_MAIN_DBG_CBA_NOGATE_PROXY | R/W | X | MAIN domain Debug bus clock gate deactivate. Reset Source: mod_por_rst_n |
| 27 | RESERVED | NONE | 0h | Reserved |
| 26 | MAIN_CLKGATE_CTRL0_MAIN_R5FSS1_NOGATE_PROXY | R/W | X | MAIN domain R5FSS1 clock gate deactivate. Reset Source: mod_por_rst_n |
| 25 | MAIN_CLKGATE_CTRL0_MAIN_R5FSS0_NOGATE_PROXY | R/W | X | MAIN domain R5FSS0 clock gate deactivate. Reset Source: mod_por_rst_n |
| 24 | MAIN_CLKGATE_CTRL0_MAIN_TIMERMGR_NOGATE_PROXY | R/W | X | MAIN domain TIMERMGR (pwr_dis_nogate) clock gate deactivate. Reset Source: mod_por_rst_n |
| 23:22 | RESERVED | NONE | 0h | Reserved |
| 21 | MAIN_CLKGATE_CTRL0_MAIN_ICSSG1_NOGATE_PROXY | R/W | X | MAIN domain ICSSG1 clock gate deactivate. Reset Source: mod_por_rst_n |
| 20 | MAIN_CLKGATE_CTRL0_MAIN_ICSSG0_NOGATE_PROXY | R/W | X | MAIN domain ICSSG0 clock gate deactivate. Reset Source: mod_por_rst_n |
| 19 | RESERVED | NONE | 0h | Reserved |
| 18 | MAIN_CLKGATE_CTRL0_MAIN_PDMA1_NOGATE_PROXY | R/W | X | MAIN domain PDMA1 (pwr_dis_nogate) clock gate deactivate. Reset Source: mod_por_rst_n |
| 17 | MAIN_CLKGATE_CTRL0_MAIN_PDMA0_NOGATE_PROXY | R/W | X | MAIN domain PDMA0 (pwr_dis_nogate) clock gate deactivate. Reset Source: mod_por_rst_n |
| 16 | MAIN_CLKGATE_CTRL0_MAIN_DMSS_NOGATE_PROXY | R/W | X | MAIN domain DMSS (pwr_dis_nogate) clock gate deactivate. Reset Source: mod_por_rst_n |
| 15 | MAIN_CLKGATE_CTRL0_MAIN_GIC500_NOGATE_PROXY | R/W | X | MAIN A53SS0 (gic500_1_2) clock gate deactivate. Reset Source: mod_por_rst_n |
| 14:11 | RESERVED | NONE | 0h | Reserved |
| 10 | MAIN_CLKGATE_CTRL0_MAIN_A53_0_DBG_NOGATE_PROXY | R/W | X | MAIN A53SS0 Debug Port clock gate deactivate. Reset Source: mod_por_rst_n |
| 9 | MAIN_CLKGATE_CTRL0_MAIN_A53_0_CFG_NOGATE_PROXY | R/W | X | MAIN A53SS0 Configuration Port clock gate deactivate. Reset Source: mod_por_rst_n |
| 8 | MAIN_CLKGATE_CTRL0_MAIN_A53_0_ACP_NOGATE_PROXY | R/W | X | MAIN A53SS0 ACP clock gate deactivate. Reset Source: mod_por_rst_n |
| 7 | MAIN_CLKGATE_CTRL0_MAIN_A53_0_NOGATE_PROXY | R/W | X | MAIN A53SS0 clock gate deactivate. Reset Source: mod_por_rst_n |
| 6 | MAIN_CLKGATE_CTRL0_MAIN_CBA_ECC_AGG_NOGATE_PROXY | R/W | X | MAIN domain data bus ECC aggragator (main_cba_ecc_aggr_main_0) clock gate deactivate. Reset Source: mod_por_rst_n |
| 5 | MAIN_CLKGATE_CTRL0_MAIN_FW_CBA_NOGATE_PROXY | R/W | X | MAIN domain datal bus (main_fw_cbass) clock gate deactivate. Reset Source: mod_por_rst_n |
| 4 | MAIN_CLKGATE_CTRL0_MAIN_CBA_NOGATE_PROXY | R/W | X | MAIN domain data bus (main_cbass) clock gate deactivate. Reset Source: mod_por_rst_n |
| 3 | RESERVED | NONE | 0h | Reserved |
| 2 | MAIN_CLKGATE_CTRL0_MAIN_INFRA_ECC_AGG_NOGATE_PROXY | R/W | X | MAIN domain Infrastructure ECC aggragator (main_infra_ecc_aggr) clock gate deactivate. Reset Source: mod_por_rst_n |
| 1 | RESERVED | NONE | 0h | Reserved |
| 0 | MAIN_CLKGATE_CTRL0_MAIN_INFRA_CBA_NOGATE_PROXY | R/W | X | MAIN domain Infrastructure bus (main_infra_cbass) clock gate deactivate. Reset Source: mod_por_rst_n |