SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Register Description: The Interrupt Status register is read by software to determine the cause of an interrupt.
Formula = (j * 1000h); where j = 0 to 183d
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| Instance Name | Physical Address |
|---|---|
| DMASS0_INTAGGR_INTR | 4800 0018h + formula |
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 |
| INTR_STATUS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 |
| INTR_STATUS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 |
| INTR_STATUS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| INTR_STATUS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| INTR_STATUS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| INTR_STATUS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| INTR_STATUS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| INTR_STATUS | |||||||
| R/W1TC | |||||||
| 0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 63:0 | INTR_STATUS | R/W1TC | 0h | Raw state (not enabled/masked) of bits in internal interrupt status register. Writing a 1 to any bit of this register will cause the corresponding raw status bit to be cleared Reset Source: srst_n |