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There are six DCC modules integrated in the device MAIN domain - DCC0 through DCC5. Figure 12-429 shows the integration of DCC modules.
Table 12-476 through Table 12-479 summarize the integration of DCC in the device MAIN domain.
| Module Instance | Power Sleep Controller | Power Domain | Module Domain | Interconnect |
|---|---|---|---|---|
| DCC0 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
| DCC1 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
| DCC2 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
| DCC3 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
| DCC4 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
| DCC5 | PSC0 | PD0 | LPSC0 | INFRA_CBASS0 |
| Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
|---|---|---|---|---|
| DCC0 | DCC0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC0 interface and functional clock |
| DCC1 | DCC1_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC1 interface and functional clock |
| DCC2 | DCC2_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC2 interface and functional clock |
| DCC3 | DCC3_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC3 interface and functional clock |
| DCC4 | DCC4_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC4 interface and functional clock |
| DCC5 | DCC5_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | DCC5 interface and functional clock |
| Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
|---|---|---|---|---|
| DCC0 | DCC0_RST | MOD_G_RST | LPSC0 | DCC0 asynchronous module reset |
| DCC1 | DCC1_RST | MOD_G_RST | LPSC0 | DCC1 asynchronous module reset |
| DCC2 | DCC2_RST | MOD_G_RST | LPSC0 | DCC2 asynchronous module reset |
| DCC3 | DCC3_RST | MOD_G_RST | LPSC0 | DCC3 asynchronous module reset |
| DCC4 | DCC4_RST | MOD_G_RST | LPSC0 | DCC4 asynchronous module reset |
| DCC5 | DCC5_RST | MOD_G_RST | LPSC0 | DCC5 asynchronous module reset |
| Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
|---|---|---|---|---|---|
| DCC0 | DCC0_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_112 | ESM0 | DCC0 error interrupt | Level |
| DCC1 | DCC1_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_113 | ESM0 | DCC1 error interrupt | Level |
| DCC2 | DCC2_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_114 | ESM0 | DCC2 error interrupt | Level |
| DCC3 | DCC3_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_115 | ESM0 | DCC3 error interrupt | Level |
| DCC4 | DCC4_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_116 | ESM0 | DCC4 error interrupt | Level |
| DCC5 | DCC5_INTR_ERR_LEVEL_0 | ESM0_LVL_IN_117 | ESM0 | DCC5 error interrupt | Level |
Section 12.6.1.2.2.1 summarizes the DCC input source clocks in the device MAIN domain.