SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
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| Instance Name | Physical Address |
|---|---|
| MCU_CTRL_MMR0 | 0451 8170h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| NONE | |||||||
| 0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | RST_CTRL_MCU_RESET_ISO_DONE_Z | RST_CTRL_MCU_ESM_ERROR_RST_EN_Z | RST_CTRL_DMSC_COLD_RESET_EN_Z | ||||
| NONE | R/W | R/W | R/W | ||||
| 0h | 0h | 1h | 0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | RST_CTRL_SW_MCU_WARMRST | ||||||
| NONE | R/W | ||||||
| 0h | Fh | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RST_CTRL_SW_MAIN_POR | RST_CTRL_SW_MAIN_WARMRST | ||||||
| R/W | R/W | ||||||
| Fh | Fh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:19 | RESERVED | NONE | 0h | Reserved |
| 18 | RST_CTRL_MCU_RESET_ISO_DONE_Z | R/W | 0h | MCU can set this bit to block warm reset in the main domain which is useful when the MCU may be accessing Reset Source: mcu_chip1_rst_n |
| 17 | RST_CTRL_MCU_ESM_ERROR_RST_EN_Z | R/W | 1h | Deactivate Reset of MCU by ESM Reset Source: mcu_chip1_rst_n |
| 16 | RST_CTRL_DMSC_COLD_RESET_EN_Z | R/W | 0h | Deactivate Reset of MCU by DMSC Reset Source: mcu_chip1_rst_n |
| 15:12 | RESERVED | NONE | 0h | Reserved |
| 11:8 | RST_CTRL_SW_MCU_WARMRST | R/W | Fh | This is a fault tolerant bitfield. Reset Source: mcu_chip1_rst_n |
| 7:4 | RST_CTRL_SW_MAIN_POR | R/W | Fh | This is a fault tolerant bitfield. Reset Source: main_chip1_rst_n |
| 3:0 | RST_CTRL_SW_MAIN_WARMRST | R/W | Fh | This is a fault tolerant bitfield. Reset Source: main_chip1_rst_n |