SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The CTRL_MMR0 module has one interrupt request, the CTRL_MMR0_ACCESS_ERR_0, which is associated with the following registers:
The PADCFG_CTRL0_CFG0 module also has one interrupt request, the PADCFG_CTRL0_ACCESS_ERR_0, which is associated with the following registers:
The following applies for the interrupt behavior of the CTRL_MMR0 module:
The same as previously described applies also for the interrupt behavior of the PADCFG_CTRL0_CFG0 module
Table 5-9 lists the interrupt events which can assert the CTRL_MMR0_ACCESS_ERR_0 interrupt line.
Table 5-10 lists the interrupt events which can assert the PADCFG_CTRL0_ACCESS_ERR_0 interrupt line.
| Event Flag | Event Mask | Description |
|---|---|---|
MAIN_CTRL_MMR_CFG0_INTR_RAW_STATUS[2] LOCK_ERR MAIN_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR[2] EN_LOCK_ERR | MAIN_CTRL_MMR_CFG0_INTR_ENABLE[2] LOCK_ERR_EN_SET MAIN_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR[2] LOCK_ERR_EN_CLR | Lock violation interrupt. Occurs when writing to a register in a locked CTRL_MMR0 partition. |
MAIN_CTRL_MMR_CFG0_INTR_RAW_STATUS[1] ADDR_ERR MAIN_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR[1] EN_ADDR_ERR | MAIN_CTRL_MMR_CFG0_INTR_ENABLE[1] ADDR_ERR_EN_SET MAIN_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR[1] ADDR_ERR_EN_CLR | Addressing violation interrupt. Occurs when accessing an illegal address inside the CTRL_MMR0 module. |
MAIN_CTRL_MMR_CFG0_INTR_RAW_STATUS[0] PROT_ERR MAIN_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR[0] EN_PROT_ERR | MAIN_CTRL_MMR_CFG0_INTR_ENABLE[0] PROT_ERR_EN_SET MAIN_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR[0] PROT_ERR_EN_CLR | Protection violation interrupt. Occurs when a register is accessed without the required secure/privilege level permissions. |
| Event Flag | Event Mask | Description |
|---|---|---|
MAIN_PADCFG_CTRL_MMR_CFG0_INTR_RAW_STATUS[2] LOCK_ERR MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR[2] EN_LOCK_ERR | MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE[2] LOCK_ERR_EN_SET MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR[2] LOCK_ERR_EN_CLR | Lock violation interrupt. Occurs when writing to a register in a locked PADCFG_CTRL0_CFG0 partition. |
MAIN_PADCFG_CTRL_MMR_CFG0_INTR_RAW_STATUS[1] ADDR_ERR MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR[1] EN_ADDR_ERR | MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE[1] ADDR_ERR_EN_SET MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR[1] ADDR_ERR_EN_CLR | Addressing violation interrupt. Occurs when accessing an illegal address inside the PADCFG_CTRL0_CFG0 module. |
MAIN_PADCFG_CTRL_MMR_CFG0_INTR_RAW_STATUS[0] PROT_ERR MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR[0] EN_PROT_ERR | MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE[0] PROT_ERR_EN_SET MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR[0] PROT_ERR_EN_CLR | Protection violation interrupt. Occurs when a register is accessed without the required secure/privilege level permissions. |
When an error event as described in Table 5-9 occurs, the error associated details are captured in the MAIN_CTRL_MMR_CFG0_FAULT_ADDRESS, MAIN_CTRL_MMR_CFG0_FAULT_TYPE_STATUS and MAIN_CTRL_MMR_CFG0_FAULT_ATTR_STATUS registers. MAIN_CTRL_MMR_CFG0_FAULT_ADDRESS contains the address of the first fault access. MAIN_CTRL_MMR_CFG0_FAULT_TYPE_STATUS and MAIN_CTRL_MMR_CFG0_FAULT_ATTR_STATUS contain status attributes associated with the first fault access. To clear the contents of these three registers and allow them to latch the attributes of the next fault the MAIN_CTRL_MMR_CFG0_FAULT_CLEAR[0] CLEAR bit must be set to 1h.
The same as previously described applies also for the PADCFG_CTRL0_CFG0 module. The corresponding registers are as follows: