The ARM Dual-Core Cortex-R5F processor subsystem (R5FSS) supports the following main features:
- Armv7-R architecture
- Supported modes of operation (boot-time configurable):
- Dual Core mode: two independent free-operating cores (Asymmetric Multi-Processing, no coherence)
- Single Core mode: one free-operating core and one non-operating core
R5FSS Memory System
- 32KB Instruction Cache
- 4x8KB ways
- SECDED ECC protected per 64 bits
- 32KB Data Cache
- 64KB tightly-coupled memory (TCM) per CPU
- SECDED ECC protected per 32 bits
- TCM hard error cache Implemented in CPU
- Readable/writable from system
- TCMs initialized (to 0's) at reset
- 32KB TCMA (ATCM)
- 16KB TCMB0 (B0TCM)
- 16KB TCMB1 (B1TCM)
- 128KB TCMA (ATCM) and 128KB TCMB (BTCM) for each core in Split-mode
Full-precision Floating Point (VFPv3)
8 breakpoints, 8 watch points
CoreSight Debug Access Port (DAP)
CoreSight ETM-R5 interface (CTI, ETM, ATB)
Performance Monitoring Unit (PMU)
32-bit to 36-bit Region-based Address Translation (RAT) on memory access initiators
Integrated Vectored Interrupt Manager (VIM) per core with 256 Interrupt Inputs each
- Programmable interrupt priority (4-bit)
- Programmable interrupt enable mask
- Software-generated interrupts
- Synchronous clock domain crossing on all core interfaces
Note: The operating cores can be configured to use the full TCM memory space available to both cores.
In Dual Core mode, CORE0 and CORE1 each have 64KB of TCM:
- 32KB TCMA
- 16KB TCMB0 + 16KB TCMB1
In Single Core mode, CORE0 has 128KB of TCM :- 64KB TCMA
- 64KB TCMB (32KB TCMB0 + 32KB TCMB1)
Note: These details describe a superset of the R5FSS memory configuration. For additional details on device memory availability, please refer to the device-specific data sheet.