SPRUIM2J May   2020  â€“ May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Glossary
    3.     Related Documentation From Texas Instruments
    4.     6
    5.     Support Resources
    6.     Trademarks
    7.     Export Control Notice
  3. 1 Introduction
    1. 1.1 Device Overview
    2.     12
    3. 1.2 Functional Block Diagram
      1. 1.2.1 Module Allocation and Instances within Device Domains
    4. 1.3 Device MAIN Domain
      1. 1.3.1  Arm Cortex-A53 Subsystem (A53SS)
      2. 1.3.2  Arm Cortex-R5F Processor Sub System (R5FSS)
      3. 1.3.3  Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
      4. 1.3.4  DDR 16-bit Subsystem (DDR16)
      5. 1.3.5  Region-based Address Translation Module (RAT)
      6. 1.3.6  Data Movement Subsystem (DMSS)
      7. 1.3.7  Mailbox (MAILBOX)
      8. 1.3.8  Spinlock (SPINLOCK)
      9. 1.3.9  Analog-to-Digital Converter (ADC)
      10. 1.3.10 General Purpose Input/Output Interface (GPIO)
      11. 1.3.11 Inter-Integrated Circuit Interface (I2C)
      12. 1.3.12 Serial Peripheral Interface (SPI)
      13. 1.3.13 Universal Asynchronous Receiver/Transmitter (UART)
      14. 1.3.14 3-port Gigabit Ethernet Switch (CPSW3G)
      15. 1.3.15 Peripheral Component Interconnect Express Subsystem (PCIE)
      16. 1.3.16 Serializer/Deserializer (SERDES)
      17. 1.3.17 Universal Serial Bus 3.1 Subsystem (USBSS)
      18. 1.3.18 General Purpose Memory Controller (GPMC)
      19. 1.3.19 Error Location Module (ELM)
      20. 1.3.20 Flash Subsystem (FSS) with Octal Serial Peripheral Interface (OSPI)
      21. 1.3.21 Multi-Media Card/Secure Digital Interface (MMCSD)
      22. 1.3.22 Enhanced Capture Module (ECAP)
      23. 1.3.23 Enhanced Pulse-Width Modulation Module (EPWM)
      24. 1.3.24 Enhanced Quadrature Encoder Pulse Module (EQEP)
      25. 1.3.25 Controller Area Network (MCAN)
      26. 1.3.26 Fast Serial Interface Receiver (FSI_RX)
      27. 1.3.27 Fast Serial Interface Transmitter (FSI_TX)
      28. 1.3.28 Timers
      29. 1.3.29 Internal Diagnostics Modules
    5. 1.4 Device MCU Domain
      1. 1.4.1 MCU Arm Cortex M4F Subsystem (MCU_M4FSS)
      2. 1.4.2 MCU General Purpose Input/Output Interface (MCU_GPIO)
      3. 1.4.3 MCU Inter-Integrated Circuit Interface (MCU_I2C)
      4. 1.4.4 MCU Multi-channel Serial Peripheral Interface (MCU_SPI)
      5. 1.4.5 MCU Universal Asynchronous Receiver/Transmitter (MCU_UART)
      6. 1.4.6 MCU Timers
      7. 1.4.7 MCU Internal Diagnostics Modules
    6. 1.5 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Memory Map
    2. 2.2 MCU_M4FSS0 Memory Map
    3. 2.3 R5FSS0 Memory Map
    4. 2.4 R5FSS1 Memory Map
    5. 2.5 PRU_ICSSG0 Memory Map
    6. 2.6 PRU_ICSSG1 Memory Map
    7. 2.7 MCU_M4FSS0 Memory Map
    8. 2.8 DMSC0 Memory Map
    9. 2.9 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 Terminology
    2. 3.2 System Interconnect Overview
    3. 3.3 Initiator/Target Connectivity
    4. 3.4 Interrupt Condition for Interconnect
      1. 3.4.1 Register MMR for default_err_intr
      2. 3.4.2 Register MMR for default_exp
    5. 3.5 IO Coherency Support
    6. 3.6 Quality of Service (QoS) Block
      1. 3.6.1 QoS Block MMR
      2. 3.6.2 QoS Summary Table
    7. 3.7 Route ID
      1. 3.7.1 Route ID Table
    8. 3.8 ISC and Firewall
      1. 3.8.1 Initiator-Side Security Controls (ISC)
        1. 3.8.1.1 ISC and Priv-ID
        2. 3.8.1.2 ISC Registers
      2. 3.8.2 Transaction Attributes for BCDMA and PktDMA Transactions
      3. 3.8.3 Firewall Block
        1. 3.8.3.1 Region Based Firewalls
        2. 3.8.3.2 Region Based Firewall Programming
    9. 3.9 System Interconnect Integration
      1. 3.9.1 Interconnect Integration in MAIN/MCU Domain
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Boot Terminology
    2. 4.2 Boot Process
      1. 4.2.1 Public ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
    3. 4.3 Boot Mode Pins
      1. 4.3.1 BOOTMODE Pin Mapping
        1. 4.3.1.1 Primary Boot Mode Selection and Configuration
        2. 4.3.1.2 Backup Boot Mode Selection and Configuration
    4. 4.4 Boot Modes
      1. 4.4.1  Boot with OSPI Controller
        1. 4.4.1.1 OSPI Boot
          1. 4.4.1.1.1 OSPI Bootloader Operation
            1. 4.4.1.1.1.1 OSPI Initialization Process
            2. 4.4.1.1.1.2 OSPI Loading Process
        2. 4.4.1.2 xSPI Boot
          1. 4.4.1.2.1 xSPI Bootloader Operation
          2. 4.4.1.2.2 xSPI Initialization Process
        3. 4.4.1.3 QSPI Boot
          1. 4.4.1.3.1 QSPI Bootloader Operation
            1. 4.4.1.3.1.1 QSPI Initialization Process
            2. 4.4.1.3.1.2 QSPI Loading Process
        4. 4.4.1.4 SPI Boot
          1. 4.4.1.4.1 SPI Bootloader Operation
            1. 4.4.1.4.1.1 SPI Initialization Process
            2. 4.4.1.4.1.2 SPI Loading Process
      2. 4.4.2  I2C Boot
        1. 4.4.2.1 I2C Bootloader Operation
          1. 4.4.2.1.1 I2C Initialization Process
            1. 4.4.2.1.1.1 Block Size
            2. 4.4.2.1.1.2 Addressing
          2. 4.4.2.1.2 I2C Loading Process
            1. 4.4.2.1.2.1 Loading a Boot Image From EEPROM
      3. 4.4.3  SD Card Boot
        1. 4.4.3.1 SD Card Bootloader Operation
      4. 4.4.4  eMMC Boot
        1. 4.4.4.1 eMMC Bootloader Operation
        2. 4.4.4.2 eMMC Flash
      5. 4.4.5  Ethernet Boot
        1. 4.4.5.1 Ethernet Bootloader Operation
          1. 4.4.5.1.1 Ethernet Initialization Process
          2. 4.4.5.1.2 Ethernet Loading Process
            1. 4.4.5.1.2.1 Ethernet Boot Data Formats
              1. 4.4.5.1.2.1.1 Limitations
              2. 4.4.5.1.2.1.2 BOOTP Request
                1. 4.4.5.1.2.1.2.1 MAC Header (DIX)
                2. 4.4.5.1.2.1.2.2 IPv4 Header
                3. 4.4.5.1.2.1.2.3 UDP Header
                4. 4.4.5.1.2.1.2.4 BOOTP Payload
                5. 4.4.5.1.2.1.2.5 TFTP
          3. 4.4.5.1.3 Ethernet Hand Over Process
      6. 4.4.6  USB Boot
        1. 4.4.6.1 USB Bootloader Operation
          1. 4.4.6.1.1 USB-Specific Attributes
            1. 4.4.6.1.1.1 DFU Device Mode
        2. 4.4.6.2 Limitations for USB DFU and PCIe boot modes
      7. 4.4.7  PCIe Boot
        1. 4.4.7.1 PCIe Bootloader Operation
          1. 4.4.7.1.1 PCIe Initialization Process
          2. 4.4.7.1.2 PCIe Loading Process
        2. 4.4.7.2 Limitations for USB DFU and PCIe boot modes
      8. 4.4.8  UART Boot
        1. 4.4.8.1 UART Bootloader Operation
          1. 4.4.8.1.1 Initialization Process
          2. 4.4.8.1.2 UART Loading Process
            1. 4.4.8.1.2.1 UART XMODEM
          3. 4.4.8.1.3 UART Hand-Over Process
      9. 4.4.9  GPMC NOR Boot
        1. 4.4.9.1 GPMC NOR Bootloader Operation
          1. 4.4.9.1.1 GPMC NOR Initialization Process
          2. 4.4.9.1.2 GPMC NOR Loading Process
      10. 4.4.10 GPMC NAND Boot
        1. 4.4.10.1 GPMC NAND Bootloader Operation
      11. 4.4.11 No boot/Development boot
    5. 4.5 PLL Configuration
    6. 4.6 Boot Parameter Tables
      1. 4.6.1  Common Header
      2. 4.6.2  PLL Setup
      3. 4.6.3  OSPI/QSPI/SPI Boot Parameter Table
      4. 4.6.4  UART Boot Parameter Table
      5. 4.6.5  PCIe Boot Parameter Table
      6. 4.6.6  I2C Boot Parameter Table
      7. 4.6.7  MMCSD/eMMC Boot Parameter Table
      8. 4.6.8  Ethernet Boot Parameter Table
      9. 4.6.9  xSPI Boot Parameter Table
      10. 4.6.10 USB DFU Boot Parameter Table
      11. 4.6.11 USB MSC Boot Parameter Table
      12. 4.6.12 GPMC NOR Boot Parameter Table
      13. 4.6.13 GPMC NAND Boot Parameter Table
    7. 4.7 Boot Image Format
      1. 4.7.1 Overall Structure
      2. 4.7.2 X.509 Certificate
      3. 4.7.3 Organizational Identifier (OID)
      4. 4.7.4 X.509 Extensions Specific to Boot
        1. 4.7.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.7.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.7.5 Extended Boot Info Extension
        1. 4.7.5.1 Impact on HS Device
        2. 4.7.5.2 Extended Boot Info Details
        3. 4.7.5.3 Certificate / Component Types
        4. 4.7.5.4 Extended Boot Encryption Info
        5. 4.7.5.5 Component Ordering
        6. 4.7.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.7.5.7 Device Type and Extended Boot Extension
      6. 4.7.6 Generating X.509 Certificates
        1. 4.7.6.1 Key Generation
          1. 4.7.6.1.1 Degenerate RSA Keys
        2. 4.7.6.2 Configuration Script
        3. 4.7.6.3 Image Data
    8. 4.8 Boot Memory Maps
      1. 4.8.1 Memory Layout/MPU
      2. 4.8.2 Global Memory Addresses Used by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 CTRL_MMR0 and PADCFG_CTRL0_CFG0
        1. 5.1.1.1 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Overview
        2. 5.1.1.2 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Integration
        3. 5.1.1.3 CTRL_MMR0 and PADCFG_CTRL0_CFG0 Functional Description
          1. 5.1.1.3.1 Description for CTRL_MMR0 and PADCFG_CTRL0_CFG0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  I/O Debounce Control Registers
            4. 5.1.1.3.1.4  Proxy Addressing Registers
            5. 5.1.1.3.1.5  CTRL_MMR0 Module Interrupts
            6. 5.1.1.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.1.3.1.7  Clock Muxing and Division Registers
            8. 5.1.1.3.1.8  Ethernet Port Operation Control Registers
            9. 5.1.1.3.1.9  DDRSS Dynamic Frequency Change Registers
            10. 5.1.1.3.1.10 Device Feature Registers
      2. 5.1.2 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0
        1. 5.1.2.1 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Register Types
            1. 5.1.2.3.1.1 Pad Configuration Registers
            2. 5.1.2.3.1.2 Kick Protection Registers
            3. 5.1.2.3.1.3 MCU_CTRL_MMR0 and MCU_PADCFG_CTRL0_CFG0 Module Interrupts
            4. 5.1.2.3.1.4 Clock Muxing and Division Registers
            5. 5.1.2.3.1.5 I/O Debounce Control Registers
            6. 5.1.2.3.1.6 PRG Related Registers
            7. 5.1.2.3.1.7 POK Module Registers
        4. 5.1.2.4 MCU_PADCFG_CTRL0_CFG0 Registers
        5. 5.1.2.5 MCU_CTRL_MMR0 Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Management Unit
          1. 5.2.2.1.1 Power OK (POK) Modules
            1. 5.2.2.1.1.1 Configuration Registers
          2. 5.2.2.1.2 Power on Reset (POR) Module
            1. 5.2.2.1.2.1 POR Overview
            2. 5.2.2.1.2.2 POR Integration
          3. 5.2.2.1.3 PoR/Reset Generator (PRG) Modules
            1. 5.2.2.1.3.1 PRG Overview
          4. 5.2.2.1.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.1.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.1.5.1 VTM Overview
              1. 5.2.2.1.5.1.1 VTM Features
              2. 5.2.2.1.5.1.2 VTM Not Supported Features
            2. 5.2.2.1.5.2 VTM Functional Description
              1. 5.2.2.1.5.2.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.1.5.2.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.1.5.2.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.1.5.2.3 VTM VID Voltage Domains
              4. 5.2.2.1.5.2.4 VTM Clocking
              5. 5.2.2.1.5.2.5 VTM Retention Interface
              6. 5.2.2.1.5.2.6 VTM ECC Aggregator
              7. 5.2.2.1.5.2.7 VTM Programming Model
                1. 5.2.2.1.5.2.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.1.5.2.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.1.5.2.7.3 Sensors Programming Sequences
              8. 5.2.2.1.5.2.8 AVS-Class0
          6. 5.2.2.1.6 Integrated Low-dropout Regulator (LDO)
            1. 5.2.2.1.6.1 SDIO LDO Overview
        2. 5.2.2.2 Power Control Modules
          1. 5.2.2.2.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.2.1.1 PSC Terminology
            2. 5.2.2.2.1.2 PSC Features
            3. 5.2.2.2.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.2.1.3.1 Device Power-Management Layout
              2. 5.2.2.2.1.3.2 PSC0 LPSC Features
              3. 5.2.2.2.1.3.3 MCU_PSC0 LPSC Features
            4. 5.2.2.2.1.4 PSC: Executing State Transitions
              1. 5.2.2.2.1.4.1 Power Domain State Transitions
              2. 5.2.2.2.1.4.2 Module State Transitions
              3. 5.2.2.2.1.4.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.2.1.4.4 Recommendations for Power Domain/Module Sequencing
            5. 5.2.2.2.1.5 LPSC Dependencies Overview
          2. 5.2.2.2.2 DMSC-L Power Management Overview
            1. 5.2.2.2.2.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Device Power States and Transitions
      4. 5.2.4 Thermal Management
    3. 5.3 Reset
      1. 5.3.1 Overview
        1. 5.3.1.1 MAIN Domain Supported Resets
        2. 5.3.1.2 MCU Domain Supported Resets
        3. 5.3.1.3 Reset Terminology
        4. 5.3.1.4 Reset Architecture
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
        1. 5.3.3.1 Reset Source Status Registers
        2. 5.3.3.2 MCU_RESETSTATz Status Pin
        3. 5.3.3.3 MCU_SAFETY_ERRORn Status Pin
        4. 5.3.3.4 RESETSTATz Status Pin
        5. 5.3.3.5 PORz_OUT Status Pin
      4. 5.3.4 Reset Controls
        1. 5.3.4.1 Reset Control Registers
        2. 5.3.4.2 Reset Isolation
      5. 5.3.5 Reset Details
        1. 5.3.5.1 POR Resets
          1. 5.3.5.1.1 SW_MAIN_PORz Reset
          2. 5.3.5.1.2 MCU_PORz Reset
        2. 5.3.5.2 Warm Resets
          1. 5.3.5.2.1 MAIN Domain Warm Reset Sequence Flow
          2. 5.3.5.2.2 MAIN_RESET_REQz Reset
          3. 5.3.5.2.3 SW_MAIN_WARMRSTz Reset
          4. 5.3.5.2.4 MCU_RESETz Reset
          5. 5.3.5.2.5 SW_MCU_WARMRSTz Reset
          6. 5.3.5.2.6 Warm Resets
        3. 5.3.5.3 DMSC-L Resets
          1. 5.3.5.3.1 DMSC_COLD_OUT_RST_n MAIN Reset
          2. 5.3.5.3.2 DMSC_WARM_OUT_RST_n MAIN Reset
          3. 5.3.5.3.3 DMSC_COLD_OUT_RST_n MCU Reset
        4. 5.3.5.4 VTM Thermal Alert Reset
        5. 5.3.5.5 MAIN ESM_ERRORz Reset
        6. 5.3.5.6 MCU ESM_ERRORz Reset
        7. 5.3.5.7 Reset - High Heating Value (HHV)
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 335
          3. 5.4.3.1.3 OBSCLK0 Pin
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillator with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 MCU Domain PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRACF Type Output Clocks
              2. 5.4.5.4.1.2.2 PLL Lock
              3. 5.4.5.4.1.2.3 HSDIVIDER
              4. 5.4.5.4.1.2.4 ICG Module
              5. 5.4.5.4.1.2.5 PLL Power Down
              6. 5.4.5.4.1.2.6 PLL Calibration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 Clock Synthesis Inputs to the PLLs
          2. 5.4.5.5.2 Clock Output Parameter
          3. 5.4.5.5.3 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
  8. 6 Processors and Accelerators
    1. 6.1 Arm Cortex-A53 Subsystem (A53SS)
      1. 6.1.1 A53SS Overview
        1. 6.1.1.1 A53SS Introduction
        2. 6.1.1.2 A53SS Features
      2. 6.1.2 A53SS Integration
      3. 6.1.3 A53SS Functional Description
        1. 6.1.3.1  A53SS Block Diagram
        2. 6.1.3.2  Arm Cortex-A53 Cluster
        3. 6.1.3.3  A53SS Interfaces and Async Bridges
        4. 6.1.3.4  A53SS Interrupts
          1. 6.1.3.4.1 A53SS Interrupt Inputs
          2. 6.1.3.4.2 A53SS Interrupt Outputs
        5. 6.1.3.5  A53SS Power Management and Clocking
          1. 6.1.3.5.1 A53SS Power Management
          2. 6.1.3.5.2 A53SS Clocking
        6. 6.1.3.6  A53SS Debug
        7. 6.1.3.7  A53SS Global and Debug Timestamps
        8. 6.1.3.8  A53SS Watchdog
        9. 6.1.3.9  A53SS Functional Safety - ECC Error Injection Support
          1. 6.1.3.9.1 A53 ECC Aggregators During Low Power States
          2. 6.1.3.9.2 Auto-initialization of Memories
          3. 6.1.3.9.3 A53 SRAM Safety
          4. 6.1.3.9.4 A53 SRAM ECC Aggregator Configurations
        10. 6.1.3.10 A53SS Boot
        11. 6.1.3.11 A53SS Interprocessor Communication
    2. 6.2 Arm Cortex R5F Subsystem (R5FSS)
      1. 6.2.1 R5FSS Overview
        1. 6.2.1.1 R5FSS Features
        2. 6.2.1.2 R5FSS Not Supported Features
      2. 6.2.2 R5FSS Integration
        1. 6.2.2.1 R5FSS Integration in MAIN Domain
      3. 6.2.3 R5FSS Functional Description
        1. 6.2.3.1  R5FSS Block Diagram
        2. 6.2.3.2  R5FSS Cortex-R5F Core
          1. 6.2.3.2.1 L1 Caches
          2. 6.2.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.2.3.2.3 R5FSS Special Signals
        3. 6.2.3.3  R5FSS Interfaces
          1. 6.2.3.3.1 Initiator Interfaces
          2. 6.2.3.3.2 Target Interfaces
        4. 6.2.3.4  R5FSS Power, Clocking and Reset
          1. 6.2.3.4.1 R5FSS Power
          2. 6.2.3.4.2 R5FSS Clocking
          3. 6.2.3.4.3 R5FSS Reset
        5. 6.2.3.5  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.2.3.5.1 VIM Overview
          2. 6.2.3.5.2 VIM Interrupt Inputs
          3. 6.2.3.5.3 VIM Interrupt Outputs
          4. 6.2.3.5.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.2.3.5.5 VIM Interrupt Prioritization
          6. 6.2.3.5.6 VIM ECC Support
          7. 6.2.3.5.7 VIM IDLE State
          8. 6.2.3.5.8 VIM Interrupt Handling
            1. 6.2.3.5.8.1 Servicing IRQ Through Vector Interface
            2. 6.2.3.5.8.2 Servicing IRQ Through MMR Interface
            3. 6.2.3.5.8.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.2.3.5.8.4 Servicing FIQ
            5. 6.2.3.5.8.5 Servicing FIQ (Alternative)
        6. 6.2.3.6  R5FSS Region Address Translation (RAT)
          1. 6.2.3.6.1 R5FSS Usage
          2. 6.2.3.6.2 RAT Function
          3. 6.2.3.6.3 How to use RAT Block in R5
          4. 6.2.3.6.4 Example of Using RAT to Access Full 36b SoC Memory Map
        7. 6.2.3.7  R5FSS ECC Support
        8. 6.2.3.8  R5FSS Memory View
        9. 6.2.3.9  R5FSS Interrupts
        10. 6.2.3.10 R5FSS Debug and Trace
        11. 6.2.3.11 R5FSS Boot Options
        12. 6.2.3.12 R5FSS Core Memory ECC Events
    3. 6.3 Cortex-M4F Subsystem (MCU_M4FSS)
      1. 6.3.1 MCU_M4FSS Overview
        1. 6.3.1.1 MCU_M4FSS Features
        2. 6.3.1.2 MCU_M4FSS Not Supported Features
      2. 6.3.2 MCU_M4FSS Integration
      3. 6.3.3 MCU_M4FSS Functional Description
        1. 6.3.3.1  MCU_M4FSS Block Diagram
        2. 6.3.3.2  MCU_M4FSS Processor
        3. 6.3.3.3  MCU_M4FSS Internal RAMs
        4. 6.3.3.4  MCU_M4FSS Interfaces
        5. 6.3.3.5  MCU_M4FSS Power, Clocking and Reset
          1. 6.3.3.5.1 MCU_M4FSS Power
          2. 6.3.3.5.2 MCU_M4FSS Clocking
          3. 6.3.3.5.3 MCU_M4FSS Reset
        6. 6.3.3.6  MCU_M4FSS Memory View
        7. 6.3.3.7  MCU_M4FSS RAT
          1. 6.3.3.7.1 Why RAT is needed for M4F
          2. 6.3.3.7.2 RAT Function
          3. 6.3.3.7.3 How to use RAT Block in Blazar M4F
        8. 6.3.3.8  MCU_M4FSS ECC Support
        9. 6.3.3.9  MCU_M4FSS Interrupts
        10. 6.3.3.10 MCU_M4FSS Debug and Trace
        11. 6.3.3.11 MCU_M4FSS Time Sync
        12. 6.3.3.12 MCU_M4FSS SysTick
        13. 6.3.3.13 MCU_M4FSS Initialization
    4. 6.4 Programmable Real-Time Unit and Industrial Communication Subsystem - Gigabit (PRU_ICSSG)
      1. 6.4.1  PRU_ICSSG Overview
        1. 6.4.1.1 PRU_ICSSG Key Features
        2. 6.4.1.2 Not Supported Features
      2. 6.4.2  PRU_ICSSG Environment
        1. 6.4.2.1 PRU_ICSSG Internal Pinmux
          1.        PRU_ICSSG I/O Signals
        2. 6.4.2.2 PRU_ICSSG Fast GPIO pins
      3. 6.4.3  PRU_ICSSG Integration
        1.       PRU_ICSSG Clocks
      4. 6.4.4  PRU_ICSSG Top Level Resources Functional Description
        1. 6.4.4.1 PRU_ICSSG Reset Management
        2. 6.4.4.2 PRU_ICSSG Power and Clock Management
          1. 6.4.4.2.1 PRU_ICSSG CORE Clock Generation
          2. 6.4.4.2.2 PRU_ICSSG Idle State
          3. 6.4.4.2.3 PRU_ICSSG Protect
          4. 6.4.4.2.4 Module Clock Configurations at PRU_ICSSG Top Level
        3. 6.4.4.3 Other PRU_ICSSG Module Functional Registers at Subsystem Level
        4. 6.4.4.4 PRU_ICSSG Memory Maps
          1. 6.4.4.4.1 PRU_ICSSG Local Memory Map
            1. 6.4.4.4.1.1 PRU_ICSSG Local Instruction Memory Map
            2. 6.4.4.4.1.2 PRU_ICSSG Local Data Memory Map
          2. 6.4.4.4.2 PRU_ICSSG Global Memory Map
      5. 6.4.5  PRU_ICSSG PRU Cores
        1. 6.4.5.1 PRU Cores Overview
        2. 6.4.5.2 PRU Cores Functional Description
          1. 6.4.5.2.1 PRUs Constant Table
          2. 6.4.5.2.2 PRU Module Interface
            1. 6.4.5.2.2.1 Real-Time Status Interface Mapping (R31): Interrupt Events Input
            2. 6.4.5.2.2.2 Event Interface Mapping (R31): PRU System Events
            3. 6.4.5.2.2.3 General-Purpose Inputs (R31): Enhanced PRU GP Module
              1. 6.4.5.2.2.3.1 PRU EGPIs Direct Input
              2. 6.4.5.2.2.3.2 PRU EGPIs 16-Bit Parallel Capture
              3. 6.4.5.2.2.3.3 PRU EGPIs 28-Bit Shift In
                1. 6.4.5.2.2.3.3.1 PRU EGPI Programming Model
              4. 6.4.5.2.2.3.4 General-Purpose Outputs (R30): Enhanced PRU GP Module
                1. 6.4.5.2.2.3.4.1 PRU EGPOs Direct Output
                2. 6.4.5.2.2.3.4.2 PRU EGPO Shift Out
                  1. 4.5.2.2.3.4.2.1 PRU EGPO Programming Model
              5. 6.4.5.2.2.3.5 Sigma Delta (SD) Decimation Filtering
                1. 6.4.5.2.2.3.5.1 Sigma Delta Block Diagram and Signals
                2. 6.4.5.2.2.3.5.2 PRU R30 / R31 Interface
                3. 6.4.5.2.2.3.5.3 Sigma Delta Description
                4. 6.4.5.2.2.3.5.4 Sigma Delta Basic Programming Example
              6. 6.4.5.2.2.3.6 Three Channel Peripheral Interface
                1. 6.4.5.2.2.3.6.1 Peripheral Interface Block Diagram and Signal Configuration
                2. 6.4.5.2.2.3.6.2 PRU R30 and R31 Interface
                3. 6.4.5.2.2.3.6.3 Clock Generation
                  1. 4.5.2.2.3.6.3.1 Configuration
                  2. 4.5.2.2.3.6.3.2 Clock Output Start Conditions
                    1. 5.2.2.3.6.3.2.1 TX Mode (RX_EN = 0)
                    2. 5.2.2.3.6.3.2.2 RX Mode (RX_EN = 1)
                  3. 4.5.2.2.3.6.3.3 Stop Conditions
                4. 6.4.5.2.2.3.6.4 Three Peripheral Mode Basic Programming Model
                  1. 4.5.2.2.3.6.4.1 Clock Generation
                  2. 4.5.2.2.3.6.4.2 TX - Single Shot
                  3. 4.5.2.2.3.6.4.3 TX - Continuous FIFO Loading
                  4. 4.5.2.2.3.6.4.4 RX - Auto Arm or Non-Auto Arm
        3. 6.4.5.3 PRU_ICSSG RAM Index Allocation
      6. 6.4.6  PRU_ICSSG Broadside Accelerators
        1. 6.4.6.1 PRU_ICSSG Broadside Accelerators Overview
        2. 6.4.6.2 PRU_ICSSG Data Processing Accelerators Functional
          1. 6.4.6.2.1  PRU Multiplier with Accumulation (MPY/MAC)
            1. 6.4.6.2.1.1 PRU MAC Operations
              1. 6.4.6.2.1.1.1 PRU versus MAC Interface
              2. 6.4.6.2.1.1.2 Multiply only mode(default state), MAC_MODE = 0
                1. 6.4.6.2.1.1.2.1 Programming PRU MAC in "Multiply-ONLY" mode
              3. 6.4.6.2.1.1.3 Multiply and Accumulate Mode, MAC_MODE = 1
                1. 6.4.6.2.1.1.3.1 Programming PRU MAC in Multiply and Accumulate Mode
          2. 6.4.6.2.2  PRU CRC16/32 Module
            1. 6.4.6.2.2.1 PRU and CRC16/32 Interface
            2. 6.4.6.2.2.2 CRC Programming Model
            3. 6.4.6.2.2.3 PRU and CRC16/32 Interface (R9:R2)
          3. 6.4.6.2.3  PRU_ICSSG Scratch Pad Memory
            1. 6.4.6.2.3.1 PRU0/1 Scratch Pad Overview
            2. 6.4.6.2.3.2 PRU0 /1 Scratch Pad Operations
              1. 6.4.6.2.3.2.1 Optional XIN/XOUT Shift
              2. 6.4.6.2.3.2.2 Scratch Pad Operations Examples
          4. 6.4.6.2.4  PRU_ICSSG IPC Scratch Pad Memory
          5. 6.4.6.2.5  PRU_ICSSG Broadside (BS) RAM
            1. 6.4.6.2.5.1 Programming the BS RAM
          6. 6.4.6.2.6  PRU_ICSSG SUM32 Hardware Accelerator
          7. 6.4.6.2.7  PRU_ICSSG Byte Swap (BSWAP)
            1. 6.4.6.2.7.1 Byte Order Swap Function
            2. 6.4.6.2.7.2 4_8 Function
            3. 6.4.6.2.7.3 4_16 Function
          8. 6.4.6.2.8  PRU_ICSSG Task Manager
            1. 6.4.6.2.8.1 Task Manager General Purpose Mode
              1. 6.4.6.2.8.1.1 Tasks and Sub-tasks
              2. 6.4.6.2.8.1.2 Task Manager Hardware Context Switching
              3. 6.4.6.2.8.1.3 Task Manager Programming Guide
            2. 6.4.6.2.8.2 Task Manager RX_TX Mode
              1. 6.4.6.2.8.2.1 RX_TX Task Manager Features
              2. 6.4.6.2.8.2.2 Tasks and Sub-tasks
          9. 6.4.6.2.9  PRU_ICSSG Spinlock
            1. 6.4.6.2.9.1 PRU0/1 and RTU_PRU0/1 Spinlock Interface
          10. 6.4.6.2.10 PRU_ICSSG Filter Data Base (FDB)
            1. 6.4.6.2.10.1 FDB Modes of operation
              1. 6.4.6.2.10.1.1 FDB LUT: Hardware operation (HSR Disabled: MII_G_RT_FDB_GEN_CFG2[5] FDB_HSR_EN = 0h)
              2. 6.4.6.2.10.1.2 FDB LUT: Hardware operation (HSR Enabled: MII_G_RT_FDB_GEN_CFG2[5] FDB_HSR_EN = 1h)
              3. 6.4.6.2.10.1.3 8KB/16KB Generic broadside RAM mode of operation
                1. 6.4.6.2.10.1.3.1 Broadside (BS) Mapping
              4. 6.4.6.2.10.1.4 FDB General purpose compare mode operation
        3. 6.4.6.3 PRU_ICSSG Data Movement Accelerators Functional
          1. 6.4.6.3.1 PRU_ICSSG XFR2VBUS Hardware Accelerator
            1. 6.4.6.3.1.1 Blocking Conditions
            2. 6.4.6.3.1.2 Read Operation with Auto Disabled
            3. 6.4.6.3.1.3 Read Operation with Auto Enabled
            4. 6.4.6.3.1.4 Write Operation with Auto Disabled
            5. 6.4.6.3.1.5 RTU_PRU/ PRU to XFR2VBUS Interface
            6. 6.4.6.3.1.6 XFR2VBUS Programming Model
          2. 6.4.6.3.2 PRU_ICSSG XFRDMA Functional Operation
            1. 6.4.6.3.2.1 XFRDMA: XFR Bus
              1. 6.4.6.3.2.1.1 XFRDMA: XFR Status
              2. 6.4.6.3.2.1.2 XFRDMA: XFR Bus XOUT
              3. 6.4.6.3.2.1.3 XFRDMA: XFR Bus XOUXFRDMA Functional Operation T Alignment
              4. 6.4.6.3.2.1.4 XFRDMA: XFR Bus XIN
                1. 6.4.6.3.2.1.4.1 XFRDMA: XFR Bus XIN Alignment
            2. 6.4.6.3.2.2 XFRDMA: PSI-L Bus
              1. 6.4.6.3.2.2.1 PRU XFRPSI Mapping
            3. 6.4.6.3.2.3 XFRDMA: Temporary FIFOs
              1. 6.4.6.3.2.3.1 XFRDMA: FIFO Stalls
          3. 6.4.6.3.3 PRU_ICSSG XFR2TR Ring Accelerator
            1. 6.4.6.3.3.1 XFR2TR Programming Model
      7. 6.4.7  PRU_ICSSG Local INTC
        1. 6.4.7.1 PRU_ICSSG Interrupt Controller Functional Description
          1. 6.4.7.1.1 PRU_ICSSG Interrupt Controller Events
          2. 6.4.7.1.2 PRU_ICSSG Interrupt Controller System Events Flow
            1. 6.4.7.1.2.1 PRU_ICSSG Interrupt Processing
              1. 6.4.7.1.2.1.1 PRU_ICSSG Interrupt Enabling
            2. 6.4.7.1.2.2 PRU_ICSSG Interrupt Status Checking
            3. 6.4.7.1.2.3 PRU_ICSSG Interrupt Channel Mapping
              1. 6.4.7.1.2.3.1 PRU_ICSSG Host Interrupt Mapping
              2. 6.4.7.1.2.3.2 PRU_ICSSG Interrupt Prioritization
            4. 6.4.7.1.2.4 PRU_ICSSG Interrupt Nesting
            5. 6.4.7.1.2.5 PRU_ICSSG Interrupt Status Clearing
          3. 6.4.7.1.3 PRU_ICSSG Interrupt Disabling
        2. 6.4.7.2 PRU_ICSSG Interrupt Controller Basic Programming Model
        3. 6.4.7.3 PRU_ICSSG Interrupt Requests Mapping
      8. 6.4.8  PRU_ICSSG UART Module
        1. 6.4.8.1 PRU_ICSSG UART Overview
        2. 6.4.8.2 PRU_ICSSG UART Environment
          1. 6.4.8.2.1 PRU_ICSSG UART Pin Multiplexing
          2. 6.4.8.2.2 PRU_ICSSG UART Signal Descriptions
          3. 6.4.8.2.3 PRU_ICSSG UART Protocol Description and Data Format
            1. 6.4.8.2.3.1 PRU_ICSSG UART Transmission Protocol
            2. 6.4.8.2.3.2 PRU_ICSSG UART Reception Protocol
            3. 6.4.8.2.3.3 PRU_ICSSG UART Data Format
              1. 6.4.8.2.3.3.1 Frame Formatting
          4. 6.4.8.2.4 PRU_ICSSG UART Clock Generation and Control
        3. 6.4.8.3 PRU_ICSSG UART Functional Description
          1. 6.4.8.3.1 PRU_ICSSG UART Functional Block Diagram
          2. 6.4.8.3.2 PRU_ICSSG UART Reset Considerations
            1. 6.4.8.3.2.1 PRU_ICSSG UART Software Reset Considerations
            2. 6.4.8.3.2.2 PRU_ICSSG UART Hardware Reset Considerations
          3. 6.4.8.3.3 PRU_ICSSG UART Power Management
          4. 6.4.8.3.4 PRU_ICSSG UART Interrupt Support
            1. 6.4.8.3.4.1 PRU_ICSSG UART Interrupt Events and Requests
            2. 6.4.8.3.4.2 PRU_ICSSG UART Interrupt Multiplexing
          5. 6.4.8.3.5 630
          6. 6.4.8.3.6 PRU_ICSSG UART DMA Event Support
          7. 6.4.8.3.7 PRU_ICSSG UART Operations
            1. 6.4.8.3.7.1 PRU_ICSSG UART FIFO Modes
              1. 6.4.8.3.7.1.1 PRU_ICSSG UART FIFO Interrupt Mode
              2. 6.4.8.3.7.1.2 PRU_ICSSG UART FIFO Poll Mode
            2. 6.4.8.3.7.2 PRU_ICSSG UART Autoflow Control
              1. 6.4.8.3.7.2.1 PRU_ICSSG UART Signal UART0_RTS Behavior
              2. 6.4.8.3.7.2.2 PRU_ICSSG UART Signal UART0_CTS Behavior
            3. 6.4.8.3.7.3 PRU_ICSSG UART Loopback Control
          8. 6.4.8.3.8 PRU_ICSSG UART Emulation Considerations
          9. 6.4.8.3.9 PRU_ICSSG UART Exception Processing
            1. 6.4.8.3.9.1 PRU_ICSSG UART Divisor Latch Not Programmed
            2. 6.4.8.3.9.2 Changing Operating Mode During Busy Serial Communication of PRU_ICSSG UART
      9. 6.4.9  PRU_ICSSG ECAP Module
        1. 6.4.9.1 PRU_ICSSG ECAP Functional Description
      10. 6.4.10 PRU_ICSSG PWM Module
        1. 6.4.10.1 PRU_ICSSG PWM Supported Features
        2. 6.4.10.2 PRU_ICSSG PWM States Overview
        3. 6.4.10.3 PRU_ICSSG PWM Trip State Logic
        4. 6.4.10.4 PRU_ICSSG PWM Glitch Filter
      11. 6.4.11 PRU_ICSSG MII_G_RT Module
        1. 6.4.11.1 PRU_ICSSG MII_G_RT Introduction
          1. 6.4.11.1.1 PRU_ICSSG MII_G_RT Features
          2. 6.4.11.1.2 Unsupported Features
          3. 6.4.11.1.3 PRU_ICSSG MII_G_RT Block Diagram
        2. 6.4.11.2 MII_G_RT Functional Description
          1. 6.4.11.2.1 MII_G_RT Data Path Configuration
            1. 6.4.11.2.1.1 Auto-forward with Optional PRU Snoop
            2. 6.4.11.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications
            3. 6.4.11.2.1.3 32-byte Double Buffer or Ping-Pong Processing
          2. 6.4.11.2.2 MII_G_RT Definition and Terms
            1. 6.4.11.2.2.1 MII_G_RT Data Frame Structure
            2. 6.4.11.2.2.2 PRU R30 and R31
            3. 6.4.11.2.2.3 RX and TX L1 FIFO Data Movement
            4. 6.4.11.2.2.4 Receive CRC Computation
            5. 6.4.11.2.2.5 Transmit CRC Computation
            6. 6.4.11.2.2.6 Transmit CRC Computation for fragmented frames
          3. 6.4.11.2.3 RX MII Interface
            1. 6.4.11.2.3.1 RX MII Receive Data Latch
            2. 6.4.11.2.3.2 RX MII Start of Frame Detection
            3. 6.4.11.2.3.3 CRC Error Detection
            4. 6.4.11.2.3.4 RX Error Detection and Action
            5. 6.4.11.2.3.5 RX Data Path Options to PRU
            6. 6.4.11.2.3.6 RX MII Port → RX L1 FIFO → PRU
            7. 6.4.11.2.3.7 RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU
              1. 6.4.11.2.3.7.1 RX L2 Status in mode 0, none IET mode (when ICSS_G_CFG[2] RX_L2_G_EN= 0h)
              2. 6.4.11.2.3.7.2 677
              3. 6.4.11.2.3.7.3 RX L2 Status for IET Type 1/Type 2 (when MII_G_RT_ICSS_G_CFG[2] RX_L2_G_EN = 1h)
              4. 6.4.11.2.3.7.4 679
              5. 6.4.11.2.3.7.5 Broadside Stitch FIFO
              6. 6.4.11.2.3.7.6 MII_G_RT RX Classifier
                1. 6.4.11.2.3.7.6.1 RX Rate Counter Block
                2. 6.4.11.2.3.7.6.2 RX Rate Hit Mapping
                3. 6.4.11.2.3.7.6.3 Traffic Class Selector Block
                4. 6.4.11.2.3.7.6.4 PRU_ICSSG RX L2 Filter Block
                  1. 4.11.2.3.7.6.4.1 PRU_ICSSG RX L2 Filter Operation
                  2. 4.11.2.3.7.6.4.2 PRU_ICSSG RX L2 Filter - Type 1 (MAC Filter) Operation
                  3. 4.11.2.3.7.6.4.3 PRU_ICSSG RX L2 Filter - Type 3 (Content Filter) Operation
                  4. 4.11.2.3.7.6.4.4 PRU_ICSSG RX L2 Filter - Type 3 (Content Filter) Auto Restart operation
                  5. 4.11.2.3.7.6.4.5 RX SA Hash
                  6. 4.11.2.3.7.6.4.6 RX Connection Hash
          4. 6.4.11.2.4 PRU_ICSSG TX MII Interface
            1. 6.4.11.2.4.1 TX Data Path Options to TX L1 FIFO
              1. 6.4.11.2.4.1.1 PRU → TX L1 FIFO → TX MII Port
                1. 6.4.11.2.4.1.1.1 TX L2 FIFO Features
                2. 6.4.11.2.4.1.1.2 696
                3. 6.4.11.2.4.1.1.3 TX Insertion
                4. 6.4.11.2.4.1.1.4 TX Preemption
                  1. 4.11.2.4.1.1.4.1 TX Preemption Programming Model
              2. 6.4.11.2.4.1.2 RX L1 FIFO → TX L1 FIFO (Direct Connection) → TX MII Port
          5. 6.4.11.2.5 PRU R31 Command Interface
          6. 6.4.11.2.6 Other Configuration Options
            1. 6.4.11.2.6.1 Nibble and Byte Order
            2. 6.4.11.2.6.2 MII_G_RT Preamble Source
            3. 6.4.11.2.6.3 PRU and MII Port Multiplexer
              1. 6.4.11.2.6.3.1 Receive Multiplexer
              2. 6.4.11.2.6.3.2 Transmit Multiplexer
            4. 6.4.11.2.6.4 RX L2 Scratch Pad
        3. 6.4.11.3 PRU_ICSSG PA_STATS Module
          1. 6.4.11.3.1 Statistics Page
          2. 6.4.11.3.2 Statistics Collection Modes
            1. 6.4.11.3.2.1 Manual Read Mode
          3. 6.4.11.3.3 Clock Stop
      12. 6.4.12 PRU_ICSSG MII MDIO Module
        1. 6.4.12.1 PRU_ICSSG MII MDIO Overview
        2. 6.4.12.2 PRU_ICSSG MII MDIO Functional Description
          1. 6.4.12.2.1 MDIO Clause 22 Frame Formats
            1. 6.4.12.2.1.1 PRU-ICSSG MDIO Control and Interface Signals
          2. 6.4.12.2.2 MDIO Clause 45 Frame Formats
          3. 6.4.12.2.3 PRU_ICSSG MII MDIO Interractions
          4. 6.4.12.2.4 PRU_ICSSG MII MDIO Interrupts
            1. 6.4.12.2.4.1 Normal Mode ([30]STATECHANGEMODE = 0h)
            2. 6.4.12.2.4.2 State Change Mode ([30]STATECHANGEMODE = 1h)
          5. 6.4.12.2.5 Manual Mode
        3. 6.4.12.3 PRU_ICSSG MII MDIO Receive/Transmit Frame Host Software Interface
      13. 6.4.13 PRU_ICSSG IEP
        1. 6.4.13.1 PRU_ICSSG IEP Overview
        2. 6.4.13.2 PRU_ICSSG IEP Functional Description
          1. 6.4.13.2.1 PRU_ICSSG IEP Clock Generation
          2. 6.4.13.2.2 PRU_ICSSG IEP Timer
            1. 6.4.13.2.2.1 PRU_ICSSG IEP Timer Features
          3. 6.4.13.2.3 32-Bit Shadow Mode
          4. 6.4.13.2.4 PRU_ICSSG IEP Timer Basic Programming Sequence
          5. 6.4.13.2.5 Industrial Ethernet Mapping
          6. 6.4.13.2.6 PRU_ICSSG IEP Sync0/Sync1 Module
            1. 6.4.13.2.6.1 PRU_ICSSG IEP Sync0/Sync1 Features
            2. 6.4.13.2.6.2 PRU_ICSSG IEP Sync0/Sync1 Generation Modes
          7. 6.4.13.2.7 PRU_ICSSG IEP WatchDog
          8. 6.4.13.2.8 PRU_ICSSG IEP DIGIO
            1. 6.4.13.2.8.1 PRU_ICSSG IEP DIGIO Features
            2. 6.4.13.2.8.2 741
            3. 6.4.13.2.8.3 PRU_ICSSG IEP DIGIO Block Diagrams
            4. 6.4.13.2.8.4 PRU_ICSSG IEP Basic Programming Model
  9. 7 Interprocessor Communication (IPC)
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 DDR Subsystem (DDRSS)
      1. 8.1.1 DDRSS Overview
        1. 8.1.1.1 DDRSS Not Supported Features
      2. 8.1.2 DDRSS Environment
      3. 8.1.3 DDRSS Integration
        1. 8.1.3.1 DDRSS Integration in MAIN Domain
      4. 8.1.4 DDRSS Functional Description
        1. 8.1.4.1 Class of Service (CoS)
        2. 8.1.4.2 AXI Write Data All-Strobes
        3. 8.1.4.3 Inline ECC for SDRAM Data
          1. 8.1.4.3.1 ECC Cache
          2. 8.1.4.3.2 ECC Cache Flush
          3. 8.1.4.3.3 ECC Statistics
        4. 8.1.4.4 Address Alias Prevention
        5. 8.1.4.5 AXI Bus Timeout
        6. 8.1.4.6 DDRSS Interrupts
        7. 8.1.4.7 DDRSS Memory Regions
        8. 8.1.4.8 DDRSS Dynamic Frequency Change Interface
        9. 8.1.4.9 DDR Controller Functional Description
          1. 8.1.4.9.1 DDR PHY Interface (DFI)
          2. 8.1.4.9.2 Command Queue
            1. 8.1.4.9.2.1 Placement Logic
            2. 8.1.4.9.2.2 Command Selection Logic
          3. 8.1.4.9.3 Transaction Processing
          4. 8.1.4.9.4 Paging Policy
          5. 8.1.4.9.5 DDR Controller Initialization
    2. 8.2 Region-based Address Translation (RAT) Module
      1. 8.2.1 RAT Functional Description
        1. 8.2.1.1 RAT Availability
        2. 8.2.1.2 RAT Operation
        3. 8.2.1.3 RAT Error Logging
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GICSS)
        1. 9.2.1.1 GICSS Overview
          1. 9.2.1.1.1 GICSS Features
          2. 9.2.1.1.2 GICSS Not Supported Features
        2. 9.2.1.2 GICSS Integration
        3. 9.2.1.3 GICSS Functional Description
          1. 9.2.1.3.1 GICSS Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GICSS Interrupt Types
          4. 9.2.1.3.4 GICSS Interfaces
          5. 9.2.1.3.5 GICSS Interrupt Outputs
          6. 9.2.1.3.6 GICSS ECC Support
          7. 9.2.1.3.7 GICSS AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GICSS Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GICSS0_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 MCU_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
    4. 9.4 Interrupt Sources
      1. 9.4.1 Interrupts (Inputs)
      2. 9.4.2 Interrupts (Outputs)
    5. 9.5 Time Sync and Compare Interrupt Events
      1. 9.5.1 CMPEVT_INTRTR0 Interrupt Map
      2. 9.5.2 TIMESYNC_INTRTR0 Interrupt Map
  12. 10Time Sync
    1. 10.1 Time Sync Module (CPTS)
      1. 10.1.1 CPTS Overview
        1. 10.1.1.1 CPTS Features
        2. 10.1.1.2 CPTS Not Supported Features
      2. 10.1.2 CPTS Integration
      3. 10.1.3 CPTS Functional Description
        1. 10.1.3.1  CPTS Architecture
        2. 10.1.3.2  CPTS Initialization
        3. 10.1.3.3  32-bit Time Stamp Value
        4. 10.1.3.4  64-bit Time Stamp Value
          1. 10.1.3.4.1 64-Bit Timestamp Nudge
          2. 10.1.3.4.2 64-bit Timestamp PPM
        5. 10.1.3.5  Event FIFO
        6. 10.1.3.6  Timestamp Compare Output
          1. 10.1.3.6.1 Non-Toggle Mode
          2. 10.1.3.6.2 Toggle Mode
        7. 10.1.3.7  Timestamp Sync Output
        8. 10.1.3.8  Timestamp GENF Output
          1. 10.1.3.8.1 GENFn Nudge
          2. 10.1.3.8.2 GENFn PPM
        9. 10.1.3.9  Time Sync Events
          1. 10.1.3.9.1 Time Stamp Push Event
          2. 10.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 10.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 10.1.3.9.4 Hardware Time Stamp Push Event
        10. 10.1.3.10 Timestamp Compare Event
        11. 10.1.3.11 CPTS Interrupt Handling
    2. 10.2 Timer Manager
      1. 10.2.1 Timer Manager Overview
        1. 10.2.1.1 Timer Manager Features
        2. 10.2.1.2 Timer Manager Not Supported Features
      2. 10.2.2 Timer Manager Integration
      3. 10.2.3 Timer Manager Functional Description
        1. 10.2.3.1 Timer Manager Function Overview
        2. 10.2.3.2 Timer Counter
          1. 10.2.3.2.1 Timer Counter Rollover
        3. 10.2.3.3 Timer Control Module (FSM)
        4. 10.2.3.4 Timer Reprogramming
          1. 10.2.3.4.1 Periodic Hardware Timers
        5. 10.2.3.5 Event FIFO
        6. 10.2.3.6 Timer Manager Unmapped Events mapping
      4. 10.2.4 Timer Manager Programming Guide
        1. 10.2.4.1 Timer Manager Low-level Programming Models
          1. 10.2.4.1.1 Surrounding Modules Global Initialization
          2. 10.2.4.1.2 Initialization Sequence
          3. 10.2.4.1.3 Real-time Operating Requirements
            1. 10.2.4.1.3.1 Timer Touch
            2. 10.2.4.1.3.2 Timer Disable
            3. 10.2.4.1.3.3 Timer Enable
          4. 10.2.4.1.4 Power Up/Power Down Sequence
    3. 10.3 Time Sync and Compare Events
      1. 10.3.1 Time Sync Architecture
        1. 10.3.1.1 Time Sync Architecture Overview
      2. 10.3.2 Time Sync Routers
        1. 10.3.2.1 Time Sync Routers Overview
        2. 10.3.2.2 Time Sync Routers Integration
          1. 10.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 10.3.2.2.2 CMPEVT_INTRTR0 Integration
      3. 10.3.3 Time Sync Event Sources
  13. 11Data Movement Architecture
    1. 11.1 Data Movement Architecture Overview
      1. 11.1.1 Overview
        1. 11.1.1.1 Ring Accelerator (RINGACC)
        2. 11.1.1.2 Secure Proxy (SEC_PROXY)
        3. 11.1.1.3 Interrupt Aggregator (INTAGGR)
        4. 11.1.1.4 Packet DMA (PKTDMA)
          1. 11.1.1.4.1 PKTDMA Submodule Descriptions
            1. 11.1.1.4.1.1  Bus Interface Unit
            2. 11.1.1.4.1.2  Config CR
            3. 11.1.1.4.1.3  Configuration Registers
              1. 11.1.1.4.1.3.1 RX State Mapping
              2. 11.1.1.4.1.3.2 TX State Mapping
            4. 11.1.1.4.1.4  Tx Packet DMA Unit
            5. 11.1.1.4.1.5  Tx Packet Coherency Unit
            6. 11.1.1.4.1.6  Tx Per Channel Buffers
            7. 11.1.1.4.1.7  Rx Per Channel Buffers
            8. 11.1.1.4.1.8  Rx Packet DMA Unit
            9. 11.1.1.4.1.9  Rx Packet Coherency Unit
            10. 11.1.1.4.1.10 Event Handler
          2. 11.1.1.4.2 Channel Classes
        5. 11.1.1.5 Block Copy DMA (BCDMA)
          1. 11.1.1.5.1 BCDMA Submodule Descriptions
            1. 11.1.1.5.1.1  Bus Interface Unit
            2. 11.1.1.5.1.2  Config CR
            3. 11.1.1.5.1.3  Configuration Registers
              1. 11.1.1.5.1.3.1 BCDMA Mapping Table
            4. 11.1.1.5.1.4  Read Unit(s)
            5. 11.1.1.5.1.5  TR Coherency Unit
            6. 11.1.1.5.1.6  Per-Copy-Channel Buffers
            7. 11.1.1.5.1.7  Tx Per-Split-Channel Buffers
            8. 11.1.1.5.1.8  Rx Per-Split-Channel Buffers
            9. 11.1.1.5.1.9  Write Unit(s)
            10. 11.1.1.5.1.10 Event Coherency Unit
            11. 11.1.1.5.1.11 Event Handler
          2. 11.1.1.5.2 Channel Classes
      2. 11.1.2 Definition of Terms
      3. 11.1.3 DMSS Hardware/Software Interface
        1. 11.1.3.1 Data Buffers
        2. 11.1.3.2 Descriptors
          1. 11.1.3.2.1 Host Packet Descriptor
          2. 11.1.3.2.2 Host Buffer Descriptor
          3. 11.1.3.2.3 Transfer Request Descriptor
        3. 11.1.3.3 Transfer Request Record
          1. 11.1.3.3.1 Overview
          2. 11.1.3.3.2 Addressing Algorithm
            1. 11.1.3.3.2.1 Linear Addressing (Forward)
          3. 11.1.3.3.3 Transfer Request Formats
          4. 11.1.3.3.4 Flags Field Definition
            1. 11.1.3.3.4.1 Type: TR Type Field
            2. 11.1.3.3.4.2 EVENT_SIZE: Event Generation Definition
            3. 11.1.3.3.4.3 TRIGGER_INFO: TR Triggers
            4. 11.1.3.3.4.4 TRIGGERX_TYPE: Trigger Type
            5. 11.1.3.3.4.5 TRIGGERX: Trigger Selection
            6. 11.1.3.3.4.6 Configuration Specific Flags Definition
          5. 11.1.3.3.5 TR Address and Size Attributes
            1. 11.1.3.3.5.1  ICNT0
            2. 11.1.3.3.5.2  ICNT1
            3. 11.1.3.3.5.3  ADDR
            4. 11.1.3.3.5.4  DIM1
            5. 11.1.3.3.5.5  ICNT2
            6. 11.1.3.3.5.6  ICNT3
            7. 11.1.3.3.5.7  DIM2
            8. 11.1.3.3.5.8  DIM3
            9. 11.1.3.3.5.9  DDIM1
            10. 11.1.3.3.5.10 DADDR
            11. 11.1.3.3.5.11 DDIM2
            12. 11.1.3.3.5.12 DDIM3
            13. 11.1.3.3.5.13 DICNT0
            14. 11.1.3.3.5.14 DICNT1
            15. 11.1.3.3.5.15 DICNT2
            16. 11.1.3.3.5.16 DICNT3
        4. 11.1.3.4 Transfer Response Record
          1. 11.1.3.4.1 STATUS Field Definition
            1. 11.1.3.4.1.1 STATUS_TYPE Definitions
              1. 11.1.3.4.1.1.1 Transfer Error
              2. 11.1.3.4.1.1.2 Aborted Error
              3. 11.1.3.4.1.1.3 Submission Error
              4. 11.1.3.4.1.1.4 Unsupported Feature
              5. 11.1.3.4.1.1.5 Transfer Exception
              6. 11.1.3.4.1.1.6 Teardown Flush
        5. 11.1.3.5 Channels
        6. 11.1.3.6 Flows
        7. 11.1.3.7 Queues
          1. 11.1.3.7.1 Queue Types
            1. 11.1.3.7.1.1 Transmit Queues
            2. 11.1.3.7.1.2 Transmit Completion Queues
            3. 11.1.3.7.1.3 Free Descriptor / Buffer Queues
            4. 11.1.3.7.1.4 Receive Queues
            5. 11.1.3.7.1.5 Ring Based Queues Implementation
      4. 11.1.4 Operational Description
        1. 11.1.4.1  Resource Allocation
        2. 11.1.4.2  PKTDMA/BCDMA - Ring Operation
          1. 11.1.4.2.1 Queue Initialization
          2. 11.1.4.2.2 Queueing Entries
          3. 11.1.4.2.3 De-queueing Entries
        3. 11.1.4.3  PKTDMA/BCDMA - Output Event Generation
        4. 11.1.4.4  PKTDMA - Transmit Channel Setup
        5. 11.1.4.5  PKTDMA - Transmit Channel Pause
        6. 11.1.4.6  PKTDMA - Transmit Channel Teardown
        7. 11.1.4.7  PKTDMA - Transmit Operation
        8. 11.1.4.8  PKTDMA - Receive Free Descriptor / Buffer Queue Setup
        9. 11.1.4.9  PKTDMA - Receive Channel Setup
        10. 11.1.4.10 PKTDMA - Receive Channel Teardown
        11. 11.1.4.11 PKTDMA - Receive Channel Pause
        12. 11.1.4.12 PKTDMA - Receive Operation
        13. 11.1.4.13 BCDMA - Block Copy Channel Setup
        14. 11.1.4.14 BCDMA - Block Copy Channel Pause
        15. 11.1.4.15 BCDMA - Block Copy Channel Teardown
        16. 11.1.4.16 BCDMA - Block Copy Operation (TR Packet)
        17. 11.1.4.17 BCDMA - Block Copy Error/Exception Handling
          1. 11.1.4.17.1 Null Icnt0 Error
          2. 11.1.4.17.2 Unsupported TR Type
          3. 11.1.4.17.3 Bus Errors
        18. 11.1.4.18 BCDMA - Split Transmit Channel Setup
        19. 11.1.4.19 BCDMA - Split Transmit Operation Pause
        20. 11.1.4.20 BCDMA - Split Transmit Channel Teardown
        21. 11.1.4.21 BCDMA - Split Transmit Operation (TR Packet)
        22. 11.1.4.22 BCDMA - Split Transmit Error / Exception Handling
          1. 11.1.4.22.1 Null Icnt0 Error
          2. 11.1.4.22.2 Unsupported TR Type
          3. 11.1.4.22.3 Bus Errors
        23. 11.1.4.23 BCDMA - Split Receive Channel Setup
        24. 11.1.4.24 BCDMA - Split Receive Channel Pause
        25. 11.1.4.25 BCDMA - Split Receive Channel Teardown
        26. 11.1.4.26 BCDMA - Split Receive Operation (TR Packet)
        27. 11.1.4.27 BCDMA - Split Receive Error / Exception Handling
          1. 11.1.4.27.1 PKTDMA Exception Conditions
            1. 11.1.4.27.1.1 Descriptor Starvation
            2. 11.1.4.27.1.2 Protocol Errors
            3. 11.1.4.27.1.3 Dropped Packets
            4. 11.1.4.27.1.4 Long Packet
          2. 11.1.4.27.2 BCDMA Exception Conditions
            1. 11.1.4.27.2.1 Reception of EOL Delimiter
            2. 11.1.4.27.2.2 EOP Asserted Prematurely (Short Packet)
            3. 11.1.4.27.2.3 EOP Asserted Late (Long Packets)
            4. 11.1.4.27.2.4 Descriptor Starvation
    2. 11.2 Data Movement Subsystem (DMSS)
      1. 11.2.1 Data Movement Subsystem (DMSS)
        1. 11.2.1.1 DMSS Overview
        2. 11.2.1.2 DMSS Integration
          1. 11.2.1.2.1 DMSS Integration Attributes
          2. 11.2.1.2.2 DMSS Clocks
          3. 11.2.1.2.3 DMSS Resets
          4. 11.2.1.2.4 DMSS Interrupt Requests
          5. 11.2.1.2.5 DMSS L2G Interrupt Inputs
          6. 11.2.1.2.6 DMSS DMA Events
          7. 11.2.1.2.7 Global Event Map
          8. 11.2.1.2.8 PSI-L System Thread Map
        3. 11.2.1.3 DMSS Functional Description
        4. 11.2.1.4 DMSS Interrupt Configuration
          1. 11.2.1.4.1 DMSS Event and Interrupt Flow
            1. 11.2.1.4.1.1 DMSS Interrupt Description
      2. 11.2.2 Ring Accelerator (RINGACC)
        1. 11.2.2.1 RINGACC Overview
          1. 11.2.2.1.1 RINGACC Features
          2. 11.2.2.1.2 RINGACC Not Supported Features
          3. 11.2.2.1.3 RINGACC Parameters
        2. 11.2.2.2 RINGACC Integration
          1. 11.2.2.2.1 RINGACC Integration Attributes
          2. 11.2.2.2.2 RINGACC Clocks
          3. 11.2.2.2.3 RINGACC Resets
          4. 11.2.2.2.4 RINGACC Interrupt Requests
          5. 11.2.2.2.5 RINGACC Outbound Events
        3. 11.2.2.3 RINGACC Functional Description
          1. 11.2.2.3.1 Block Diagram
            1. 11.2.2.3.1.1  Configuration Registers
            2. 11.2.2.3.1.2  Source Command FIFO
            3. 11.2.2.3.1.3  Source Write Data FIFO
            4. 11.2.2.3.1.4  Source Read Data FIFO
            5. 11.2.2.3.1.5  Source Write Status FIFO
            6. 11.2.2.3.1.6  Main State Machine
            7. 11.2.2.3.1.7  Destination Command FIFO
            8. 11.2.2.3.1.8  Destination Write Data FIFO
            9. 11.2.2.3.1.9  Destination Read Data FIFO
            10. 11.2.2.3.1.10 Destination Write Status FIFO
          2. 11.2.2.3.2 Events
          3. 11.2.2.3.3 Bus Error Handling
          4. 11.2.2.3.4 Monitors
            1. 11.2.2.3.4.1 Threshold Monitor
            2. 11.2.2.3.4.2 Watermark Monitor
            3. 11.2.2.3.4.3 Starvation Monitor
            4. 11.2.2.3.4.4 Statistics Monitor
            5. 11.2.2.3.4.5 Overflow
            6. 11.2.2.3.4.6 Ring Update Port
            7. 11.2.2.3.4.7 Tracing
      3. 11.2.3 Secure Proxy (SEC_PROXY)
        1. 11.2.3.1 Secure Proxy Overview
          1. 11.2.3.1.1 Secure Proxy Features
          2. 11.2.3.1.2 Secure Proxy Parameters
          3. 11.2.3.1.3 Secure Proxy Not Supported Features
        2. 11.2.3.2 Secure Proxy Integration
          1. 11.2.3.2.1 Secure Proxy Integration Attributes
          2. 11.2.3.2.2 Secure Proxy Clocks
          3. 11.2.3.2.3 Secure Proxy Resets
          4. 11.2.3.2.4 Secure Proxy Interrupt Requests
          5. 11.2.3.2.5 Secure Proxy DMA Events
        3. 11.2.3.3 Secure Proxy Functional Description
          1. 11.2.3.3.1  Targets
            1. 11.2.3.3.1.1 Ring Accelerator
          2. 11.2.3.3.2  Buffers
            1. 11.2.3.3.2.1 Proxy Credits
            2. 11.2.3.3.2.2 Proxy Private Word
            3. 11.2.3.3.2.3 Completion Byte
          3. 11.2.3.3.3  Proxy Thread Sizes
          4. 11.2.3.3.4  Proxy Thread Interleaving
          5. 11.2.3.3.5  Proxy States
          6. 11.2.3.3.6  Proxy Host Access
            1. 11.2.3.3.6.1 Proxy Host Writes
            2. 11.2.3.3.6.2 Proxy Host Reads
            3. 11.2.3.3.6.3 Buffer Accesses
            4. 11.2.3.3.6.4 Target Access
            5. 11.2.3.3.6.5 Error State
          7. 11.2.3.3.7  Permission Inheritance
          8. 11.2.3.3.8  Resource Association
          9. 11.2.3.3.9  Direction
          10. 11.2.3.3.10 Threshold Events
          11. 11.2.3.3.11 Error Events
          12. 11.2.3.3.12 Bus Error and Credits
          13. 11.2.3.3.13 Debug
      4. 11.2.4 Interrupt Aggregator (INTAGGR)
        1. 11.2.4.1 INTAGGR Overview
          1. 11.2.4.1.1 INTAGGR Features
          2. 11.2.4.1.2 INTAGGR Parameters
        2. 11.2.4.2 INTAGGR Integration
          1. 11.2.4.2.1 INTAGGR Integration Attributes
          2. 11.2.4.2.2 INTAGGR Clocks
          3. 11.2.4.2.3 INTAGGR Resets
          4. 11.2.4.2.4 INTAGGR Interrupt Requests
          5. 11.2.4.2.5 INTAGGR DMA Events
        3. 11.2.4.3 INTAGGR Functional Description
          1. 11.2.4.3.1 Submodule Descriptions
          2. 11.2.4.3.2 General Functionality
      5. 11.2.5 Packet Streaming Interface Link (PSI-L)
        1. 11.2.5.1 PSI-L Overview
        2. 11.2.5.2 PSI-L Functional Description
          1. 11.2.5.2.1 PSI-L Introduction
          2. 11.2.5.2.2 PSI-L Operation
    3. 11.3 Peripheral DMA (PDMA)
      1. 11.3.1 PDMA Controller
        1. 11.3.1.1 PDMA Overview
          1. 11.3.1.1.1 PDMA Features
            1. 11.3.1.1.1.1 PDMA0 Features
            2. 11.3.1.1.1.2 PDMA1 Features
        2. 11.3.1.2 PDMA Integration
          1. 11.3.1.2.1 PDMA Integration in MAIN Domain
        3. 11.3.1.3 PDMA Functional Description
          1. 11.3.1.3.1 PDMA Functional Blocks
            1. 11.3.1.3.1.1 Scheduler
            2. 11.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 11.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 11.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 11.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 11.3.1.3.2 PDMA General Functionality
            1. 11.3.1.3.2.1 Operational States
            2. 11.3.1.3.2.2 Clock Stop
            3. 11.3.1.3.2.3 Emulation Control
          3. 11.3.1.3.3 PDMA Events and Flow Control
            1. 11.3.1.3.3.1 Channel Types
              1. 11.3.1.3.3.1.1 X-Y FIFO Mode
              2. 11.3.1.3.3.1.2 MCAN Mode
            2. 11.3.1.3.3.2 Channel Triggering
            3. 11.3.1.3.3.3 Completion Events
          4. 11.3.1.3.4 PDMA Transmit Operation
            1. 11.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 11.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 11.3.1.3.4.3 Destination Channel Initialization
              1. 11.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 11.3.1.3.4.3.2 Static Transfer Request Setup
              3. 11.3.1.3.4.3.3 PSI-L Destination Thread Enables
            4. 11.3.1.3.4.4 Data Transfer
              1. 11.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 11.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 11.3.1.3.4.4.2 MCAN Mode Channel
                1. 11.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 11.3.1.3.4.4.3 AASRC Mode Channel
            5. 11.3.1.3.4.5 Tx Pause
            6. 11.3.1.3.4.6 Tx Teardown
            7. 11.3.1.3.4.7 Tx Channel Reset
            8. 11.3.1.3.4.8 Tx Debug/State Registers
          5. 11.3.1.3.5 PDMA Receive Operation
            1. 11.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 11.3.1.3.5.2 Source Channel Initialization
              1. 11.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 11.3.1.3.5.2.2 Static Transfer Request Setup
              3. 11.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 11.3.1.3.5.3 Data Transfer
              1. 11.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 11.3.1.3.5.3.2 MCAN Mode Channel
                1. 11.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 11.3.1.3.5.3.3 AASRC Mode Channel
            4. 11.3.1.3.5.4 Rx Pause
            5. 11.3.1.3.5.5 Rx Teardown
            6. 11.3.1.3.5.6 Rx Channel Reset
            7. 11.3.1.3.5.7 Rx Debug/State Register
          6. 11.3.1.3.6 PDMA ECC Support
      2. 11.3.2 PDMA Sources
        1. 11.3.2.1 PDMA0 Event Map
        2. 11.3.2.2 PDMA1 Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MAIN Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in MCU Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1291
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in MCU Domain
          2. 12.1.3.3.2 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
      4. 12.1.4 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.4.1 MCSPI Overview
          1. 12.1.4.1.1 SPI Features
          2. 12.1.4.1.2 SPI Not Supported Features
        2. 12.1.4.2 MCSPI Environment
          1. 12.1.4.2.1 Basic MCSPI Pins for Controller Mode
          2. 12.1.4.2.2 Basic MCSPI Pins for Peripheral Mode
          3. 12.1.4.2.3 MCSPI Protocol and Data Format
            1. 12.1.4.2.3.1 Transfer Format
          4. 12.1.4.2.4 MCSPI in Controller Mode
          5. 12.1.4.2.5 MCSPI in Peripheral Mode
        3. 12.1.4.3 MCSPI Integration
          1. 12.1.4.3.1 MCSPI Integration in MCU Domain
          2. 12.1.4.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.4.4 MCSPI Functional Description
          1. 12.1.4.4.1 SPI Block Diagram
          2. 12.1.4.4.2 MCSPI Reset
          3. 12.1.4.4.3 MCSPI Controller Mode
            1. 12.1.4.4.3.1 Controller Mode Features
            2. 12.1.4.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.4.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.4.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.4.4.3.5 Single-Channel Controller Mode
              1. 12.1.4.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.4.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.4.4.3.5.3 Turbo Mode
            6. 12.1.4.4.3.6 Start-Bit Mode
            7. 12.1.4.4.3.7 Chip-Select Timing Control
            8. 12.1.4.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.4.4.3.8.1 Clock Ratio Granularity
          4. 12.1.4.4.4 MCSPI Peripheral Mode
            1. 12.1.4.4.4.1 Dedicated Resources
            2. 12.1.4.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.4.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.4.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.4.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.4.4.6 MCSPI FIFO Buffer Management
            1. 12.1.4.4.6.1 Buffer Almost Full
            2. 12.1.4.4.6.2 Buffer Almost Empty
            3. 12.1.4.4.6.3 End of Transfer Management
            4. 12.1.4.4.6.4 Multiple MCSPI Word Access
            5. 12.1.4.4.6.5 First MCSPI Word Delay
          7. 12.1.4.4.7 MCSPI Interrupts
            1. 12.1.4.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.4.4.7.1.1 TXx_EMPTY
              2. 12.1.4.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.4.4.7.1.3 RXx_ FULL
              4. 12.1.4.4.7.1.4 End Of Word Count
            2. 12.1.4.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.4.4.7.2.1 TXx_EMPTY
              2. 12.1.4.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.4.4.7.2.3 RXx_FULL
              4. 12.1.4.4.7.2.4 RX0_OVERFLOW
              5. 12.1.4.4.7.2.5 End Of Word Count
            3. 12.1.4.4.7.3 Interrupt-Driven Operation
            4. 12.1.4.4.7.4 Polling
          8. 12.1.4.4.8 MCSPI DMA Requests
          9. 12.1.4.4.9 MCSPI Power Saving Management
            1. 12.1.4.4.9.1 Normal Mode
            2. 12.1.4.4.9.2 Idle Mode
              1. 12.1.4.4.9.2.1 Force-Idle Mode
        5. 12.1.4.5 MCSPI Programming Guide
          1. 12.1.4.5.1 MCSPI Global Initialization
            1. 12.1.4.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.4.5.1.2 MCSPI Global Initialization
              1. 12.1.4.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.4.5.2 MCSPI Operational Mode Configuration
            1. 12.1.4.5.2.1 MCSPI Operational Modes
              1. 12.1.4.5.2.1.1 Common Transfer Sequence
              2. 12.1.4.5.2.1.2 End of Transfer Sequences
              3. 12.1.4.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.4.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.4.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.4.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.4.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.4.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.4.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.4.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.4.5.2.1.7 Peripheral Receive-Only
              8. 12.1.4.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.4.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.4.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.4.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.4.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.4.5.2.1.8.5 Transmit-Only
                6. 12.1.4.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.4.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.4.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.4.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.4.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.4.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.4.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
      5. 12.1.5 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.5.1 UART Overview
          1. 12.1.5.1.1 UART Features
          2. 12.1.5.1.2 IrDA Features
          3. 12.1.5.1.3 CIR Features
          4. 12.1.5.1.4 UART Not Supported Features
        2. 12.1.5.2 UART Environment
          1. 12.1.5.2.1 UART Functional Interfaces
            1. 12.1.5.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.5.2.1.2 UART Interface Description
            3. 12.1.5.2.1.3 UART Protocol and Data Format
            4. 12.1.5.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.5.2.2 RS-485 Functional Interfaces
            1. 12.1.5.2.2.1 System Using RS-485 Communication
            2. 12.1.5.2.2.2 RS-485 Interface Description
          3. 12.1.5.2.3 IrDA Functional Interfaces
            1. 12.1.5.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.5.2.3.2 IrDA Interface Description
            3. 12.1.5.2.3.3 IrDA Protocol and Data Format
              1. 12.1.5.2.3.3.1 SIR Mode
                1. 12.1.5.2.3.3.1.1 Frame Format
                2. 12.1.5.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.5.2.3.3.1.3 Abort Sequence
                4. 12.1.5.2.3.3.1.4 Pulse Shaping
                5. 12.1.5.2.3.3.1.5 Encoder
                6. 12.1.5.2.3.3.1.6 Decoder
                7. 12.1.5.2.3.3.1.7 IR Address Checking
              2. 12.1.5.2.3.3.2 SIR Free-Format Mode
              3. 12.1.5.2.3.3.3 MIR Mode
                1. 12.1.5.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.5.2.3.3.3.2 SIP Generation
              4. 12.1.5.2.3.3.4 FIR Mode
          4. 12.1.5.2.4 CIR Functional Interfaces
            1. 12.1.5.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.5.2.4.2 CIR Interface Description
            3. 12.1.5.2.4.3 CIR Protocol and Data Format
              1. 12.1.5.2.4.3.1 Carrier Modulation
              2. 12.1.5.2.4.3.2 Pulse Duty Cycle
              3. 12.1.5.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.5.3 UART Integration
          1. 12.1.5.3.1 UART Integration in MCU Domain
          2. 12.1.5.3.2 UART Integration in MAIN Domain
        4. 12.1.5.4 UART Functional Description
          1. 12.1.5.4.1 UART Block Diagram
          2. 12.1.5.4.2 UART Clock Configuration
          3. 12.1.5.4.3 UART Software Reset
            1. 12.1.5.4.3.1 Independent TX/RX
          4. 12.1.5.4.4 UART Power Management
            1. 12.1.5.4.4.1 UART Mode Power Management
              1. 12.1.5.4.4.1.1 Module Power Saving
              2. 12.1.5.4.4.1.2 System Power Saving
            2. 12.1.5.4.4.2 IrDA Mode Power Management
              1. 12.1.5.4.4.2.1 Module Power Saving
              2. 12.1.5.4.4.2.2 System Power Saving
            3. 12.1.5.4.4.3 CIR Mode Power Management
              1. 12.1.5.4.4.3.1 Module Power Saving
              2. 12.1.5.4.4.3.2 System Power Saving
            4. 12.1.5.4.4.4 Local Power Management
          5. 12.1.5.4.5 UART Interrupt Requests
            1. 12.1.5.4.5.1 UART Mode Interrupt Management
              1. 12.1.5.4.5.1.1 UART Interrupts
              2. 12.1.5.4.5.1.2 Wake-Up Interrupt
            2. 12.1.5.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.5.4.5.2.1 IrDA Interrupts
              2. 12.1.5.4.5.2.2 Wake-Up Interrupts
            3. 12.1.5.4.5.3 CIR Mode Interrupt Management
              1. 12.1.5.4.5.3.1 CIR Interrupts
              2. 12.1.5.4.5.3.2 Wake-Up Interrupts
          6. 12.1.5.4.6 UART FIFO Management
            1. 12.1.5.4.6.1 FIFO Trigger
              1. 12.1.5.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.5.4.6.1.2 Receive FIFO Trigger
            2. 12.1.5.4.6.2 FIFO Interrupt Mode
            3. 12.1.5.4.6.3 FIFO Polled Mode Operation
            4. 12.1.5.4.6.4 FIFO DMA Mode Operation
              1. 12.1.5.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.5.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.5.4.6.4.3 DMA Transmission
              4. 12.1.5.4.6.4.4 DMA Reception
          7. 12.1.5.4.7 UART Mode Selection
            1. 12.1.5.4.7.1 Register Access Modes
              1. 12.1.5.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.5.4.7.1.2 Register Access Submode
              3. 12.1.5.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.5.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.5.4.7.2.1 Registers Available for the UART Function
              2. 12.1.5.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.5.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.5.4.8 UART Protocol Formatting
            1. 12.1.5.4.8.1 UART Mode
              1. 12.1.5.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.5.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.5.4.8.1.3 UART Data Formatting
                1. 12.1.5.4.8.1.3.1 Frame Formatting
                2. 12.1.5.4.8.1.3.2 Hardware Flow Control
                3. 12.1.5.4.8.1.3.3 Software Flow Control
                  1. 1.5.4.8.1.3.3.1 Receive (RX)
                  2. 1.5.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.5.4.8.1.3.4 Autobauding Modes
                5. 12.1.5.4.8.1.3.5 Error Detection
                6. 12.1.5.4.8.1.3.6 Overrun During Receive
                7. 12.1.5.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.5.4.8.1.3.7.1 Time-Out Counter
                  2. 1.5.4.8.1.3.7.2 Break Condition
            2. 12.1.5.4.8.2 RS-485 Mode
              1. 12.1.5.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.5.4.8.3 IrDA Mode
              1. 12.1.5.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.5.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.5.4.8.3.3 IrDA Data Formatting
                1. 12.1.5.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.5.4.8.3.3.2  IrDA Reception Control
                3. 12.1.5.4.8.3.3.3  IR Address Checking
                4. 12.1.5.4.8.3.3.4  Frame Closing
                5. 12.1.5.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.5.4.8.3.3.6  Error Detection
                7. 12.1.5.4.8.3.3.7  Underrun During Transmission
                8. 12.1.5.4.8.3.3.8  Overrun During Receive
                9. 12.1.5.4.8.3.3.9  Status FIFO
                10. 12.1.5.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.5.4.8.3.3.11 Time-guard
              4. 12.1.5.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.5.4.8.3.4.1 Abort Sequence
                2. 12.1.5.4.8.3.4.2 Pulse Shaping
                3. 12.1.5.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.5.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.5.4.8.4 CIR Mode
              1. 12.1.5.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.5.4.8.4.2 CIR Data Formatting
                1. 12.1.5.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.5.4.8.4.2.2 CIR Transmission
                3. 12.1.5.4.8.4.2.3 CIR Reception
        5. 12.1.5.5 UART Programming Guide
          1. 12.1.5.5.1 UART Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 UART Module Global Initialization
          2. 12.1.5.5.2 UART Mode selection
          3. 12.1.5.5.3 UART Submode selection
          4. 12.1.5.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.5.5.4.1 DMA mode Settings
            2. 12.1.5.5.4.2 FIFO Trigger Settings
          5. 12.1.5.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.5.5.5.1 Baud rate settings
            2. 12.1.5.5.5.2 Interrupt settings
            3. 12.1.5.5.5.3 Protocol settings
            4. 12.1.5.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.5.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.5.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.5.5.6.1 Hardware Flow Control Configuration
            2. 12.1.5.5.6.2 Software Flow Control Configuration
          7. 12.1.5.5.7 IrDA Programming Model
            1. 12.1.5.5.7.1 SIR mode
              1. 12.1.5.5.7.1.1 Receive
              2. 12.1.5.5.7.1.2 Transmit
            2. 12.1.5.5.7.2 MIR mode
              1. 12.1.5.5.7.2.1 Receive
              2. 12.1.5.5.7.2.2 Transmit
            3. 12.1.5.5.7.3 FIR mode
              1. 12.1.5.5.7.3.1 Receive
              2. 12.1.5.5.7.3.2 Transmit
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet Switch (CPSW3G)
        1. 12.2.1.1 CPSW0 Overview
          1. 12.2.1.1.1 CPSW0 Features
          2. 12.2.1.1.2 CPSW0 Not Supported Features
          3. 12.2.1.1.3 CPSW Terminology
        2. 12.2.1.2 CPSW0 Environment
          1. 12.2.1.2.1 CPSW0 RMII Interface
          2. 12.2.1.2.2 CPSW0 RGMII Interface
        3. 12.2.1.3 CPSW0 Integration
        4. 12.2.1.4 CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_3G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 3-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1  Multicast Address Table Entry
                2. 12.2.1.4.6.1.9.2  OUI Unicast Address Table Entry
                3. 12.2.1.4.6.1.9.3  Unicast Address Table Entry (Bit 40 == 0)
                4. 12.2.1.4.6.1.9.4  Multicast Address Table Entry (Bit 40==1)
                5. 12.2.1.4.6.1.9.5  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                6. 12.2.1.4.6.1.9.6  VLAN/Multicast Address Table Entry (Bit 40==1)
                7. 12.2.1.4.6.1.9.7  Inner VLAN Table Entry
                8. 12.2.1.4.6.1.9.8  Outer VLAN Table Entry
                9. 12.2.1.4.6.1.9.9  EtherType Table Entry
                10. 12.2.1.4.6.1.9.10 IPv4 Table Entry
                11. 12.2.1.4.6.1.9.11 IPv6 Table Entry High
                12. 12.2.1.4.6.1.9.12 IPv6 Table Entry Low
              10. 12.2.1.4.6.1.10 Multicast Address
                1. 12.2.1.4.6.1.10.1 Multicast Ranges
              11. 12.2.1.4.6.1.11 Aging and Auto Aging
              12. 12.2.1.4.6.1.12 ALE Policing and Classification
                1. 12.2.1.4.6.1.12.1 ALE Policing
                2. 12.2.1.4.6.1.12.2 Classifier to Host Thread Mapping
                3. 12.2.1.4.6.1.12.3 ALE Classification
                  1. 2.1.4.6.1.12.3.1 Classifier to CPPI Transmit Flow ID Mapping
              13. 12.2.1.4.6.1.13 Mirroring
              14. 12.2.1.4.6.1.14 Trunking
              15. 12.2.1.4.6.1.15 DSCP
              16. 12.2.1.4.6.1.16 Packet Forwarding Processes
                1. 12.2.1.4.6.1.16.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.16.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.16.3 Egress Process
                4. 12.2.1.4.6.1.16.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.16.4.1 Learning Process
                  2. 2.1.4.6.1.16.4.2 Updating Process
                  3. 2.1.4.6.1.16.4.3 Touching Process
              17. 12.2.1.4.6.1.17 VLAN Aware Mode
              18. 12.2.1.4.6.1.18 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 Ethernet MAC Sliver Overview
                1. 12.2.1.4.6.10.1.1 CRC Insertion
                2. 12.2.1.4.6.10.1.2 MTXER
                3. 12.2.1.4.6.10.1.3 Adaptive Performance Optimization (APO)
                4. 12.2.1.4.6.10.1.4 Inter-Packet-Gap Enforcement
                5. 12.2.1.4.6.10.1.5 Back Off
                6. 12.2.1.4.6.10.1.6 Programmable Transmit Inter-Packet Gap
                7. 12.2.1.4.6.10.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A05Ch)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.1.4.6.18.8  Rx Cut Thru with No Delay
              9. 12.2.1.4.6.18.9  Rx Cut Thru with Delay
              10. 12.2.1.4.6.18.10 Rx Cut Thru Store-and-Forward
              11. 12.2.1.4.6.18.11 Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.11.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.1.4.6.18.11.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.1.4.6.18.11.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.1.4.6.18.11.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.1.4.6.18.11.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.1.4.6.18.11.6  Collisions (Offset = 3A048h)
                7. 12.2.1.4.6.18.11.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.1.4.6.18.11.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.1.4.6.18.11.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.1.4.6.18.11.10 Late Collisions (Offset = 3A058h)
                11. 12.2.1.4.6.18.11.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.1.4.6.18.11.12 Tx Octets (Offset = 3A064h)
                13. 12.2.1.4.6.18.11.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.1.4.6.18.11.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8)
                15. 12.2.1.4.6.18.11.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.1.4.6.18.11.16 IET Transmit Merge Hold Count (Offset = 3A150h)
                17. 12.2.1.4.6.18.11.17 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                18. 12.2.1.4.6.18.11.18 Tx CRC Errors
                19. 12.2.1.4.6.18.11.19 Tx Cut Thru
                20. 12.2.1.4.6.18.11.20 Tx Cut Thru Store-and-Forward
              12. 12.2.1.4.6.18.12 Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.12.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.1.4.6.18.12.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.1.4.6.18.12.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.1.4.6.18.12.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.1.4.6.18.12.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.1.4.6.18.12.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.1.4.6.18.12.7 Net Octets (Offset = 3A080h)
              13. 12.2.1.4.6.18.13 1802
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 1830
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_3G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_3G Ingress)
            3. 12.2.1.4.8.3 Cut-Thru
              1. 12.2.1.4.8.3.1 Host Port Cut-Thru Operations
              2. 12.2.1.4.8.3.2 Cut-Thru Error Packets
            4. 12.2.1.4.8.4 Port Speed
            5. 12.2.1.4.8.5 CPPI Checksum Offload
              1. 12.2.1.4.8.5.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.5.1.1 IPV4 UDP
                2. 12.2.1.4.8.5.1.2 IPV4 TCP
                3. 12.2.1.4.8.5.1.3 IPV6 UDP
                4. 12.2.1.4.8.5.1.4 IPV6 TCP
            6. 12.2.1.4.8.6 CPPI Receive Checksum Offload
            7. 12.2.1.4.8.7 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
      2. 12.2.2 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.2.1 PCIe Subsystem Overview
          1. 12.2.2.1.1 PCIe Subsystem Features
          2. 12.2.2.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.2.2 PCIe Subsystem Environment
        3. 12.2.2.3 PCIe Subsystem Integration
        4. 12.2.2.4 PCIe Subsystem Functional Description
          1. 12.2.2.4.1  PCIe Subsystem Block Diagram
            1. 12.2.2.4.1.1 PCIe PHY Interface
              1. 12.2.2.4.1.1.1 PCIe Core Module
            2. 12.2.2.4.1.2 Custom Logic
          2. 12.2.2.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.2.4.2.1 PCIe Conventional Reset
            2. 12.2.2.4.2.2 PCIe Function Level Reset
            3. 12.2.2.4.2.3 PCIe Reset Isolation
              1. 12.2.2.4.2.3.1 Root Complex Reset with Device Not Reset
              2. 12.2.2.4.2.3.2 Device Reset with Root Complex Not Reset
              3. 12.2.2.4.2.3.3 End Point Device Reset with Root Complex Not Reset
              4. 12.2.2.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.2.4.2.4 PCIe Reset Limitations
            5. 12.2.2.4.2.5 PCIe Reset Requirements
          3. 12.2.2.4.3  PCIe Subsystem Power Management
            1. 12.2.2.4.3.1 CBA Power Management
          4. 12.2.2.4.4  PCIe Subsystem Interrupts
            1. 12.2.2.4.4.1 Interrupts Aggregation
            2. 12.2.2.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.2.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.2.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.2.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.2.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.2.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.2.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.2.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.2.4.4.3.5 PTM Valid Interrupt
            4. 12.2.2.4.4.4 Interrupt Generation in RC Mode
            5. 12.2.2.4.4.5 Interrupt Reception in RC Mode
              1. 12.2.2.4.4.5.1 PCIe Legacy Interrupt Reception in RC Mode
              2. 12.2.2.4.4.5.2 MSI/MSI-X Interrupt Reception in RC Mode
              3. 12.2.2.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.2.4.4.6 Common Interrupt Reception in RC and EP Modes
              1. 12.2.2.4.4.6.1 PCIe Local Interrupt
              2. 12.2.2.4.4.6.2 PHY Interrupt
              3. 12.2.2.4.4.6.3 Link down Interrupt
              4. 12.2.2.4.4.6.4 Transaction Error Interrupts
              5. 12.2.2.4.4.6.5 Power Management Event Interrupt
            7. 12.2.2.4.4.7 ECC Aggregator Interrupts
            8. 12.2.2.4.4.8 CPTS Interrupt
          5. 12.2.2.4.5  PCIe Subsystem DMA Support
            1. 12.2.2.4.5.1 PCIe DMA Support in RC Mode
            2. 12.2.2.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.2.4.6  PCIe Subsystem Transactions
            1. 12.2.2.4.6.1 PCIe Supported Transactions
            2. 12.2.2.4.6.2 PCIe Transaction Limitations
          7. 12.2.2.4.7  PCIe Subsystem Address Translation
            1. 12.2.2.4.7.1 PCIe Inbound Address Translation
              1. 12.2.2.4.7.1.1 Root Complex Inbound PCIe to AXI Address Translation
              2. 12.2.2.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.2.4.7.2 PCIe Outbound Address Translation
              1. 12.2.2.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.2.4.8  PCIe Subsystem Quality-of-Service (QoS)
          9. 12.2.2.4.9  PCIe Subsystem Precision Time Measurement (PTM)
          10. 12.2.2.4.10 PCIe Subsystem Loopback
            1. 12.2.2.4.10.1 PCIe Loopback
              1. 12.2.2.4.10.1.1 PCIe Loopback Initiator Mode
              2. 12.2.2.4.10.1.2 PCIe Loopback Target Mode
          11. 12.2.2.4.11 PCIe Subsystem Error Handling
          12. 12.2.2.4.12 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.2.4.12.1 ECC Aggregators
            2. 12.2.2.4.12.2 RAM ECC Inversion
        5. 12.2.2.5 PCIe Subsystem Registers
      3. 12.2.3 Serializer/Deserializer (SerDes)
        1. 12.2.3.1 SerDes Overview
          1. 12.2.3.1.1 SerDes Features
          2. 12.2.3.1.2 Not Supported Features
          3. 12.2.3.1.3 Industry Standards Compatibility
        2. 12.2.3.2 SerDes Environment
          1. 12.2.3.2.1 SerDes I/Os
        3. 12.2.3.3 SerDes Integration
          1. 12.2.3.3.1 WIZ Settings
            1. 12.2.3.3.1.1 Interface Selection
            2. 12.2.3.3.1.2 Internal Reference Clock Selection
        4. 12.2.3.4 SerDes Functional Description
          1. 12.2.3.4.1 SerDes Block Diagram
      4. 12.2.4 Universal Serial Bus Subsystem (USBSS)
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
          1. 12.2.4.2.1 USB I/Os
          2. 12.2.4.2.2 USB Subsystem Application
          3. 12.2.4.2.3 VBUS Sense
        3. 12.2.4.3 USB Integration
          1. 12.2.4.3.1 Resets, Interrupts, and Clocks
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Controller Reset
          2. 12.2.4.4.2 Overcurrent Detection
          3. 12.2.4.4.3 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MAIN Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS Regions
            1. 12.3.1.4.2.1 FSS Regions Boot Size Configuration
          3. 12.3.1.4.3 FSS Memory Regions
            1. 12.3.1.4.3.1 FSS XIP Prefetcher
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Power Up/Down Sequence
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MAIN Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
              4. 12.3.2.4.2.1.4 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
      3. 12.3.3 General-Purpose Memory Controller (GPMC)
        1. 12.3.3.1 GPMC Overview
          1. 12.3.3.1.1 GPMC Features
          2. 12.3.3.1.2 GPMC Not Supported Features
        2. 12.3.3.2 GPMC Environment
          1. 12.3.3.2.1 GPMC Modes
          2. 12.3.3.2.2 GPMC I/O Signals
        3. 12.3.3.3 GPMC Integration
          1. 12.3.3.3.1 GPMC Integration in MAIN Domain
        4. 12.3.3.4 GPMC Functional Description
          1. 12.3.3.4.1  GPMC Block Diagram
          2. 12.3.3.4.2  GPMC Clock Configuration
          3. 12.3.3.4.3  GPMC Power Management
          4. 12.3.3.4.4  GPMC Interrupt Requests
          5. 12.3.3.4.5  GPMC Interconnect Port Interface
          6. 12.3.3.4.6  GPMC Address and Data Bus
            1. 12.3.3.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.3.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.3.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.3.4.7.2 Access Protocol
              1. 12.3.3.4.7.2.1 Supported Devices
              2. 12.3.3.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.3.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.3.4.7.3 External Signals
              1. 12.3.3.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.3.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.3.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.3.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.3.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.3.4.7.3.1.5 Wait With NAND Device
                6. 12.3.3.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.3.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.3.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.3.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.3.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.3.4.7.3.2 DIR Pin
              3. 12.3.3.4.7.3.3 Reset
              4. 12.3.3.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.3.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.3.4.7.4 Error Handling
          8. 12.3.3.4.8  GPMC Timing Setting
            1. 12.3.3.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.3.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.3.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.3.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.3.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.3.4.8.6  GPMC_CLKOUT
            7. 12.3.3.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.3.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.3.4.8.8.1 Access Time on Read Access
              2. 12.3.3.4.8.8.2 Access Time on Write Access
            9. 12.3.3.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.3.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.3.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.3.4.8.10 Bus Keeping Support
          9. 12.3.3.4.9  GPMC NOR Access Description
            1. 12.3.3.4.9.1 Asynchronous Access Description
              1. 12.3.3.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.3.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.3.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.3.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.3.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.3.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.3.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.3.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.3.4.9.2 Synchronous Access Description
              1. 12.3.3.4.9.2.1 Synchronous Single Read
              2. 12.3.3.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.3.4.9.2.3 Synchronous Single Write
              4. 12.3.3.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.3.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.3.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.3.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.3.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.3.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.3.4.9.4 Page and Burst Support
            5. 12.3.3.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.3.4.10 GPMC pSRAM Access Specificities
          11. 12.3.3.4.11 GPMC NAND Access Description
            1. 12.3.3.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.3.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.3.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.3.4.11.1.3 Command Latch Cycle
              4. 12.3.3.4.11.1.4 Address Latch Cycle
              5. 12.3.3.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.3.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.3.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.3.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.3.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.3.4.11.2 NAND Device-Ready Pin
              1. 12.3.3.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.3.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.3.4.11.3 ECC Calculator
              1. 12.3.3.4.11.3.1 Hamming Code
                1. 12.3.3.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.3.4.11.3.1.2 ECC Enabling
                3. 12.3.3.4.11.3.1.3 ECC Computation
                4. 12.3.3.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.3.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.3.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.3.4.11.3.2 BCH Code
                1. 12.3.3.4.11.3.2.1 Requirements
                2. 12.3.3.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.3.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.3.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.3.4.11.3.2.2.3 Wrapping Modes
                    1. 3.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 3.4.11.3.2.2.3.2  Mode 0x1
                    3. 3.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 3.4.11.3.2.2.3.4  Mode 0x2
                    5. 3.4.11.3.2.2.3.5  Mode 0x3
                    6. 3.4.11.3.2.2.3.6  Mode 0x7
                    7. 3.4.11.3.2.2.3.7  Mode 0x8
                    8. 3.4.11.3.2.2.3.8  Mode 0x4
                    9. 3.4.11.3.2.2.3.9  Mode 0x9
                    10. 3.4.11.3.2.2.3.10 Mode 0x5
                    11. 3.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 3.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.3.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.3.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.3.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.3.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.3.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.3.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.3.4.11.4.2 Prefetch Mode
              3. 12.3.3.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.3.4.11.4.4 Write-Posting Mode
              5. 12.3.3.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.3.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.3.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.3.4.12 GPMC Memory Regions
          13. 12.3.3.4.13 GPMC Use Cases and Tips
            1. 12.3.3.4.13.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.3.4.13.1.1 External Memory Attached to the GPMC Module
              2. 12.3.3.4.13.1.2 Typical GPMC Setup
                1. 12.3.3.4.13.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.3.4.13.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.3.4.13.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.3.4.13.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.3.4.13.2.1 Supported Memories or Devices
                1. 12.3.3.4.13.2.1.1 Memory Pin Multiplexing
                2. 12.3.3.4.13.2.1.2 NAND Interface Protocol
                3. 12.3.3.4.13.2.1.3 NOR Interface Protocol
                4. 12.3.3.4.13.2.1.4 Other Technologies
        5. 12.3.3.5 GPMC Basic Programming Model
          1. 12.3.3.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.3.5.2 GPMC Initialization
          3. 12.3.3.5.3 GPMC Configuration in NOR Mode
          4. 12.3.3.5.4 GPMC Configuration in NAND Mode
          5. 12.3.3.5.5 Set Memory Access
          6. 12.3.3.5.6 GPMC Timing Parameters
            1. 12.3.3.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.3.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.3.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.3.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      4. 12.3.4 Error Location Module (ELM)
        1. 12.3.4.1 ELM Overview
          1. 12.3.4.1.1 ELM Features
          2. 12.3.4.1.2 ELM Not Supported Features
        2. 12.3.4.2 ELM Integration
          1. 12.3.4.2.1 ELM Integration in MAIN Domain
        3. 12.3.4.3 ELM Functional Description
          1. 12.3.4.3.1 ELM Software Reset
          2. 12.3.4.3.2 ELM Power Management
          3. 12.3.4.3.3 ELM Interrupt Requests
          4. 12.3.4.3.4 ELM Processing Initialization
          5. 12.3.4.3.5 ELM Processing Sequence
          6. 12.3.4.3.6 ELM Processing Completion
        4. 12.3.4.4 ELM Basic Programming Model
          1. 12.3.4.4.1 ELM Low-Level Programming Model
            1. 12.3.4.4.1.1 Processing Initialization
            2. 12.3.4.4.1.2 Read Results
            3. 12.3.4.4.1.3 2203
          2. 12.3.4.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.4.4.3 Use Case: ELM Used in Page Mode
      5. 12.3.5 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.5.1 MMCSD Overview
          1. 12.3.5.1.1 MMCSD Features
          2. 12.3.5.1.2 MMCSD Not Supported Features
        2. 12.3.5.2 MMCSD Environment
          1. 12.3.5.2.1 MMCSD IO Mulitplexer
          2. 12.3.5.2.2 Protocol and Data Format
            1. 12.3.5.2.2.1 Protocol
            2. 12.3.5.2.2.2 Data Format
              1. 12.3.5.2.2.2.1 Coding Scheme for Command Token
              2. 12.3.5.2.2.2.2 Coding Scheme for Response Token
              3. 12.3.5.2.2.2.3 Coding Scheme for Data Token
        3. 12.3.5.3 MMCSD Integration
          1. 12.3.5.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.5.4 MMCSD Functional Description
          1. 12.3.5.4.1 Block Diagram
          2. 12.3.5.4.2 Memory Regions
          3. 12.3.5.4.3 Interrupt Requests
          4. 12.3.5.4.4 ECC Support
            1. 12.3.5.4.4.1 ECC Aggregator
          5. 12.3.5.4.5 Advanced DMA
        5. 12.3.5.5 MMCSD Programming Guide
          1. 12.3.5.5.1 Sequences
            1. 12.3.5.5.1.1  SD Card Detection
            2. 12.3.5.5.1.2  SD Clock Control
              1. 12.3.5.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.5.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.5.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.5.5.1.3  SD Bus Power Control
            4. 12.3.5.5.1.4  Changing Bus Width
            5. 12.3.5.5.1.5  Timeout Setting on DAT Line
            6. 12.3.5.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.5.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.5.5.1.7  SD Transaction Generation
              1. 12.3.5.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.5.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.5.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.5.5.1.7.1.3 2243
              2. 12.3.5.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.5.5.1.7.2.1 Not using DMA
                2. 12.3.5.5.1.7.2.2 Using SDMA
                3. 12.3.5.5.1.7.2.3 Using ADMA
            8. 12.3.5.5.1.8  Abort Transaction
              1. 12.3.5.5.1.8.1 Asynchronous Abort
              2. 12.3.5.5.1.8.2 Synchronous Abort
            9. 12.3.5.5.1.9  Changing Bus Speed Mode
            10. 12.3.5.5.1.10 Error Recovery
              1. 12.3.5.5.1.10.1 Error Interrupt Recovery
              2. 12.3.5.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.5.5.1.11 Wakeup Control (Optional)
            12. 12.3.5.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.5.5.1.12.1 Suspend Sequence
              2. 12.3.5.5.1.12.2 Resume Sequence
              3. 12.3.5.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.5.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.5.5.2 Driver Flow Sequence
            1. 12.3.5.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.5.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.5.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.5.5.2.2 Boot Operation
              1. 12.3.5.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.5.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.5.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.5.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.5.5.2.3.1 Sampling Clock Tuning
              2. 12.3.5.5.2.3.2 Tuning Modes
              3. 12.3.5.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.5.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.5.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.5.5.2.4.2 Task Issuance Sequence
              3. 12.3.5.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.5.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.5.5.2.4.5 Error Detect and Recovery when CQ is enabled
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Modular Controller Area Network (MCAN)
        1. 12.4.1.1 MCAN Overview
          1. 12.4.1.1.1 MCAN Features
          2. 12.4.1.1.2 MCAN Not Supported Features
        2. 12.4.1.2 MCAN Environment
          1. 12.4.1.2.1 CAN Network Basics
        3. 12.4.1.3 MCAN Integration
          1. 12.4.1.3.1 MCAN Integration in MAIN Domain
        4. 12.4.1.4 MCAN Functional Description
          1. 12.4.1.4.1  Module Clocking Requirements
          2. 12.4.1.4.2  Interrupt and DMA Requests
            1. 12.4.1.4.2.1 Interrupt Requests
            2. 12.4.1.4.2.2 DMA Requests
          3. 12.4.1.4.3  Operating Modes
            1. 12.4.1.4.3.1 Software Initialization
            2. 12.4.1.4.3.2 Normal Operation
            3. 12.4.1.4.3.3 CAN FD Operation
            4. 12.4.1.4.3.4 Transmitter Delay Compensation
              1. 12.4.1.4.3.4.1 Description
              2. 12.4.1.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.1.4.3.5 Restricted Operation Mode
            6. 12.4.1.4.3.6 Bus Monitoring Mode
            7. 12.4.1.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.1.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.1.4.3.8 Power Down (Sleep Mode)
              1. 12.4.1.4.3.8.1 External Clock Stop Mode
              2. 12.4.1.4.3.8.2 Suspend Mode
              3. 12.4.1.4.3.8.3 Wakeup request
            9. 12.4.1.4.3.9 Test Modes
              1. 12.4.1.4.3.9.1 Internal Loopback Mode
          4. 12.4.1.4.4  Timestamp Generation
            1. 12.4.1.4.4.1 External Timestamp Counter
          5. 12.4.1.4.5  Timeout Counter
          6. 12.4.1.4.6  ECC Support
            1. 12.4.1.4.6.1 ECC Wrapper
            2. 12.4.1.4.6.2 ECC Aggregator
          7. 12.4.1.4.7  Rx Handling
            1. 12.4.1.4.7.1 Acceptance Filtering
              1. 12.4.1.4.7.1.1 Range Filter
              2. 12.4.1.4.7.1.2 Filter for specific IDs
              3. 12.4.1.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.1.4.7.1.4 Standard Message ID Filtering
              5. 12.4.1.4.7.1.5 Extended Message ID Filtering
            2. 12.4.1.4.7.2 Rx FIFOs
              1. 12.4.1.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.1.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.1.4.7.3 Dedicated Rx Buffers
              1. 12.4.1.4.7.3.1 Rx Buffer Handling
            4. 12.4.1.4.7.4 Debug on CAN Support
          8. 12.4.1.4.8  Tx Handling
            1. 12.4.1.4.8.1 Transmit Pause
            2. 12.4.1.4.8.2 Dedicated Tx Buffers
            3. 12.4.1.4.8.3 Tx FIFO
            4. 12.4.1.4.8.4 Tx Queue
            5. 12.4.1.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.1.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.1.4.8.7 Transmit Cancellation
            8. 12.4.1.4.8.8 Tx Event Handling
          9. 12.4.1.4.9  FIFO Acknowledge Handling
          10. 12.4.1.4.10 Message RAM
            1. 12.4.1.4.10.1 Message RAM Configuration
            2. 12.4.1.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.1.4.10.3 Tx Buffer Element
            4. 12.4.1.4.10.4 Tx Event FIFO Element
            5. 12.4.1.4.10.5 Standard Message ID Filter Element
            6. 12.4.1.4.10.6 Extended Message ID Filter Element
      2. 12.4.2 Enhanced Capture (ECAP) Module
        1. 12.4.2.1 ECAP Overview
          1. 12.4.2.1.1 ECAP Features
        2. 12.4.2.2 ECAP Environment
          1. 12.4.2.2.1 ECAP I/O Interface
        3. 12.4.2.3 ECAP Integration
          1. 12.4.2.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.2.4 ECAP Functional Description
          1. 12.4.2.4.1 Capture and APWM Operating Modes
            1. 12.4.2.4.1.1 ECAP Capture Mode Description
              1. 12.4.2.4.1.1.1 ECAP Event Prescaler
              2. 12.4.2.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.2.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.2.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.2.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.2.4.1.1.6 ECAP Interrupt Control
              7. 12.4.2.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.2.4.1.2 ECAP APWM Mode Operation
          2. 12.4.2.4.2 Summary of ECAP Functional Registers
        5. 12.4.2.5 ECAP Use Cases
          1. 12.4.2.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.2.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.2.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.2.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.2.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.2.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.2.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.2.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.2.5.5 Application of the APWM Mode
            1. 12.4.2.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.2.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.2.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.2.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.2.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.2.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
      3. 12.4.3 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.3.1 EPWM Overview
          1. 12.4.3.1.1 EPWM Features
          2. 12.4.3.1.2 EPWM Not Supported Features
          3. 12.4.3.1.3 Multiple EPWM Module Details
        2. 12.4.3.2 EPWM Environment
        3. 12.4.3.3 EPWM Integration
          1. 12.4.3.3.1 EPWM Additional Integration Details
            1. 12.4.3.3.1.1 EPWM Tripzone Connectivity
            2. 12.4.3.3.1.2 Daisy-Chain Connectivity between EPWM Modules
            3. 12.4.3.3.1.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
            4. 12.4.3.3.1.4 EPWM Modules Time-Base Clock Gating
        4. 12.4.3.4 EPWM Functional Description
          1. 12.4.3.4.1  EPWM Submodule Features
            1. 12.4.3.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.3.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.3.4.2.1 Overview
            2. 12.4.3.4.2.2 Controlling and Monitoring the EPWM Time-Base Submodule
            3. 12.4.3.4.2.3 Calculating PWM Period and Frequency
              1. 12.4.3.4.2.3.1 EPWM Time-Base Period Shadow Register
              2. 12.4.3.4.2.3.2 EPWM Time-Base Counter Synchronization
            4. 12.4.3.4.2.4 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            5. 12.4.3.4.2.5 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.3.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.3.4.3.1 Overview
            2. 12.4.3.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.3.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.3.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.3.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.3.4.4.1 Overview
            2. 12.4.3.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.3.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.3.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.3.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.3.4.5.1 Overview
            2. 12.4.3.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.3.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.3.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.3.4.6.1 Overview
            2. 12.4.3.4.6.2 2420
            3. 12.4.3.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.3.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.3.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.3.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.3.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.3.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.3.4.7.1 Overview
            2. 12.4.3.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.3.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.3.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.3.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.3.4.8.1 Overview
            2. 12.4.3.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.3.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.3.4.8.4 Operation Overview of the EPWM SOCx Pulse Generator
          9. 12.4.3.4.9  EPWM Functional Register Groups
          10. 12.4.3.4.10 Proper EPWM Interrupt Initialization Procedure
      4. 12.4.4 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.4.1 EQEP Overview
          1. 12.4.4.1.1 EQEP Features
          2. 12.4.4.1.2 EQEP Not Supported Features
        2. 12.4.4.2 EQEP Environment
          1. 12.4.4.2.1 EQEP I/O Interface
        3. 12.4.4.3 EQEP Integration
          1. 12.4.4.3.1 Device Specific EQEP Features
        4. 12.4.4.4 EQEP Functional Description
          1. 12.4.4.4.1 EQEP Inputs
          2. 12.4.4.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.4.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.4.4.2.1.1 Quadrature Count Mode
              2. 12.4.4.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.4.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.4.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.4.4.2.2 EQEP Input Polarity Selection
            3. 12.4.4.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.4.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.4.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.4.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.4.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.4.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.4.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.4.4.3.2 EQEP Position Counter Latch
              1. 12.4.4.4.3.2.1 Index Event Latch
              2. 12.4.4.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.4.4.3.3 EQEP Position Counter Initialization
            4. 12.4.4.4.3.4 EQEP Position-Compare Unit
          4. 12.4.4.4.4 EQEP Edge Capture Unit
          5. 12.4.4.4.5 EQEP Watchdog
          6. 12.4.4.4.6 Unit Timer Base
          7. 12.4.4.4.7 EQEP Interrupt Structure
          8. 12.4.4.4.8 Summary of EQEP Functional Registers
      5. 12.4.5 Fast Serial Interface (FSI)
        1. 12.4.5.1 FSI Overview
          1. 12.4.5.1.1 FSI Features
          2. 12.4.5.1.2 FSI Not Supported Featurs
        2. 12.4.5.2 FSI Environment
          1. 12.4.5.2.1 Signal Description
        3. 12.4.5.3 FSI Integration
          1. 12.4.5.3.1 FSI Interrupts
            1. 12.4.5.3.1.1 Transmitter Interrupts
            2. 12.4.5.3.1.2 Receiver Interrupts
            3. 12.4.5.3.1.3 Configuring Interrupts
            4. 12.4.5.3.1.4 Handling Interrupts
        4. 12.4.5.4 FSI Functional Description
          1. 12.4.5.4.1 FSI Functional Description
          2. 12.4.5.4.2 FSI Transmitter Module (FSI_TX)
            1. 12.4.5.4.2.1 Initialization
            2. 12.4.5.4.2.2 FSI_TX Clocking
            3. 12.4.5.4.2.3 Transmitting Frames
              1. 12.4.5.4.2.3.1 Software Triggered Frames
              2. 12.4.5.4.2.3.2 Ping Frame Generation
                1. 12.4.5.4.2.3.2.1 Automatic Ping Frames
                2. 12.4.5.4.2.3.2.2 Software Triggered Ping Frame
            4. 12.4.5.4.2.4 Transmit Buffer Management
            5. 12.4.5.4.2.5 CRC Submodule
            6. 12.4.5.4.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
            7. 12.4.5.4.2.7 Reset
          3. 12.4.5.4.3 FSI Receiver Module (FSI_RX)
            1. 12.4.5.4.3.1  Initialization
            2. 12.4.5.4.3.2  FSI_RX Clocking
            3. 12.4.5.4.3.3  Receiving Frames
            4. 12.4.5.4.3.4  Ping Frame Watchdog
            5. 12.4.5.4.3.5  Frame Watchdog
            6. 12.4.5.4.3.6  Delay Line Control
            7. 12.4.5.4.3.7  Buffer Management
            8. 12.4.5.4.3.8  CRC Submodule
            9. 12.4.5.4.3.9  Using the Zero Bits of the Receiver Tag Registers
            10. 12.4.5.4.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
            11. 12.4.5.4.3.11 FSI_RX Reset
          4. 12.4.5.4.4 Frame Format
            1. 12.4.5.4.4.1 FSI Frame Phases
            2. 12.4.5.4.4.2 Frame Types
              1. 12.4.5.4.4.2.1 Ping Frames
              2. 12.4.5.4.4.2.2 Error Frames
              3. 12.4.5.4.4.2.3 Data Frames
            3. 12.4.5.4.4.3 Multi-Lane Transmission
          5. 12.4.5.4.5 Flush Sequence
          6. 12.4.5.4.6 Internal Loopback
          7. 12.4.5.4.7 CRC Generation
          8. 12.4.5.4.8 ECC Module
          9. 12.4.5.4.9 FSI-SPI Compatibility Mode
            1. 12.4.5.4.9.1 Available SPI Modes
              1. 12.4.5.4.9.1.1 FSITX as SPI Controller, Transmit Only
                1. 12.4.5.4.9.1.1.1 Initialization
                2. 12.4.5.4.9.1.1.2 Operation
              2. 12.4.5.4.9.1.2 FSIRX as SPI Peripheral, Receive Only
                1. 12.4.5.4.9.1.2.1 Initialization
                2. 12.4.5.4.9.1.2.2 Operation
              3. 12.4.5.4.9.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
                1. 12.4.5.4.9.1.3.1 Initialization
                2. 12.4.5.4.9.1.3.2 Operation
        5. 12.4.5.5 FSI Programing Guide
          1. 12.4.5.5.1 Establishing the Communication Link
            1. 12.4.5.5.1.1 Establishing the Communication Link from the Main Device
            2. 12.4.5.5.1.2 Establishing the Communication Link from the Remote Device
          2. 12.4.5.5.2 Register Protection
          3. 12.4.5.5.3 Emulation Mode
    5. 12.5 Timer Modules
      1. 12.5.1 Global Timebase Counter (GTC)
        1. 12.5.1.1 Global Timebase Counter (GTC)
          1. 12.5.1.1.1 GTC Overview
            1. 12.5.1.1.1.1 GTC Features
            2. 12.5.1.1.1.2 GTC Not Supported Features
          2. 12.5.1.1.2 GTC Integration
        2. 12.5.1.2 GTC Functional Description
          1. 12.5.1.2.1 GTC Block Diagram
          2. 12.5.1.2.2 GTC Counter
          3. 12.5.1.2.3 GTC Register Partitioning
      2. 12.5.2 RTI-Windowed Watchdog Timer (WWDT)
        1. 12.5.2.1 RTI Overview
          1. 12.5.2.1.1 RTI Features
          2. 12.5.2.1.2 RTI Not Supported Features
        2. 12.5.2.2 RTI Integration
          1. 12.5.2.2.1 RTI Integration in MCU Domain
          2. 12.5.2.2.2 RTI Integration in MAIN Domain
        3. 12.5.2.3 RTI Functional Description
          1. 12.5.2.3.1 RTI Digital Windowed Watchdog
            1. 12.5.2.3.1.1 RTI Debug Mode Behavior
            2. 12.5.2.3.1.2 RTI Low Power Mode Operation
          2. 12.5.2.3.2 RTI Digital Watchdog
          3. 12.5.2.3.3 RTI Counter Operation
      3. 12.5.3 Timers
        1. 12.5.3.1 Timers Overview
          1. 12.5.3.1.1 Timers Features
          2. 12.5.3.1.2 Timers Not Supported Features
        2. 12.5.3.2 Timers Environment
          1. 12.5.3.2.1 Timer External System Interface
        3. 12.5.3.3 Timers Integration
          1. 12.5.3.3.1 Timers Integration in MCU Domain
          2. 12.5.3.3.2 Timers Integration in MAIN Domain
        4. 12.5.3.4 Timers Functional Description
          1. 12.5.3.4.1  Timer Block Diagram
          2. 12.5.3.4.2  Timer Power Management
            1. 12.5.3.4.2.1 Wake-Up Capability
          3. 12.5.3.4.3  Timer Software Reset
          4. 12.5.3.4.4  Timer Interrupts
          5. 12.5.3.4.5  Timer Mode Functionality
            1. 12.5.3.4.5.1 1-ms Tick Generation
          6. 12.5.3.4.6  Timer Capture Mode Functionality
          7. 12.5.3.4.7  Timer Compare Mode Functionality
          8. 12.5.3.4.8  Timer Prescaler Functionality
          9. 12.5.3.4.9  Timer Pulse-Width Modulation
          10. 12.5.3.4.10 Timer Counting Rate
          11. 12.5.3.4.11 Timer Under Emulation
          12. 12.5.3.4.12 Accessing Timer Registers
            1. 12.5.3.4.12.1 Writing to Timer Registers
              1. 12.5.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.5.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.5.3.4.12.2 Reading From Timer Counter Registers
              1. 12.5.3.4.12.2.1 Read Posted
              2. 12.5.3.4.12.2.2 Read Non-Posted
          13. 12.5.3.4.13 Timer Posted Mode Selection
        5. 12.5.3.5 Timers Low-Level Programming Models
          1. 12.5.3.5.1 Timer Global Initialization
            1. 12.5.3.5.1.1 Main Sequence – Timer Module Global Initialization
          2. 12.5.3.5.2 Timer Operational Mode Configuration
            1. 12.5.3.5.2.1 Timer Mode
              1. 12.5.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.5.3.5.2.2 Timer Compare Mode
              1. 12.5.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.5.3.5.2.3 Timer Capture Mode
              1. 12.5.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.5.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.5.3.5.2.3.3 Subsequence – Detect Event
            4. 12.5.3.5.2.4 Timer PWM Mode
              1. 12.5.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
    6. 12.6 Internal Diagnostics Modules
      1. 12.6.1 Dual Clock Comparator (DCC)
        1. 12.6.1.1 DCC Overview
          1. 12.6.1.1.1 DCC Features
          2. 12.6.1.1.2 DCC Not Supported Features
        2. 12.6.1.2 DCC Integration
          1. 12.6.1.2.1 DCC Integration in MCU Domain
            1. 12.6.1.2.1.1 MCU DCC Input Source Clock Mapping
          2. 12.6.1.2.2 DCC Integration in MAIN Domain
            1. 12.6.1.2.2.1 DCC Input Source Clock Mapping
        3. 12.6.1.3 DCC Functional Description
          1. 12.6.1.3.1 DCC Counter Operation
          2. 12.6.1.3.2 DCC Low Power Mode Operation
          3. 12.6.1.3.3 DCC Suspend Mode Behavior
          4. 12.6.1.3.4 DCC Single-Shot Mode
          5. 12.6.1.3.5 DCC Continuous Mode
            1. 12.6.1.3.5.1 DCC Continue on Error
            2. 12.6.1.3.5.2 DCC Error Count
          6. 12.6.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.6.1.3.7 DCC Error Trajectory Record
            1. 12.6.1.3.7.1 DCC FIFO Capturing for Errors
            2. 12.6.1.3.7.2 DCC FIFO in Continuous Capture Mode
            3. 12.6.1.3.7.3 DCC FIFO Details
            4. 12.6.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.6.1.3.8 DCC Count Read Registers
      2. 12.6.2 Error Signaling Module (ESM)
        1. 12.6.2.1 ESM Overview
          1. 12.6.2.1.1 ESM Features
        2. 12.6.2.2 ESM Environment
        3. 12.6.2.3 ESM Integration
          1. 12.6.2.3.1 ESM Integration in MCU Domain
          2. 12.6.2.3.2 ESM Integration in MAIN Domain
        4. 12.6.2.4 ESM Functional Description
          1. 12.6.2.4.1 ESM Interrupt Requests
            1. 12.6.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.6.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.6.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.6.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.6.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.6.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.6.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.6.2.4.2 ESM Error Event Inputs
          3. 12.6.2.4.3 ESM Error Pin Output
          4. 12.6.2.4.4 PWM Mode
          5. 12.6.2.4.5 ESM Minimum Time Interval
          6. 12.6.2.4.6 ESM Protection for Registers
          7. 12.6.2.4.7 ESM Clock Stop
      3. 12.6.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.6.3.1 MCRC Overview
          1. 12.6.3.1.1 MCRC Features
          2. 12.6.3.1.2 MCRC Not Supported Features
        2. 12.6.3.2 MCRC Integration
        3. 12.6.3.3 MCRC Functional Description
          1. 12.6.3.3.1  MCRC Block Diagram
          2. 12.6.3.3.2  MCRC General Operation
          3. 12.6.3.3.3  MCRC Modes of Operation
            1. 12.6.3.3.3.1 AUTO Mode
            2. 12.6.3.3.3.2 Semi-CPU Mode
            3. 12.6.3.3.3.3 Full-CPU Mode
          4. 12.6.3.3.4  PSA Signature Register
          5. 12.6.3.3.5  PSA Sector Signature Register
          6. 12.6.3.3.6  CRC Value Register
          7. 12.6.3.3.7  Raw Data Register
          8. 12.6.3.3.8  Example DMA Controller Setup
            1. 12.6.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.6.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.6.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.6.3.3.9  Pattern Count Register
          10. 12.6.3.3.10 Sector Count Register/Current Sector Register
          11. 12.6.3.3.11 Interrupts
            1. 12.6.3.3.11.1 Overrun Interrupt
            2. 12.6.3.3.11.2 Timeout Interrupt
            3. 12.6.3.3.11.3 Underrun Interrupt
            4. 12.6.3.3.11.4 Compression Complete Interrupt
            5. 12.6.3.3.11.5 Interrupt Offset Register
            6. 12.6.3.3.11.6 Error Handling
          12. 12.6.3.3.12 Power Down Mode
          13. 12.6.3.3.13 Emulation
        4. 12.6.3.4 MCRC Programming Examples
          1. 12.6.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.6.3.4.1.1 DMA Setup
            2. 12.6.3.4.1.2 Timer Setup
            3. 12.6.3.4.1.3 CRC Setup
          2. 12.6.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.6.3.4.2.1 DMA Setup
            2. 12.6.3.4.2.2 CRC Setup
          3. 12.6.3.4.3 Example: Semi-CPU Mode
            1. 12.6.3.4.3.1 DMA Setup
            2. 12.6.3.4.3.2 Timer Setup
            3. 12.6.3.4.3.3 CRC Setup
          4. 12.6.3.4.4 Example: Full-CPU Mode
            1. 12.6.3.4.4.1 CRC Setup
      4. 12.6.4 ECC Aggregator
        1. 12.6.4.1 ECC Aggregator Overview
          1. 12.6.4.1.1 ECC Aggregator Features
        2. 12.6.4.2 ECC Aggregator Integration
        3. 12.6.4.3 ECC Aggregator Functional Description
          1. 12.6.4.3.1 ECC Aggregator Block Diagram
          2. 12.6.4.3.2 ECC Aggregator Register Groups
          3. 12.6.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.6.4.3.4 Serial Write Operation
          5. 12.6.4.3.5 Interrupts
          6. 12.6.4.3.6 Inject Only Mode
        4. 12.6.4.4 ECC Aggregators Interconnect
  15. 13On-Chip Debug
    1. 13.1 On-Chip Debug Overview
    2. 13.2 On-Chip Debug Features
    3.     2714
    4. 13.3 On-Chip Debug Functional Description
      1. 13.3.1  On-Chip Debug Block Diagram
      2. 13.3.2  Device Interfaces
        1. 13.3.2.1 JTAG Interface
        2. 13.3.2.2 Trigger and Debug Boot Mode Interface
        3. 13.3.2.3 Trace Port Interface
      3. 13.3.3  Debug and Boundary Scan Access and Control
      4. 13.3.4  Debug Boot Modes and Boundary Scan Compliance
      5. 13.3.5  Peripheral Suspend
      6. 13.3.6  Power, Reset, Clock Management
      7. 13.3.7  Debug Cross Triggering
      8. 13.3.8  R5FSS0/R5FSS1 Debug
      9. 13.3.9  DMSC Debug
      10. 13.3.10 A53SS0 Debug
      11. 13.3.11 PRU_ICSSG0/PRU_ICSSG1 Debug
      12. 13.3.12 SoC Debug and Trace
        1. 13.3.12.1 Software Messaging Trace
        2. 13.3.12.2 Debug-Aware Peripherals
        3. 13.3.12.3 Debug Suspend Router Connections
        4. 13.3.12.4 Traffic Monitoring With Bus Probes
        5. 13.3.12.5 Global Timestamping for Trace
      13. 13.3.13 Trace Traffic
        1. 13.3.13.1 Trace Sources
        2. 13.3.13.2 Trace Infrastructure
        3. 13.3.13.3 Trace Sinks
      14. 13.3.14 Application Support
  16. 14Registers
    1. 14.1  System Interconnect Registers
      1. 14.1.1 CBASS Registers
        1. 14.1.1.1    CBASS Summary Table
        2. 14.1.1.2    CBASS_ERR_PID Register
        3. 14.1.1.3    CBASS_ERR_DESTINATION_ID Register
        4. 14.1.1.4    CBASS_ERR_EXCEPTION_LOGGING_HEADER0 Register
        5. 14.1.1.5    CBASS_ERR_EXCEPTION_LOGGING_HEADER1 Register
        6. 14.1.1.6    CBASS_ERR_EXCEPTION_LOGGING_DATA0 Register
        7. 14.1.1.7    CBASS_ERR_EXCEPTION_LOGGING_DATA1 Register
        8. 14.1.1.8    CBASS_ERR_EXCEPTION_LOGGING_DATA2 Register
        9. 14.1.1.9    CBASS_ERR_EXCEPTION_LOGGING_DATA3 Register
        10. 14.1.1.10   CBASS_ERR_ERR_INTR_RAW_STAT Register
        11. 14.1.1.11   CBASS_ERR_ERR_INTR_ENABLED_STAT Register
        12. 14.1.1.12   CBASS_ERR_ERR_INTR_ENABLE_SET Register
        13. 14.1.1.13   CBASS_ERR_ERR_INTR_ENABLE_CLR Register
        14. 14.1.1.14   CBASS_ERR_EOI Register
        15. 14.1.1.15   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_CONTROL Register
        16. 14.1.1.16   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_0 Register
        17. 14.1.1.17   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_1 Register
        18. 14.1.1.18   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_PERMISSION_2 Register
        19. 14.1.1.19   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_START_ADDRESS_L Register
        20. 14.1.1.20   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_START_ADDRESS_H Register
        21. 14.1.1.21   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_END_ADDRESS_L Register
        22. 14.1.1.22   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_0_END_ADDRESS_H Register
        23. 14.1.1.23   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_CONTROL Register
        24. 14.1.1.24   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_0 Register
        25. 14.1.1.25   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_1 Register
        26. 14.1.1.26   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_PERMISSION_2 Register
        27. 14.1.1.27   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_START_ADDRESS_L Register
        28. 14.1.1.28   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_START_ADDRESS_H Register
        29. 14.1.1.29   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_END_ADDRESS_L Register
        30. 14.1.1.30   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_1_END_ADDRESS_H Register
        31. 14.1.1.31   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_CONTROL Register
        32. 14.1.1.32   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_0 Register
        33. 14.1.1.33   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_1 Register
        34. 14.1.1.34   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_PERMISSION_2 Register
        35. 14.1.1.35   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_START_ADDRESS_L Register
        36. 14.1.1.36   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_START_ADDRESS_H Register
        37. 14.1.1.37   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_END_ADDRESS_L Register
        38. 14.1.1.38   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_2_END_ADDRESS_H Register
        39. 14.1.1.39   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_CONTROL Register
        40. 14.1.1.40   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_0 Register
        41. 14.1.1.41   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_1 Register
        42. 14.1.1.42   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_PERMISSION_2 Register
        43. 14.1.1.43   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_START_ADDRESS_L Register
        44. 14.1.1.44   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_START_ADDRESS_H Register
        45. 14.1.1.45   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_END_ADDRESS_L Register
        46. 14.1.1.46   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_3_END_ADDRESS_H Register
        47. 14.1.1.47   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_CONTROL Register
        48. 14.1.1.48   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_0 Register
        49. 14.1.1.49   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_1 Register
        50. 14.1.1.50   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_PERMISSION_2 Register
        51. 14.1.1.51   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_START_ADDRESS_L Register
        52. 14.1.1.52   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_START_ADDRESS_H Register
        53. 14.1.1.53   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_END_ADDRESS_L Register
        54. 14.1.1.54   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_4_END_ADDRESS_H Register
        55. 14.1.1.55   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_CONTROL Register
        56. 14.1.1.56   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_0 Register
        57. 14.1.1.57   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_1 Register
        58. 14.1.1.58   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_PERMISSION_2 Register
        59. 14.1.1.59   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_START_ADDRESS_L Register
        60. 14.1.1.60   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_START_ADDRESS_H Register
        61. 14.1.1.61   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_END_ADDRESS_L Register
        62. 14.1.1.62   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_5_END_ADDRESS_H Register
        63. 14.1.1.63   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_CONTROL Register
        64. 14.1.1.64   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_0 Register
        65. 14.1.1.65   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_1 Register
        66. 14.1.1.66   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_PERMISSION_2 Register
        67. 14.1.1.67   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_START_ADDRESS_L Register
        68. 14.1.1.68   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_START_ADDRESS_H Register
        69. 14.1.1.69   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_END_ADDRESS_L Register
        70. 14.1.1.70   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_6_END_ADDRESS_H Register
        71. 14.1.1.71   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_CONTROL Register
        72. 14.1.1.72   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_0 Register
        73. 14.1.1.73   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_1 Register
        74. 14.1.1.74   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_PERMISSION_2 Register
        75. 14.1.1.75   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_START_ADDRESS_L Register
        76. 14.1.1.76   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_START_ADDRESS_H Register
        77. 14.1.1.77   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_END_ADDRESS_L Register
        78. 14.1.1.78   CBASS_FW_ISAM64_DDR_WRAP_MAIN_0_DDRSS_FW_REGION_7_END_ADDRESS_H Register
        79. 14.1.1.79   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_CONTROL Register
        80. 14.1.1.80   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_0 Register
        81. 14.1.1.81   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_1 Register
        82. 14.1.1.82   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_PERMISSION_2 Register
        83. 14.1.1.83   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_START_ADDRESS_L Register
        84. 14.1.1.84   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_START_ADDRESS_H Register
        85. 14.1.1.85   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_END_ADDRESS_L Register
        86. 14.1.1.86   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_0_END_ADDRESS_H Register
        87. 14.1.1.87   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_CONTROL Register
        88. 14.1.1.88   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_0 Register
        89. 14.1.1.89   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_1 Register
        90. 14.1.1.90   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_PERMISSION_2 Register
        91. 14.1.1.91   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_START_ADDRESS_L Register
        92. 14.1.1.92   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_START_ADDRESS_H Register
        93. 14.1.1.93   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_END_ADDRESS_L Register
        94. 14.1.1.94   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_1_END_ADDRESS_H Register
        95. 14.1.1.95   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_CONTROL Register
        96. 14.1.1.96   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_0 Register
        97. 14.1.1.97   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_1 Register
        98. 14.1.1.98   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_PERMISSION_2 Register
        99. 14.1.1.99   CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_START_ADDRESS_L Register
        100. 14.1.1.100  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_START_ADDRESS_H Register
        101. 14.1.1.101  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_END_ADDRESS_L Register
        102. 14.1.1.102  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_2_END_ADDRESS_H Register
        103. 14.1.1.103  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_CONTROL Register
        104. 14.1.1.104  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_0 Register
        105. 14.1.1.105  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_1 Register
        106. 14.1.1.106  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_PERMISSION_2 Register
        107. 14.1.1.107  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_START_ADDRESS_L Register
        108. 14.1.1.108  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_START_ADDRESS_H Register
        109. 14.1.1.109  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_END_ADDRESS_L Register
        110. 14.1.1.110  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_3_END_ADDRESS_H Register
        111. 14.1.1.111  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_CONTROL Register
        112. 14.1.1.112  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_0 Register
        113. 14.1.1.113  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_1 Register
        114. 14.1.1.114  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_PERMISSION_2 Register
        115. 14.1.1.115  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_START_ADDRESS_L Register
        116. 14.1.1.116  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_START_ADDRESS_H Register
        117. 14.1.1.117  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_END_ADDRESS_L Register
        118. 14.1.1.118  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_4_END_ADDRESS_H Register
        119. 14.1.1.119  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_CONTROL Register
        120. 14.1.1.120  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_0 Register
        121. 14.1.1.121  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_1 Register
        122. 14.1.1.122  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_PERMISSION_2 Register
        123. 14.1.1.123  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_START_ADDRESS_L Register
        124. 14.1.1.124  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_START_ADDRESS_H Register
        125. 14.1.1.125  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_END_ADDRESS_L Register
        126. 14.1.1.126  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_5_END_ADDRESS_H Register
        127. 14.1.1.127  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_CONTROL Register
        128. 14.1.1.128  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_0 Register
        129. 14.1.1.129  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_1 Register
        130. 14.1.1.130  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_PERMISSION_2 Register
        131. 14.1.1.131  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_START_ADDRESS_L Register
        132. 14.1.1.132  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_START_ADDRESS_H Register
        133. 14.1.1.133  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_END_ADDRESS_L Register
        134. 14.1.1.134  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_6_END_ADDRESS_H Register
        135. 14.1.1.135  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_CONTROL Register
        136. 14.1.1.136  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_0 Register
        137. 14.1.1.137  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_1 Register
        138. 14.1.1.138  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_PERMISSION_2 Register
        139. 14.1.1.139  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_START_ADDRESS_L Register
        140. 14.1.1.140  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_START_ADDRESS_H Register
        141. 14.1.1.141  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_END_ADDRESS_L Register
        142. 14.1.1.142  CBASS_FW_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_ACP_W_FW_REGION_7_END_ADDRESS_H Register
        143. 14.1.1.143  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_CONTROL Register
        144. 14.1.1.144  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_0 Register
        145. 14.1.1.145  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_1 Register
        146. 14.1.1.146  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_PERMISSION_2 Register
        147. 14.1.1.147  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_START_ADDRESS_L Register
        148. 14.1.1.148  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_START_ADDRESS_H Register
        149. 14.1.1.149  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_END_ADDRESS_L Register
        150. 14.1.1.150  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_0_END_ADDRESS_H Register
        151. 14.1.1.151  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_CONTROL Register
        152. 14.1.1.152  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_0 Register
        153. 14.1.1.153  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_1 Register
        154. 14.1.1.154  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_PERMISSION_2 Register
        155. 14.1.1.155  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_START_ADDRESS_L Register
        156. 14.1.1.156  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_START_ADDRESS_H Register
        157. 14.1.1.157  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_END_ADDRESS_L Register
        158. 14.1.1.158  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_1_END_ADDRESS_H Register
        159. 14.1.1.159  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_CONTROL Register
        160. 14.1.1.160  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_0 Register
        161. 14.1.1.161  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_1 Register
        162. 14.1.1.162  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_PERMISSION_2 Register
        163. 14.1.1.163  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_START_ADDRESS_L Register
        164. 14.1.1.164  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_START_ADDRESS_H Register
        165. 14.1.1.165  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_END_ADDRESS_L Register
        166. 14.1.1.166  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_2_END_ADDRESS_H Register
        167. 14.1.1.167  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_CONTROL Register
        168. 14.1.1.168  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_0 Register
        169. 14.1.1.169  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_1 Register
        170. 14.1.1.170  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_PERMISSION_2 Register
        171. 14.1.1.171  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_START_ADDRESS_L Register
        172. 14.1.1.172  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_START_ADDRESS_H Register
        173. 14.1.1.173  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_END_ADDRESS_L Register
        174. 14.1.1.174  CBASS_FW_IMSRAM32KX64E_MAIN_0_SLV_FW_REGION_3_END_ADDRESS_H Register
        175. 14.1.1.175  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_CONTROL Register
        176. 14.1.1.176  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_0 Register
        177. 14.1.1.177  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_1 Register
        178. 14.1.1.178  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_PERMISSION_2 Register
        179. 14.1.1.179  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_START_ADDRESS_L Register
        180. 14.1.1.180  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_START_ADDRESS_H Register
        181. 14.1.1.181  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_END_ADDRESS_L Register
        182. 14.1.1.182  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_0_END_ADDRESS_H Register
        183. 14.1.1.183  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_CONTROL Register
        184. 14.1.1.184  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_0 Register
        185. 14.1.1.185  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_1 Register
        186. 14.1.1.186  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_PERMISSION_2 Register
        187. 14.1.1.187  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_START_ADDRESS_L Register
        188. 14.1.1.188  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_START_ADDRESS_H Register
        189. 14.1.1.189  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_END_ADDRESS_L Register
        190. 14.1.1.190  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_1_END_ADDRESS_H Register
        191. 14.1.1.191  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_CONTROL Register
        192. 14.1.1.192  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_0 Register
        193. 14.1.1.193  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_1 Register
        194. 14.1.1.194  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_PERMISSION_2 Register
        195. 14.1.1.195  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_START_ADDRESS_L Register
        196. 14.1.1.196  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_START_ADDRESS_H Register
        197. 14.1.1.197  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_END_ADDRESS_L Register
        198. 14.1.1.198  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_2_END_ADDRESS_H Register
        199. 14.1.1.199  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_CONTROL Register
        200. 14.1.1.200  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_0 Register
        201. 14.1.1.201  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_1 Register
        202. 14.1.1.202  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_PERMISSION_2 Register
        203. 14.1.1.203  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_START_ADDRESS_L Register
        204. 14.1.1.204  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_START_ADDRESS_H Register
        205. 14.1.1.205  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_END_ADDRESS_L Register
        206. 14.1.1.206  CBASS_FW_IMSRAM32KX64E_MAIN_1_SLV_FW_REGION_3_END_ADDRESS_H Register
        207. 14.1.1.207  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_CONTROL Register
        208. 14.1.1.208  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_0 Register
        209. 14.1.1.209  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_1 Register
        210. 14.1.1.210  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_PERMISSION_2 Register
        211. 14.1.1.211  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_START_ADDRESS_L Register
        212. 14.1.1.212  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_START_ADDRESS_H Register
        213. 14.1.1.213  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_END_ADDRESS_L Register
        214. 14.1.1.214  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_0_END_ADDRESS_H Register
        215. 14.1.1.215  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_CONTROL Register
        216. 14.1.1.216  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_0 Register
        217. 14.1.1.217  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_1 Register
        218. 14.1.1.218  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_PERMISSION_2 Register
        219. 14.1.1.219  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_START_ADDRESS_L Register
        220. 14.1.1.220  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_START_ADDRESS_H Register
        221. 14.1.1.221  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_END_ADDRESS_L Register
        222. 14.1.1.222  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_1_END_ADDRESS_H Register
        223. 14.1.1.223  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_CONTROL Register
        224. 14.1.1.224  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_0 Register
        225. 14.1.1.225  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_1 Register
        226. 14.1.1.226  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_PERMISSION_2 Register
        227. 14.1.1.227  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_START_ADDRESS_L Register
        228. 14.1.1.228  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_START_ADDRESS_H Register
        229. 14.1.1.229  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_END_ADDRESS_L Register
        230. 14.1.1.230  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_2_END_ADDRESS_H Register
        231. 14.1.1.231  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_CONTROL Register
        232. 14.1.1.232  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_0 Register
        233. 14.1.1.233  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_1 Register
        234. 14.1.1.234  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_PERMISSION_2 Register
        235. 14.1.1.235  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_START_ADDRESS_L Register
        236. 14.1.1.236  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_START_ADDRESS_H Register
        237. 14.1.1.237  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_END_ADDRESS_L Register
        238. 14.1.1.238  CBASS_FW_IMSRAM32KX64E_MAIN_2_SLV_FW_REGION_3_END_ADDRESS_H Register
        239. 14.1.1.239  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_CONTROL Register
        240. 14.1.1.240  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_0 Register
        241. 14.1.1.241  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_1 Register
        242. 14.1.1.242  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_PERMISSION_2 Register
        243. 14.1.1.243  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_START_ADDRESS_L Register
        244. 14.1.1.244  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_START_ADDRESS_H Register
        245. 14.1.1.245  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_END_ADDRESS_L Register
        246. 14.1.1.246  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_0_END_ADDRESS_H Register
        247. 14.1.1.247  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_CONTROL Register
        248. 14.1.1.248  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_0 Register
        249. 14.1.1.249  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_1 Register
        250. 14.1.1.250  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_PERMISSION_2 Register
        251. 14.1.1.251  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_START_ADDRESS_L Register
        252. 14.1.1.252  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_START_ADDRESS_H Register
        253. 14.1.1.253  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_END_ADDRESS_L Register
        254. 14.1.1.254  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_1_END_ADDRESS_H Register
        255. 14.1.1.255  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_CONTROL Register
        256. 14.1.1.256  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_0 Register
        257. 14.1.1.257  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_1 Register
        258. 14.1.1.258  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_PERMISSION_2 Register
        259. 14.1.1.259  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_START_ADDRESS_L Register
        260. 14.1.1.260  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_START_ADDRESS_H Register
        261. 14.1.1.261  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_END_ADDRESS_L Register
        262. 14.1.1.262  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_2_END_ADDRESS_H Register
        263. 14.1.1.263  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_CONTROL Register
        264. 14.1.1.264  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_0 Register
        265. 14.1.1.265  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_1 Register
        266. 14.1.1.266  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_PERMISSION_2 Register
        267. 14.1.1.267  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_START_ADDRESS_L Register
        268. 14.1.1.268  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_START_ADDRESS_H Register
        269. 14.1.1.269  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_END_ADDRESS_L Register
        270. 14.1.1.270  CBASS_FW_IMSRAM32KX64E_MAIN_5_SLV_FW_REGION_3_END_ADDRESS_H Register
        271. 14.1.1.271  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_CONTROL Register
        272. 14.1.1.272  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_0 Register
        273. 14.1.1.273  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_1 Register
        274. 14.1.1.274  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_PERMISSION_2 Register
        275. 14.1.1.275  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_START_ADDRESS_L Register
        276. 14.1.1.276  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_START_ADDRESS_H Register
        277. 14.1.1.277  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_END_ADDRESS_L Register
        278. 14.1.1.278  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_0_END_ADDRESS_H Register
        279. 14.1.1.279  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_CONTROL Register
        280. 14.1.1.280  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_0 Register
        281. 14.1.1.281  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_1 Register
        282. 14.1.1.282  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_PERMISSION_2 Register
        283. 14.1.1.283  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_START_ADDRESS_L Register
        284. 14.1.1.284  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_START_ADDRESS_H Register
        285. 14.1.1.285  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_END_ADDRESS_L Register
        286. 14.1.1.286  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_1_END_ADDRESS_H Register
        287. 14.1.1.287  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_CONTROL Register
        288. 14.1.1.288  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_0 Register
        289. 14.1.1.289  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_1 Register
        290. 14.1.1.290  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_PERMISSION_2 Register
        291. 14.1.1.291  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_START_ADDRESS_L Register
        292. 14.1.1.292  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_START_ADDRESS_H Register
        293. 14.1.1.293  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_END_ADDRESS_L Register
        294. 14.1.1.294  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_2_END_ADDRESS_H Register
        295. 14.1.1.295  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_CONTROL Register
        296. 14.1.1.296  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_0 Register
        297. 14.1.1.297  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_1 Register
        298. 14.1.1.298  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_PERMISSION_2 Register
        299. 14.1.1.299  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_START_ADDRESS_L Register
        300. 14.1.1.300  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_START_ADDRESS_H Register
        301. 14.1.1.301  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_END_ADDRESS_L Register
        302. 14.1.1.302  CBASS_FW_IMSRAM32KX64E_MAIN_4_SLV_FW_REGION_3_END_ADDRESS_H Register
        303. 14.1.1.303  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_CONTROL Register
        304. 14.1.1.304  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_0 Register
        305. 14.1.1.305  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_1 Register
        306. 14.1.1.306  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_PERMISSION_2 Register
        307. 14.1.1.307  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_START_ADDRESS_L Register
        308. 14.1.1.308  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_START_ADDRESS_H Register
        309. 14.1.1.309  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_END_ADDRESS_L Register
        310. 14.1.1.310  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_0_END_ADDRESS_H Register
        311. 14.1.1.311  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_CONTROL Register
        312. 14.1.1.312  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_0 Register
        313. 14.1.1.313  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_1 Register
        314. 14.1.1.314  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_PERMISSION_2 Register
        315. 14.1.1.315  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_START_ADDRESS_L Register
        316. 14.1.1.316  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_START_ADDRESS_H Register
        317. 14.1.1.317  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_END_ADDRESS_L Register
        318. 14.1.1.318  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_1_END_ADDRESS_H Register
        319. 14.1.1.319  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_CONTROL Register
        320. 14.1.1.320  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_0 Register
        321. 14.1.1.321  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_1 Register
        322. 14.1.1.322  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_PERMISSION_2 Register
        323. 14.1.1.323  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_START_ADDRESS_L Register
        324. 14.1.1.324  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_START_ADDRESS_H Register
        325. 14.1.1.325  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_END_ADDRESS_L Register
        326. 14.1.1.326  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_2_END_ADDRESS_H Register
        327. 14.1.1.327  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_CONTROL Register
        328. 14.1.1.328  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_0 Register
        329. 14.1.1.329  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_1 Register
        330. 14.1.1.330  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_PERMISSION_2 Register
        331. 14.1.1.331  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_START_ADDRESS_L Register
        332. 14.1.1.332  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_START_ADDRESS_H Register
        333. 14.1.1.333  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_END_ADDRESS_L Register
        334. 14.1.1.334  CBASS_FW_IMSRAM32KX64E_MAIN_3_SLV_FW_REGION_3_END_ADDRESS_H Register
        335. 14.1.1.335  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_CONTROL Register
        336. 14.1.1.336  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_0 Register
        337. 14.1.1.337  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_1 Register
        338. 14.1.1.338  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_PERMISSION_2 Register
        339. 14.1.1.339  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_START_ADDRESS_L Register
        340. 14.1.1.340  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_START_ADDRESS_H Register
        341. 14.1.1.341  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_END_ADDRESS_L Register
        342. 14.1.1.342  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_0_END_ADDRESS_H Register
        343. 14.1.1.343  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_CONTROL Register
        344. 14.1.1.344  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_0 Register
        345. 14.1.1.345  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_1 Register
        346. 14.1.1.346  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_PERMISSION_2 Register
        347. 14.1.1.347  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_START_ADDRESS_L Register
        348. 14.1.1.348  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_START_ADDRESS_H Register
        349. 14.1.1.349  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_END_ADDRESS_L Register
        350. 14.1.1.350  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_1_END_ADDRESS_H Register
        351. 14.1.1.351  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_CONTROL Register
        352. 14.1.1.352  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_0 Register
        353. 14.1.1.353  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_1 Register
        354. 14.1.1.354  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_PERMISSION_2 Register
        355. 14.1.1.355  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_START_ADDRESS_L Register
        356. 14.1.1.356  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_START_ADDRESS_H Register
        357. 14.1.1.357  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_END_ADDRESS_L Register
        358. 14.1.1.358  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_2_END_ADDRESS_H Register
        359. 14.1.1.359  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_CONTROL Register
        360. 14.1.1.360  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_0 Register
        361. 14.1.1.361  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_1 Register
        362. 14.1.1.362  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_PERMISSION_2 Register
        363. 14.1.1.363  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_START_ADDRESS_L Register
        364. 14.1.1.364  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_START_ADDRESS_H Register
        365. 14.1.1.365  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_END_ADDRESS_L Register
        366. 14.1.1.366  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_3_END_ADDRESS_H Register
        367. 14.1.1.367  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_CONTROL Register
        368. 14.1.1.368  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_0 Register
        369. 14.1.1.369  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_1 Register
        370. 14.1.1.370  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_PERMISSION_2 Register
        371. 14.1.1.371  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_START_ADDRESS_L Register
        372. 14.1.1.372  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_START_ADDRESS_H Register
        373. 14.1.1.373  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_END_ADDRESS_L Register
        374. 14.1.1.374  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_4_END_ADDRESS_H Register
        375. 14.1.1.375  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_CONTROL Register
        376. 14.1.1.376  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_0 Register
        377. 14.1.1.377  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_1 Register
        378. 14.1.1.378  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_PERMISSION_2 Register
        379. 14.1.1.379  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_START_ADDRESS_L Register
        380. 14.1.1.380  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_START_ADDRESS_H Register
        381. 14.1.1.381  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_END_ADDRESS_L Register
        382. 14.1.1.382  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_5_END_ADDRESS_H Register
        383. 14.1.1.383  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_CONTROL Register
        384. 14.1.1.384  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_0 Register
        385. 14.1.1.385  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_1 Register
        386. 14.1.1.386  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_PERMISSION_2 Register
        387. 14.1.1.387  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_START_ADDRESS_L Register
        388. 14.1.1.388  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_START_ADDRESS_H Register
        389. 14.1.1.389  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_END_ADDRESS_L Register
        390. 14.1.1.390  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_6_END_ADDRESS_H Register
        391. 14.1.1.391  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_CONTROL Register
        392. 14.1.1.392  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_0 Register
        393. 14.1.1.393  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_1 Register
        394. 14.1.1.394  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_PERMISSION_2 Register
        395. 14.1.1.395  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_START_ADDRESS_L Register
        396. 14.1.1.396  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_START_ADDRESS_H Register
        397. 14.1.1.397  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_END_ADDRESS_L Register
        398. 14.1.1.398  CBASS_FW_IDMSS_AM64_MAIN_0_IPCSS_VBM_DST_FW_REGION_7_END_ADDRESS_H Register
        399. 14.1.1.399  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_CONTROL Register
        400. 14.1.1.400  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_0 Register
        401. 14.1.1.401  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_1 Register
        402. 14.1.1.402  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_PERMISSION_2 Register
        403. 14.1.1.403  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_START_ADDRESS_L Register
        404. 14.1.1.404  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_START_ADDRESS_H Register
        405. 14.1.1.405  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_END_ADDRESS_L Register
        406. 14.1.1.406  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_0_END_ADDRESS_H Register
        407. 14.1.1.407  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_CONTROL Register
        408. 14.1.1.408  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_0 Register
        409. 14.1.1.409  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_1 Register
        410. 14.1.1.410  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_PERMISSION_2 Register
        411. 14.1.1.411  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_START_ADDRESS_L Register
        412. 14.1.1.412  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_START_ADDRESS_H Register
        413. 14.1.1.413  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_END_ADDRESS_L Register
        414. 14.1.1.414  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_1_END_ADDRESS_H Register
        415. 14.1.1.415  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_CONTROL Register
        416. 14.1.1.416  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_0 Register
        417. 14.1.1.417  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_1 Register
        418. 14.1.1.418  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_PERMISSION_2 Register
        419. 14.1.1.419  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_START_ADDRESS_L Register
        420. 14.1.1.420  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_START_ADDRESS_H Register
        421. 14.1.1.421  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_END_ADDRESS_L Register
        422. 14.1.1.422  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_2_END_ADDRESS_H Register
        423. 14.1.1.423  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_CONTROL Register
        424. 14.1.1.424  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_0 Register
        425. 14.1.1.425  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_1 Register
        426. 14.1.1.426  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_PERMISSION_2 Register
        427. 14.1.1.427  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_START_ADDRESS_L Register
        428. 14.1.1.428  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_START_ADDRESS_H Register
        429. 14.1.1.429  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_END_ADDRESS_L Register
        430. 14.1.1.430  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_3_END_ADDRESS_H Register
        431. 14.1.1.431  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_CONTROL Register
        432. 14.1.1.432  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_0 Register
        433. 14.1.1.433  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_1 Register
        434. 14.1.1.434  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_PERMISSION_2 Register
        435. 14.1.1.435  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_START_ADDRESS_L Register
        436. 14.1.1.436  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_START_ADDRESS_H Register
        437. 14.1.1.437  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_END_ADDRESS_L Register
        438. 14.1.1.438  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_4_END_ADDRESS_H Register
        439. 14.1.1.439  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_CONTROL Register
        440. 14.1.1.440  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_0 Register
        441. 14.1.1.441  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_1 Register
        442. 14.1.1.442  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_PERMISSION_2 Register
        443. 14.1.1.443  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_START_ADDRESS_L Register
        444. 14.1.1.444  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_START_ADDRESS_H Register
        445. 14.1.1.445  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_END_ADDRESS_L Register
        446. 14.1.1.446  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_5_END_ADDRESS_H Register
        447. 14.1.1.447  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_CONTROL Register
        448. 14.1.1.448  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_0 Register
        449. 14.1.1.449  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_1 Register
        450. 14.1.1.450  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_PERMISSION_2 Register
        451. 14.1.1.451  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_START_ADDRESS_L Register
        452. 14.1.1.452  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_START_ADDRESS_H Register
        453. 14.1.1.453  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_END_ADDRESS_L Register
        454. 14.1.1.454  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_6_END_ADDRESS_H Register
        455. 14.1.1.455  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_CONTROL Register
        456. 14.1.1.456  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_0 Register
        457. 14.1.1.457  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_1 Register
        458. 14.1.1.458  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_PERMISSION_2 Register
        459. 14.1.1.459  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_START_ADDRESS_L Register
        460. 14.1.1.460  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_START_ADDRESS_H Register
        461. 14.1.1.461  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_END_ADDRESS_L Register
        462. 14.1.1.462  CBASS_FW_IEXPORT_VBUSM_32B_SLV_MAIN2MCU_SLV_FW_REGION_7_END_ADDRESS_H Register
        463. 14.1.1.463  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_CONTROL Register
        464. 14.1.1.464  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_0 Register
        465. 14.1.1.465  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_1 Register
        466. 14.1.1.466  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_PERMISSION_2 Register
        467. 14.1.1.467  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_START_ADDRESS_L Register
        468. 14.1.1.468  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_START_ADDRESS_H Register
        469. 14.1.1.469  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_END_ADDRESS_L Register
        470. 14.1.1.470  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_0_END_ADDRESS_H Register
        471. 14.1.1.471  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_CONTROL Register
        472. 14.1.1.472  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_0 Register
        473. 14.1.1.473  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_1 Register
        474. 14.1.1.474  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_PERMISSION_2 Register
        475. 14.1.1.475  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_START_ADDRESS_L Register
        476. 14.1.1.476  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_START_ADDRESS_H Register
        477. 14.1.1.477  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_END_ADDRESS_L Register
        478. 14.1.1.478  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_1_END_ADDRESS_H Register
        479. 14.1.1.479  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_CONTROL Register
        480. 14.1.1.480  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_0 Register
        481. 14.1.1.481  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_1 Register
        482. 14.1.1.482  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_PERMISSION_2 Register
        483. 14.1.1.483  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_START_ADDRESS_L Register
        484. 14.1.1.484  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_START_ADDRESS_H Register
        485. 14.1.1.485  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_END_ADDRESS_L Register
        486. 14.1.1.486  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_2_END_ADDRESS_H Register
        487. 14.1.1.487  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_CONTROL Register
        488. 14.1.1.488  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_0 Register
        489. 14.1.1.489  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_1 Register
        490. 14.1.1.490  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_PERMISSION_2 Register
        491. 14.1.1.491  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_START_ADDRESS_L Register
        492. 14.1.1.492  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_START_ADDRESS_H Register
        493. 14.1.1.493  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_END_ADDRESS_L Register
        494. 14.1.1.494  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_3_END_ADDRESS_H Register
        495. 14.1.1.495  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_CONTROL Register
        496. 14.1.1.496  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_0 Register
        497. 14.1.1.497  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_1 Register
        498. 14.1.1.498  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_PERMISSION_2 Register
        499. 14.1.1.499  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_START_ADDRESS_L Register
        500. 14.1.1.500  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_START_ADDRESS_H Register
        501. 14.1.1.501  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_END_ADDRESS_L Register
        502. 14.1.1.502  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_4_END_ADDRESS_H Register
        503. 14.1.1.503  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_CONTROL Register
        504. 14.1.1.504  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_0 Register
        505. 14.1.1.505  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_1 Register
        506. 14.1.1.506  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_PERMISSION_2 Register
        507. 14.1.1.507  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_START_ADDRESS_L Register
        508. 14.1.1.508  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_START_ADDRESS_H Register
        509. 14.1.1.509  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_END_ADDRESS_L Register
        510. 14.1.1.510  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_5_END_ADDRESS_H Register
        511. 14.1.1.511  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_CONTROL Register
        512. 14.1.1.512  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_0 Register
        513. 14.1.1.513  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_1 Register
        514. 14.1.1.514  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_PERMISSION_2 Register
        515. 14.1.1.515  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_START_ADDRESS_L Register
        516. 14.1.1.516  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_START_ADDRESS_H Register
        517. 14.1.1.517  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_END_ADDRESS_L Register
        518. 14.1.1.518  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_6_END_ADDRESS_H Register
        519. 14.1.1.519  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_CONTROL Register
        520. 14.1.1.520  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_0 Register
        521. 14.1.1.521  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_1 Register
        522. 14.1.1.522  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_PERMISSION_2 Register
        523. 14.1.1.523  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_START_ADDRESS_L Register
        524. 14.1.1.524  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_START_ADDRESS_H Register
        525. 14.1.1.525  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_END_ADDRESS_L Register
        526. 14.1.1.526  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_7_END_ADDRESS_H Register
        527. 14.1.1.527  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_CONTROL Register
        528. 14.1.1.528  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_0 Register
        529. 14.1.1.529  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_1 Register
        530. 14.1.1.530  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_PERMISSION_2 Register
        531. 14.1.1.531  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_START_ADDRESS_L Register
        532. 14.1.1.532  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_START_ADDRESS_H Register
        533. 14.1.1.533  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_END_ADDRESS_L Register
        534. 14.1.1.534  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_8_END_ADDRESS_H Register
        535. 14.1.1.535  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_CONTROL Register
        536. 14.1.1.536  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_0 Register
        537. 14.1.1.537  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_1 Register
        538. 14.1.1.538  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_PERMISSION_2 Register
        539. 14.1.1.539  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_START_ADDRESS_L Register
        540. 14.1.1.540  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_START_ADDRESS_H Register
        541. 14.1.1.541  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_END_ADDRESS_L Register
        542. 14.1.1.542  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_9_END_ADDRESS_H Register
        543. 14.1.1.543  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_CONTROL Register
        544. 14.1.1.544  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_0 Register
        545. 14.1.1.545  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_1 Register
        546. 14.1.1.546  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_PERMISSION_2 Register
        547. 14.1.1.547  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_START_ADDRESS_L Register
        548. 14.1.1.548  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_START_ADDRESS_H Register
        549. 14.1.1.549  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_END_ADDRESS_L Register
        550. 14.1.1.550  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_10_END_ADDRESS_H Register
        551. 14.1.1.551  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_CONTROL Register
        552. 14.1.1.552  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_0 Register
        553. 14.1.1.553  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_1 Register
        554. 14.1.1.554  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_PERMISSION_2 Register
        555. 14.1.1.555  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_START_ADDRESS_L Register
        556. 14.1.1.556  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_START_ADDRESS_H Register
        557. 14.1.1.557  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_END_ADDRESS_L Register
        558. 14.1.1.558  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_11_END_ADDRESS_H Register
        559. 14.1.1.559  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_CONTROL Register
        560. 14.1.1.560  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_0 Register
        561. 14.1.1.561  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_1 Register
        562. 14.1.1.562  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_PERMISSION_2 Register
        563. 14.1.1.563  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_START_ADDRESS_L Register
        564. 14.1.1.564  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_START_ADDRESS_H Register
        565. 14.1.1.565  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_END_ADDRESS_L Register
        566. 14.1.1.566  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_12_END_ADDRESS_H Register
        567. 14.1.1.567  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_CONTROL Register
        568. 14.1.1.568  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_0 Register
        569. 14.1.1.569  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_1 Register
        570. 14.1.1.570  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_PERMISSION_2 Register
        571. 14.1.1.571  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_START_ADDRESS_L Register
        572. 14.1.1.572  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_START_ADDRESS_H Register
        573. 14.1.1.573  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_END_ADDRESS_L Register
        574. 14.1.1.574  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_13_END_ADDRESS_H Register
        575. 14.1.1.575  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_CONTROL Register
        576. 14.1.1.576  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_0 Register
        577. 14.1.1.577  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_1 Register
        578. 14.1.1.578  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_PERMISSION_2 Register
        579. 14.1.1.579  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_START_ADDRESS_L Register
        580. 14.1.1.580  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_START_ADDRESS_H Register
        581. 14.1.1.581  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_END_ADDRESS_L Register
        582. 14.1.1.582  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_14_END_ADDRESS_H Register
        583. 14.1.1.583  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_CONTROL Register
        584. 14.1.1.584  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_0 Register
        585. 14.1.1.585  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_1 Register
        586. 14.1.1.586  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_PERMISSION_2 Register
        587. 14.1.1.587  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_START_ADDRESS_L Register
        588. 14.1.1.588  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_START_ADDRESS_H Register
        589. 14.1.1.589  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_END_ADDRESS_L Register
        590. 14.1.1.590  CBASS_FW_BR_SCRM_64B_CLK2_TO_SCRP_MISC_CLK2_L0_FW_REGION_15_END_ADDRESS_H Register
        591. 14.1.1.591  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_CONTROL Register
        592. 14.1.1.592  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_0 Register
        593. 14.1.1.593  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_1 Register
        594. 14.1.1.594  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_PERMISSION_2 Register
        595. 14.1.1.595  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_START_ADDRESS_L Register
        596. 14.1.1.596  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_START_ADDRESS_H Register
        597. 14.1.1.597  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_END_ADDRESS_L Register
        598. 14.1.1.598  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_0_END_ADDRESS_H Register
        599. 14.1.1.599  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_CONTROL Register
        600. 14.1.1.600  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_0 Register
        601. 14.1.1.601  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_1 Register
        602. 14.1.1.602  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_PERMISSION_2 Register
        603. 14.1.1.603  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_START_ADDRESS_L Register
        604. 14.1.1.604  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_START_ADDRESS_H Register
        605. 14.1.1.605  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_END_ADDRESS_L Register
        606. 14.1.1.606  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_1_END_ADDRESS_H Register
        607. 14.1.1.607  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_CONTROL Register
        608. 14.1.1.608  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_0 Register
        609. 14.1.1.609  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_1 Register
        610. 14.1.1.610  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_PERMISSION_2 Register
        611. 14.1.1.611  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_START_ADDRESS_L Register
        612. 14.1.1.612  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_START_ADDRESS_H Register
        613. 14.1.1.613  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_END_ADDRESS_L Register
        614. 14.1.1.614  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_2_END_ADDRESS_H Register
        615. 14.1.1.615  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_CONTROL Register
        616. 14.1.1.616  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_0 Register
        617. 14.1.1.617  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_1 Register
        618. 14.1.1.618  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_PERMISSION_2 Register
        619. 14.1.1.619  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_START_ADDRESS_L Register
        620. 14.1.1.620  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_START_ADDRESS_H Register
        621. 14.1.1.621  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_END_ADDRESS_L Register
        622. 14.1.1.622  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_3_END_ADDRESS_H Register
        623. 14.1.1.623  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_CONTROL Register
        624. 14.1.1.624  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_0 Register
        625. 14.1.1.625  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_1 Register
        626. 14.1.1.626  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_PERMISSION_2 Register
        627. 14.1.1.627  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_START_ADDRESS_L Register
        628. 14.1.1.628  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_START_ADDRESS_H Register
        629. 14.1.1.629  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_END_ADDRESS_L Register
        630. 14.1.1.630  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_4_END_ADDRESS_H Register
        631. 14.1.1.631  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_CONTROL Register
        632. 14.1.1.632  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_0 Register
        633. 14.1.1.633  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_1 Register
        634. 14.1.1.634  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_PERMISSION_2 Register
        635. 14.1.1.635  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_START_ADDRESS_L Register
        636. 14.1.1.636  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_START_ADDRESS_H Register
        637. 14.1.1.637  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_END_ADDRESS_L Register
        638. 14.1.1.638  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_5_END_ADDRESS_H Register
        639. 14.1.1.639  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_CONTROL Register
        640. 14.1.1.640  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_0 Register
        641. 14.1.1.641  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_1 Register
        642. 14.1.1.642  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_PERMISSION_2 Register
        643. 14.1.1.643  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_START_ADDRESS_L Register
        644. 14.1.1.644  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_START_ADDRESS_H Register
        645. 14.1.1.645  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_END_ADDRESS_L Register
        646. 14.1.1.646  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_6_END_ADDRESS_H Register
        647. 14.1.1.647  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_CONTROL Register
        648. 14.1.1.648  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_0 Register
        649. 14.1.1.649  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_1 Register
        650. 14.1.1.650  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_PERMISSION_2 Register
        651. 14.1.1.651  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_START_ADDRESS_L Register
        652. 14.1.1.652  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_START_ADDRESS_H Register
        653. 14.1.1.653  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_END_ADDRESS_L Register
        654. 14.1.1.654  CBASS_FW_IMSRAM32KX64E_MAIN_6_SLV_FW_REGION_7_END_ADDRESS_H Register
        655. 14.1.1.655  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_CONTROL Register
        656. 14.1.1.656  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_0 Register
        657. 14.1.1.657  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_1 Register
        658. 14.1.1.658  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_PERMISSION_2 Register
        659. 14.1.1.659  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_START_ADDRESS_L Register
        660. 14.1.1.660  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_START_ADDRESS_H Register
        661. 14.1.1.661  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_END_ADDRESS_L Register
        662. 14.1.1.662  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_0_END_ADDRESS_H Register
        663. 14.1.1.663  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_CONTROL Register
        664. 14.1.1.664  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_0 Register
        665. 14.1.1.665  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_1 Register
        666. 14.1.1.666  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_PERMISSION_2 Register
        667. 14.1.1.667  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_START_ADDRESS_L Register
        668. 14.1.1.668  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_START_ADDRESS_H Register
        669. 14.1.1.669  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_END_ADDRESS_L Register
        670. 14.1.1.670  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_1_END_ADDRESS_H Register
        671. 14.1.1.671  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_CONTROL Register
        672. 14.1.1.672  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_0 Register
        673. 14.1.1.673  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_1 Register
        674. 14.1.1.674  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_PERMISSION_2 Register
        675. 14.1.1.675  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_START_ADDRESS_L Register
        676. 14.1.1.676  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_START_ADDRESS_H Register
        677. 14.1.1.677  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_END_ADDRESS_L Register
        678. 14.1.1.678  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_2_END_ADDRESS_H Register
        679. 14.1.1.679  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_CONTROL Register
        680. 14.1.1.680  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_0 Register
        681. 14.1.1.681  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_1 Register
        682. 14.1.1.682  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_PERMISSION_2 Register
        683. 14.1.1.683  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_START_ADDRESS_L Register
        684. 14.1.1.684  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_START_ADDRESS_H Register
        685. 14.1.1.685  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_END_ADDRESS_L Register
        686. 14.1.1.686  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_3_END_ADDRESS_H Register
        687. 14.1.1.687  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_CONTROL Register
        688. 14.1.1.688  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_0 Register
        689. 14.1.1.689  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_1 Register
        690. 14.1.1.690  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_PERMISSION_2 Register
        691. 14.1.1.691  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_START_ADDRESS_L Register
        692. 14.1.1.692  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_START_ADDRESS_H Register
        693. 14.1.1.693  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_END_ADDRESS_L Register
        694. 14.1.1.694  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_4_END_ADDRESS_H Register
        695. 14.1.1.695  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_CONTROL Register
        696. 14.1.1.696  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_0 Register
        697. 14.1.1.697  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_1 Register
        698. 14.1.1.698  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_PERMISSION_2 Register
        699. 14.1.1.699  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_START_ADDRESS_L Register
        700. 14.1.1.700  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_START_ADDRESS_H Register
        701. 14.1.1.701  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_END_ADDRESS_L Register
        702. 14.1.1.702  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_5_END_ADDRESS_H Register
        703. 14.1.1.703  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_CONTROL Register
        704. 14.1.1.704  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_0 Register
        705. 14.1.1.705  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_1 Register
        706. 14.1.1.706  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_PERMISSION_2 Register
        707. 14.1.1.707  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_START_ADDRESS_L Register
        708. 14.1.1.708  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_START_ADDRESS_H Register
        709. 14.1.1.709  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_END_ADDRESS_L Register
        710. 14.1.1.710  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_6_END_ADDRESS_H Register
        711. 14.1.1.711  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_CONTROL Register
        712. 14.1.1.712  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_0 Register
        713. 14.1.1.713  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_1 Register
        714. 14.1.1.714  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_PERMISSION_2 Register
        715. 14.1.1.715  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_START_ADDRESS_L Register
        716. 14.1.1.716  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_START_ADDRESS_H Register
        717. 14.1.1.717  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_END_ADDRESS_L Register
        718. 14.1.1.718  CBASS_FW_IMSRAM32KX64E_MAIN_7_SLV_FW_REGION_7_END_ADDRESS_H Register
        719. 14.1.1.719  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_CONTROL Register
        720. 14.1.1.720  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_START_ADDRESS_L Register
        721. 14.1.1.721  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_START_ADDRESS_H Register
        722. 14.1.1.722  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_END_ADDRESS_L Register
        723. 14.1.1.723  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_0_END_ADDRESS_H Register
        724. 14.1.1.724  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_ISC_REGION_DEF_CONTROL Register
        725. 14.1.1.725  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_CONTROL Register
        726. 14.1.1.726  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_START_ADDRESS_L Register
        727. 14.1.1.727  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_START_ADDRESS_H Register
        728. 14.1.1.728  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_END_ADDRESS_L Register
        729. 14.1.1.729  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_0_END_ADDRESS_H Register
        730. 14.1.1.730  CBASS_ISC_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_ISC_REGION_DEF_CONTROL Register
        731. 14.1.1.731  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_CONTROL Register
        732. 14.1.1.732  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_START_ADDRESS_L Register
        733. 14.1.1.733  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_START_ADDRESS_H Register
        734. 14.1.1.734  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_END_ADDRESS_L Register
        735. 14.1.1.735  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_0_END_ADDRESS_H Register
        736. 14.1.1.736  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_ISC_REGION_DEF_CONTROL Register
        737. 14.1.1.737  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_CONTROL Register
        738. 14.1.1.738  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_START_ADDRESS_L Register
        739. 14.1.1.739  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_START_ADDRESS_H Register
        740. 14.1.1.740  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_END_ADDRESS_L Register
        741. 14.1.1.741  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_0_END_ADDRESS_H Register
        742. 14.1.1.742  CBASS_ISC_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_ISC_REGION_DEF_CONTROL Register
        743. 14.1.1.743  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_CONTROL Register
        744. 14.1.1.744  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_START_ADDRESS_L Register
        745. 14.1.1.745  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_START_ADDRESS_H Register
        746. 14.1.1.746  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_END_ADDRESS_L Register
        747. 14.1.1.747  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_0_END_ADDRESS_H Register
        748. 14.1.1.748  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_ISC_REGION_DEF_CONTROL Register
        749. 14.1.1.749  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_CONTROL Register
        750. 14.1.1.750  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_START_ADDRESS_L Register
        751. 14.1.1.751  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_START_ADDRESS_H Register
        752. 14.1.1.752  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_END_ADDRESS_L Register
        753. 14.1.1.753  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_0_END_ADDRESS_H Register
        754. 14.1.1.754  CBASS_ISC_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_ISC_REGION_DEF_CONTROL Register
        755. 14.1.1.755  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_CONTROL Register
        756. 14.1.1.756  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_START_ADDRESS_L Register
        757. 14.1.1.757  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_START_ADDRESS_H Register
        758. 14.1.1.758  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_END_ADDRESS_L Register
        759. 14.1.1.759  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_0_END_ADDRESS_H Register
        760. 14.1.1.760  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_RMST_ISC_REGION_DEF_CONTROL Register
        761. 14.1.1.761  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_CONTROL Register
        762. 14.1.1.762  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_START_ADDRESS_L Register
        763. 14.1.1.763  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_START_ADDRESS_H Register
        764. 14.1.1.764  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_END_ADDRESS_L Register
        765. 14.1.1.765  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_0_END_ADDRESS_H Register
        766. 14.1.1.766  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_WMST_ISC_REGION_DEF_CONTROL Register
        767. 14.1.1.767  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_CONTROL Register
        768. 14.1.1.768  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_START_ADDRESS_L Register
        769. 14.1.1.769  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_START_ADDRESS_H Register
        770. 14.1.1.770  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_END_ADDRESS_L Register
        771. 14.1.1.771  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_0_END_ADDRESS_H Register
        772. 14.1.1.772  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_RMST_ISC_REGION_DEF_CONTROL Register
        773. 14.1.1.773  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_CONTROL Register
        774. 14.1.1.774  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_START_ADDRESS_L Register
        775. 14.1.1.775  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_START_ADDRESS_H Register
        776. 14.1.1.776  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_END_ADDRESS_L Register
        777. 14.1.1.777  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_0_END_ADDRESS_H Register
        778. 14.1.1.778  CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_WMST_ISC_REGION_DEF_CONTROL Register
        779. 14.1.1.779  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_CONTROL Register
        780. 14.1.1.780  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_START_ADDRESS_L Register
        781. 14.1.1.781  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_START_ADDRESS_H Register
        782. 14.1.1.782  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_END_ADDRESS_L Register
        783. 14.1.1.783  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_0_END_ADDRESS_H Register
        784. 14.1.1.784  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_RMST_ISC_REGION_DEF_CONTROL Register
        785. 14.1.1.785  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_CONTROL Register
        786. 14.1.1.786  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_START_ADDRESS_L Register
        787. 14.1.1.787  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_START_ADDRESS_H Register
        788. 14.1.1.788  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_END_ADDRESS_L Register
        789. 14.1.1.789  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_0_END_ADDRESS_H Register
        790. 14.1.1.790  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_WMST_ISC_REGION_DEF_CONTROL Register
        791. 14.1.1.791  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_CONTROL Register
        792. 14.1.1.792  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_START_ADDRESS_L Register
        793. 14.1.1.793  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_START_ADDRESS_H Register
        794. 14.1.1.794  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_END_ADDRESS_L Register
        795. 14.1.1.795  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_0_END_ADDRESS_H Register
        796. 14.1.1.796  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_RMST_ISC_REGION_DEF_CONTROL Register
        797. 14.1.1.797  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_CONTROL Register
        798. 14.1.1.798  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_START_ADDRESS_L Register
        799. 14.1.1.799  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_START_ADDRESS_H Register
        800. 14.1.1.800  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_END_ADDRESS_L Register
        801. 14.1.1.801  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_0_END_ADDRESS_H Register
        802. 14.1.1.802  CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_WMST_ISC_REGION_DEF_CONTROL Register
        803. 14.1.1.803  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_CONTROL Register
        804. 14.1.1.804  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_L Register
        805. 14.1.1.805  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_H Register
        806. 14.1.1.806  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_L Register
        807. 14.1.1.807  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_H Register
        808. 14.1.1.808  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_CONTROL Register
        809. 14.1.1.809  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_L Register
        810. 14.1.1.810  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_H Register
        811. 14.1.1.811  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_L Register
        812. 14.1.1.812  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_H Register
        813. 14.1.1.813  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_CONTROL Register
        814. 14.1.1.814  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_L Register
        815. 14.1.1.815  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_H Register
        816. 14.1.1.816  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_L Register
        817. 14.1.1.817  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_H Register
        818. 14.1.1.818  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_CONTROL Register
        819. 14.1.1.819  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_L Register
        820. 14.1.1.820  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_H Register
        821. 14.1.1.821  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_L Register
        822. 14.1.1.822  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_H Register
        823. 14.1.1.823  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_CONTROL Register
        824. 14.1.1.824  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_L Register
        825. 14.1.1.825  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_H Register
        826. 14.1.1.826  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_L Register
        827. 14.1.1.827  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_H Register
        828. 14.1.1.828  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_CONTROL Register
        829. 14.1.1.829  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_L Register
        830. 14.1.1.830  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_H Register
        831. 14.1.1.831  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_L Register
        832. 14.1.1.832  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_H Register
        833. 14.1.1.833  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_CONTROL Register
        834. 14.1.1.834  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_L Register
        835. 14.1.1.835  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_H Register
        836. 14.1.1.836  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_L Register
        837. 14.1.1.837  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_H Register
        838. 14.1.1.838  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_CONTROL Register
        839. 14.1.1.839  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_L Register
        840. 14.1.1.840  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_H Register
        841. 14.1.1.841  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_L Register
        842. 14.1.1.842  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_H Register
        843. 14.1.1.843  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_CONTROL Register
        844. 14.1.1.844  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_L Register
        845. 14.1.1.845  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_H Register
        846. 14.1.1.846  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_L Register
        847. 14.1.1.847  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_H Register
        848. 14.1.1.848  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_CONTROL Register
        849. 14.1.1.849  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_L Register
        850. 14.1.1.850  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_H Register
        851. 14.1.1.851  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_L Register
        852. 14.1.1.852  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_H Register
        853. 14.1.1.853  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_CONTROL Register
        854. 14.1.1.854  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_L Register
        855. 14.1.1.855  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_H Register
        856. 14.1.1.856  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_L Register
        857. 14.1.1.857  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_H Register
        858. 14.1.1.858  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_CONTROL Register
        859. 14.1.1.859  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_L Register
        860. 14.1.1.860  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_H Register
        861. 14.1.1.861  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_L Register
        862. 14.1.1.862  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_H Register
        863. 14.1.1.863  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_CONTROL Register
        864. 14.1.1.864  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_L Register
        865. 14.1.1.865  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_H Register
        866. 14.1.1.866  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_L Register
        867. 14.1.1.867  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_H Register
        868. 14.1.1.868  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_CONTROL Register
        869. 14.1.1.869  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_L Register
        870. 14.1.1.870  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_H Register
        871. 14.1.1.871  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_L Register
        872. 14.1.1.872  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_H Register
        873. 14.1.1.873  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_CONTROL Register
        874. 14.1.1.874  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_L Register
        875. 14.1.1.875  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_H Register
        876. 14.1.1.876  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_L Register
        877. 14.1.1.877  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_H Register
        878. 14.1.1.878  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_CONTROL Register
        879. 14.1.1.879  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_L Register
        880. 14.1.1.880  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_H Register
        881. 14.1.1.881  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_L Register
        882. 14.1.1.882  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_H Register
        883. 14.1.1.883  CBASS_ISC_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_ISC_REGION_DEF_CONTROL Register
        884. 14.1.1.884  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_CONTROL Register
        885. 14.1.1.885  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_L Register
        886. 14.1.1.886  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_START_ADDRESS_H Register
        887. 14.1.1.887  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_L Register
        888. 14.1.1.888  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_0_END_ADDRESS_H Register
        889. 14.1.1.889  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_CONTROL Register
        890. 14.1.1.890  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_L Register
        891. 14.1.1.891  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_START_ADDRESS_H Register
        892. 14.1.1.892  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_L Register
        893. 14.1.1.893  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_1_END_ADDRESS_H Register
        894. 14.1.1.894  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_CONTROL Register
        895. 14.1.1.895  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_L Register
        896. 14.1.1.896  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_START_ADDRESS_H Register
        897. 14.1.1.897  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_L Register
        898. 14.1.1.898  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_2_END_ADDRESS_H Register
        899. 14.1.1.899  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_CONTROL Register
        900. 14.1.1.900  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_L Register
        901. 14.1.1.901  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_START_ADDRESS_H Register
        902. 14.1.1.902  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_L Register
        903. 14.1.1.903  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_3_END_ADDRESS_H Register
        904. 14.1.1.904  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_CONTROL Register
        905. 14.1.1.905  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_L Register
        906. 14.1.1.906  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_START_ADDRESS_H Register
        907. 14.1.1.907  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_L Register
        908. 14.1.1.908  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_4_END_ADDRESS_H Register
        909. 14.1.1.909  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_CONTROL Register
        910. 14.1.1.910  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_L Register
        911. 14.1.1.911  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_START_ADDRESS_H Register
        912. 14.1.1.912  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_L Register
        913. 14.1.1.913  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_5_END_ADDRESS_H Register
        914. 14.1.1.914  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_CONTROL Register
        915. 14.1.1.915  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_L Register
        916. 14.1.1.916  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_START_ADDRESS_H Register
        917. 14.1.1.917  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_L Register
        918. 14.1.1.918  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_6_END_ADDRESS_H Register
        919. 14.1.1.919  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_CONTROL Register
        920. 14.1.1.920  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_L Register
        921. 14.1.1.921  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_START_ADDRESS_H Register
        922. 14.1.1.922  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_L Register
        923. 14.1.1.923  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_7_END_ADDRESS_H Register
        924. 14.1.1.924  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_CONTROL Register
        925. 14.1.1.925  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_L Register
        926. 14.1.1.926  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_START_ADDRESS_H Register
        927. 14.1.1.927  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_L Register
        928. 14.1.1.928  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_8_END_ADDRESS_H Register
        929. 14.1.1.929  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_CONTROL Register
        930. 14.1.1.930  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_L Register
        931. 14.1.1.931  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_START_ADDRESS_H Register
        932. 14.1.1.932  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_L Register
        933. 14.1.1.933  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_9_END_ADDRESS_H Register
        934. 14.1.1.934  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_CONTROL Register
        935. 14.1.1.935  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_L Register
        936. 14.1.1.936  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_START_ADDRESS_H Register
        937. 14.1.1.937  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_L Register
        938. 14.1.1.938  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_10_END_ADDRESS_H Register
        939. 14.1.1.939  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_CONTROL Register
        940. 14.1.1.940  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_L Register
        941. 14.1.1.941  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_START_ADDRESS_H Register
        942. 14.1.1.942  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_L Register
        943. 14.1.1.943  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_11_END_ADDRESS_H Register
        944. 14.1.1.944  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_CONTROL Register
        945. 14.1.1.945  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_L Register
        946. 14.1.1.946  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_START_ADDRESS_H Register
        947. 14.1.1.947  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_L Register
        948. 14.1.1.948  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_12_END_ADDRESS_H Register
        949. 14.1.1.949  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_CONTROL Register
        950. 14.1.1.950  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_L Register
        951. 14.1.1.951  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_START_ADDRESS_H Register
        952. 14.1.1.952  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_L Register
        953. 14.1.1.953  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_13_END_ADDRESS_H Register
        954. 14.1.1.954  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_CONTROL Register
        955. 14.1.1.955  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_L Register
        956. 14.1.1.956  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_START_ADDRESS_H Register
        957. 14.1.1.957  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_L Register
        958. 14.1.1.958  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_14_END_ADDRESS_H Register
        959. 14.1.1.959  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_CONTROL Register
        960. 14.1.1.960  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_L Register
        961. 14.1.1.961  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_START_ADDRESS_H Register
        962. 14.1.1.962  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_L Register
        963. 14.1.1.963  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_15_END_ADDRESS_H Register
        964. 14.1.1.964  CBASS_ISC_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_ISC_REGION_DEF_CONTROL Register
        965. 14.1.1.965  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_CONTROL Register
        966. 14.1.1.966  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_START_ADDRESS_L Register
        967. 14.1.1.967  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_START_ADDRESS_H Register
        968. 14.1.1.968  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_END_ADDRESS_L Register
        969. 14.1.1.969  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_0_END_ADDRESS_H Register
        970. 14.1.1.970  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_CONTROL Register
        971. 14.1.1.971  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_START_ADDRESS_L Register
        972. 14.1.1.972  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_START_ADDRESS_H Register
        973. 14.1.1.973  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_END_ADDRESS_L Register
        974. 14.1.1.974  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_1_END_ADDRESS_H Register
        975. 14.1.1.975  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_CONTROL Register
        976. 14.1.1.976  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_START_ADDRESS_L Register
        977. 14.1.1.977  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_START_ADDRESS_H Register
        978. 14.1.1.978  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_END_ADDRESS_L Register
        979. 14.1.1.979  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_2_END_ADDRESS_H Register
        980. 14.1.1.980  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_CONTROL Register
        981. 14.1.1.981  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_START_ADDRESS_L Register
        982. 14.1.1.982  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_START_ADDRESS_H Register
        983. 14.1.1.983  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_END_ADDRESS_L Register
        984. 14.1.1.984  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_3_END_ADDRESS_H Register
        985. 14.1.1.985  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_CONTROL Register
        986. 14.1.1.986  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_START_ADDRESS_L Register
        987. 14.1.1.987  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_START_ADDRESS_H Register
        988. 14.1.1.988  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_END_ADDRESS_L Register
        989. 14.1.1.989  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_4_END_ADDRESS_H Register
        990. 14.1.1.990  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_CONTROL Register
        991. 14.1.1.991  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_START_ADDRESS_L Register
        992. 14.1.1.992  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_START_ADDRESS_H Register
        993. 14.1.1.993  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_END_ADDRESS_L Register
        994. 14.1.1.994  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_5_END_ADDRESS_H Register
        995. 14.1.1.995  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_CONTROL Register
        996. 14.1.1.996  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_START_ADDRESS_L Register
        997. 14.1.1.997  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_START_ADDRESS_H Register
        998. 14.1.1.998  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_END_ADDRESS_L Register
        999. 14.1.1.999  CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_6_END_ADDRESS_H Register
        1000. 14.1.1.1000 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_CONTROL Register
        1001. 14.1.1.1001 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_START_ADDRESS_L Register
        1002. 14.1.1.1002 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_START_ADDRESS_H Register
        1003. 14.1.1.1003 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_END_ADDRESS_L Register
        1004. 14.1.1.1004 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_7_END_ADDRESS_H Register
        1005. 14.1.1.1005 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_ISC_REGION_DEF_CONTROL Register
        1006. 14.1.1.1006 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_CONTROL Register
        1007. 14.1.1.1007 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_START_ADDRESS_L Register
        1008. 14.1.1.1008 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_START_ADDRESS_H Register
        1009. 14.1.1.1009 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_END_ADDRESS_L Register
        1010. 14.1.1.1010 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_0_END_ADDRESS_H Register
        1011. 14.1.1.1011 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_CONTROL Register
        1012. 14.1.1.1012 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_START_ADDRESS_L Register
        1013. 14.1.1.1013 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_START_ADDRESS_H Register
        1014. 14.1.1.1014 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_END_ADDRESS_L Register
        1015. 14.1.1.1015 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_1_END_ADDRESS_H Register
        1016. 14.1.1.1016 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_CONTROL Register
        1017. 14.1.1.1017 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_START_ADDRESS_L Register
        1018. 14.1.1.1018 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_START_ADDRESS_H Register
        1019. 14.1.1.1019 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_END_ADDRESS_L Register
        1020. 14.1.1.1020 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_2_END_ADDRESS_H Register
        1021. 14.1.1.1021 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_CONTROL Register
        1022. 14.1.1.1022 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_START_ADDRESS_L Register
        1023. 14.1.1.1023 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_START_ADDRESS_H Register
        1024. 14.1.1.1024 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_END_ADDRESS_L Register
        1025. 14.1.1.1025 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_3_END_ADDRESS_H Register
        1026. 14.1.1.1026 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_CONTROL Register
        1027. 14.1.1.1027 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_START_ADDRESS_L Register
        1028. 14.1.1.1028 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_START_ADDRESS_H Register
        1029. 14.1.1.1029 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_END_ADDRESS_L Register
        1030. 14.1.1.1030 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_4_END_ADDRESS_H Register
        1031. 14.1.1.1031 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_CONTROL Register
        1032. 14.1.1.1032 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_START_ADDRESS_L Register
        1033. 14.1.1.1033 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_START_ADDRESS_H Register
        1034. 14.1.1.1034 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_END_ADDRESS_L Register
        1035. 14.1.1.1035 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_5_END_ADDRESS_H Register
        1036. 14.1.1.1036 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_CONTROL Register
        1037. 14.1.1.1037 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_START_ADDRESS_L Register
        1038. 14.1.1.1038 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_START_ADDRESS_H Register
        1039. 14.1.1.1039 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_END_ADDRESS_L Register
        1040. 14.1.1.1040 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_6_END_ADDRESS_H Register
        1041. 14.1.1.1041 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_CONTROL Register
        1042. 14.1.1.1042 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_START_ADDRESS_L Register
        1043. 14.1.1.1043 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_START_ADDRESS_H Register
        1044. 14.1.1.1044 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_END_ADDRESS_L Register
        1045. 14.1.1.1045 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_7_END_ADDRESS_H Register
        1046. 14.1.1.1046 CBASS_ISC_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_ISC_REGION_DEF_CONTROL Register
        1047. 14.1.1.1047 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_CONTROL Register
        1048. 14.1.1.1048 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_START_ADDRESS_L Register
        1049. 14.1.1.1049 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_START_ADDRESS_H Register
        1050. 14.1.1.1050 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_END_ADDRESS_L Register
        1051. 14.1.1.1051 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_0_END_ADDRESS_H Register
        1052. 14.1.1.1052 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_ISC_REGION_DEF_CONTROL Register
        1053. 14.1.1.1053 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_CONTROL Register
        1054. 14.1.1.1054 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_START_ADDRESS_L Register
        1055. 14.1.1.1055 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_START_ADDRESS_H Register
        1056. 14.1.1.1056 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_END_ADDRESS_L Register
        1057. 14.1.1.1057 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_0_END_ADDRESS_H Register
        1058. 14.1.1.1058 CBASS_ISC_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_ISC_REGION_DEF_CONTROL Register
        1059. 14.1.1.1059 CBASS_ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_CONTROL Register
        1060. 14.1.1.1060 CBASS_ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_START_ADDRESS_L Register
        1061. 14.1.1.1061 CBASS_ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_START_ADDRESS_H Register
        1062. 14.1.1.1062 CBASS_ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_END_ADDRESS_L Register
        1063. 14.1.1.1063 CBASS_ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_0_END_ADDRESS_H Register
        1064. 14.1.1.1064 CBASS_ISC_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_ISC_REGION_DEF_CONTROL Register
        1065. 14.1.1.1065 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_CONTROL Register
        1066. 14.1.1.1066 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_START_ADDRESS_L Register
        1067. 14.1.1.1067 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_START_ADDRESS_H Register
        1068. 14.1.1.1068 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_END_ADDRESS_L Register
        1069. 14.1.1.1069 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_0_END_ADDRESS_H Register
        1070. 14.1.1.1070 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_CONTROL Register
        1071. 14.1.1.1071 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_START_ADDRESS_L Register
        1072. 14.1.1.1072 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_START_ADDRESS_H Register
        1073. 14.1.1.1073 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_END_ADDRESS_L Register
        1074. 14.1.1.1074 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_1_END_ADDRESS_H Register
        1075. 14.1.1.1075 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_CONTROL Register
        1076. 14.1.1.1076 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_START_ADDRESS_L Register
        1077. 14.1.1.1077 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_START_ADDRESS_H Register
        1078. 14.1.1.1078 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_END_ADDRESS_L Register
        1079. 14.1.1.1079 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_2_END_ADDRESS_H Register
        1080. 14.1.1.1080 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_CONTROL Register
        1081. 14.1.1.1081 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_START_ADDRESS_L Register
        1082. 14.1.1.1082 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_START_ADDRESS_H Register
        1083. 14.1.1.1083 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_END_ADDRESS_L Register
        1084. 14.1.1.1084 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_3_END_ADDRESS_H Register
        1085. 14.1.1.1085 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_CONTROL Register
        1086. 14.1.1.1086 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_START_ADDRESS_L Register
        1087. 14.1.1.1087 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_START_ADDRESS_H Register
        1088. 14.1.1.1088 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_END_ADDRESS_L Register
        1089. 14.1.1.1089 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_4_END_ADDRESS_H Register
        1090. 14.1.1.1090 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_CONTROL Register
        1091. 14.1.1.1091 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_START_ADDRESS_L Register
        1092. 14.1.1.1092 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_START_ADDRESS_H Register
        1093. 14.1.1.1093 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_END_ADDRESS_L Register
        1094. 14.1.1.1094 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_5_END_ADDRESS_H Register
        1095. 14.1.1.1095 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_CONTROL Register
        1096. 14.1.1.1096 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_START_ADDRESS_L Register
        1097. 14.1.1.1097 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_START_ADDRESS_H Register
        1098. 14.1.1.1098 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_END_ADDRESS_L Register
        1099. 14.1.1.1099 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_6_END_ADDRESS_H Register
        1100. 14.1.1.1100 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_CONTROL Register
        1101. 14.1.1.1101 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_START_ADDRESS_L Register
        1102. 14.1.1.1102 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_START_ADDRESS_H Register
        1103. 14.1.1.1103 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_END_ADDRESS_L Register
        1104. 14.1.1.1104 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_7_END_ADDRESS_H Register
        1105. 14.1.1.1105 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_ISC_REGION_DEF_CONTROL Register
        1106. 14.1.1.1106 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_CONTROL Register
        1107. 14.1.1.1107 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_START_ADDRESS_L Register
        1108. 14.1.1.1108 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_START_ADDRESS_H Register
        1109. 14.1.1.1109 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_END_ADDRESS_L Register
        1110. 14.1.1.1110 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_0_END_ADDRESS_H Register
        1111. 14.1.1.1111 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_CONTROL Register
        1112. 14.1.1.1112 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_START_ADDRESS_L Register
        1113. 14.1.1.1113 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_START_ADDRESS_H Register
        1114. 14.1.1.1114 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_END_ADDRESS_L Register
        1115. 14.1.1.1115 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_1_END_ADDRESS_H Register
        1116. 14.1.1.1116 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_CONTROL Register
        1117. 14.1.1.1117 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_START_ADDRESS_L Register
        1118. 14.1.1.1118 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_START_ADDRESS_H Register
        1119. 14.1.1.1119 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_END_ADDRESS_L Register
        1120. 14.1.1.1120 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_2_END_ADDRESS_H Register
        1121. 14.1.1.1121 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_CONTROL Register
        1122. 14.1.1.1122 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_START_ADDRESS_L Register
        1123. 14.1.1.1123 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_START_ADDRESS_H Register
        1124. 14.1.1.1124 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_END_ADDRESS_L Register
        1125. 14.1.1.1125 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_3_END_ADDRESS_H Register
        1126. 14.1.1.1126 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_CONTROL Register
        1127. 14.1.1.1127 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_START_ADDRESS_L Register
        1128. 14.1.1.1128 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_START_ADDRESS_H Register
        1129. 14.1.1.1129 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_END_ADDRESS_L Register
        1130. 14.1.1.1130 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_4_END_ADDRESS_H Register
        1131. 14.1.1.1131 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_CONTROL Register
        1132. 14.1.1.1132 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_START_ADDRESS_L Register
        1133. 14.1.1.1133 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_START_ADDRESS_H Register
        1134. 14.1.1.1134 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_END_ADDRESS_L Register
        1135. 14.1.1.1135 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_5_END_ADDRESS_H Register
        1136. 14.1.1.1136 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_CONTROL Register
        1137. 14.1.1.1137 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_START_ADDRESS_L Register
        1138. 14.1.1.1138 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_START_ADDRESS_H Register
        1139. 14.1.1.1139 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_END_ADDRESS_L Register
        1140. 14.1.1.1140 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_6_END_ADDRESS_H Register
        1141. 14.1.1.1141 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_CONTROL Register
        1142. 14.1.1.1142 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_START_ADDRESS_L Register
        1143. 14.1.1.1143 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_START_ADDRESS_H Register
        1144. 14.1.1.1144 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_END_ADDRESS_L Register
        1145. 14.1.1.1145 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_7_END_ADDRESS_H Register
        1146. 14.1.1.1146 CBASS_ISC_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_ISC_REGION_DEF_CONTROL Register
        1147. 14.1.1.1147 CBASS_ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_CONTROL Register
        1148. 14.1.1.1148 CBASS_ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_START_ADDRESS_L Register
        1149. 14.1.1.1149 CBASS_ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_START_ADDRESS_H Register
        1150. 14.1.1.1150 CBASS_ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_END_ADDRESS_L Register
        1151. 14.1.1.1151 CBASS_ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_0_END_ADDRESS_H Register
        1152. 14.1.1.1152 CBASS_ISC_IJ7_LED_MAIN_0_VBUSP_ISC_REGION_DEF_CONTROL Register
        1153. 14.1.1.1153 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_CONTROL Register
        1154. 14.1.1.1154 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_START_ADDRESS_L Register
        1155. 14.1.1.1155 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_START_ADDRESS_H Register
        1156. 14.1.1.1156 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_END_ADDRESS_L Register
        1157. 14.1.1.1157 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_0_END_ADDRESS_H Register
        1158. 14.1.1.1158 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_ISC_REGION_DEF_CONTROL Register
        1159. 14.1.1.1159 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_CONTROL Register
        1160. 14.1.1.1160 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_START_ADDRESS_L Register
        1161. 14.1.1.1161 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_START_ADDRESS_H Register
        1162. 14.1.1.1162 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_END_ADDRESS_L Register
        1163. 14.1.1.1163 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_0_END_ADDRESS_H Register
        1164. 14.1.1.1164 CBASS_ISC_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_ISC_REGION_DEF_CONTROL Register
        1165. 14.1.1.1165 CBASS_GLB_PID Register
        1166. 14.1.1.1166 CBASS_GLB_DESTINATION_ID Register
        1167. 14.1.1.1167 CBASS_GLB_EXCEPTION_LOGGING_CONTROL Register
        1168. 14.1.1.1168 CBASS_GLB_EXCEPTION_LOGGING_HEADER0 Register
        1169. 14.1.1.1169 CBASS_GLB_EXCEPTION_LOGGING_HEADER1 Register
        1170. 14.1.1.1170 CBASS_GLB_EXCEPTION_LOGGING_DATA0 Register
        1171. 14.1.1.1171 CBASS_GLB_EXCEPTION_LOGGING_DATA1 Register
        1172. 14.1.1.1172 CBASS_GLB_EXCEPTION_LOGGING_DATA2 Register
        1173. 14.1.1.1173 CBASS_GLB_EXCEPTION_LOGGING_DATA3 Register
        1174. 14.1.1.1174 CBASS_GLB_EXCEPTION_PEND_SET Register
        1175. 14.1.1.1175 CBASS_GLB_EXCEPTION_PEND_CLEAR Register
        1176. 14.1.1.1176 CBASS_QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_R_MAP0 Register
        1177. 14.1.1.1177 CBASS_QOS_ISAM64_A53_256KB_WRAP_MAIN_0_A53_DUAL_WRAP_CBA_AXI_W_MAP0 Register
        1178. 14.1.1.1178 CBASS_QOS_IEMMC8SS_16FFC_MAIN_0_EMMCSS_WR_MAP0 Register
        1179. 14.1.1.1179 CBASS_QOS_IEMMC8SS_16FFC_MAIN_0_EMMCSS_RD_MAP0 Register
        1180. 14.1.1.1180 CBASS_QOS_IGIC500SS_1_2_MAIN_0_MEM_WR_VBUSM_MAP0 Register
        1181. 14.1.1.1181 CBASS_QOS_IGIC500SS_1_2_MAIN_0_MEM_RD_VBUSM_MAP0 Register
        1182. 14.1.1.1182 CBASS_QOS_IPULSAR_LITE_MAIN_0_CPU0_RMST_MAP0 Register
        1183. 14.1.1.1183 CBASS_QOS_IPULSAR_LITE_MAIN_0_CPU0_WMST_MAP0 Register
        1184. 14.1.1.1184 CBASS_QOS_IPULSAR_LITE_MAIN_0_CPU1_RMST_MAP0 Register
        1185. 14.1.1.1185 CBASS_QOS_IPULSAR_LITE_MAIN_0_CPU1_WMST_MAP0 Register
        1186. 14.1.1.1186 CBASS_QOS_IPULSAR_LITE_MAIN_1_CPU0_RMST_MAP0 Register
        1187. 14.1.1.1187 CBASS_QOS_IPULSAR_LITE_MAIN_1_CPU0_WMST_MAP0 Register
        1188. 14.1.1.1188 CBASS_QOS_IPULSAR_LITE_MAIN_1_CPU1_RMST_MAP0 Register
        1189. 14.1.1.1189 CBASS_QOS_IPULSAR_LITE_MAIN_1_CPU1_WMST_MAP0 Register
        1190. 14.1.1.1190 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP0 Register
        1191. 14.1.1.1191 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP1 Register
        1192. 14.1.1.1192 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP2 Register
        1193. 14.1.1.1193 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP3 Register
        1194. 14.1.1.1194 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP4 Register
        1195. 14.1.1.1195 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP5 Register
        1196. 14.1.1.1196 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP6 Register
        1197. 14.1.1.1197 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP7 Register
        1198. 14.1.1.1198 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP8 Register
        1199. 14.1.1.1199 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP9 Register
        1200. 14.1.1.1200 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP10 Register
        1201. 14.1.1.1201 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP11 Register
        1202. 14.1.1.1202 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP12 Register
        1203. 14.1.1.1203 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP13 Register
        1204. 14.1.1.1204 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP14 Register
        1205. 14.1.1.1205 CBASS_QOS_IICSS_G_16FF_MAIN_0_PR1_EXT_VBUSM_MAP15 Register
        1206. 14.1.1.1206 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP0 Register
        1207. 14.1.1.1207 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP1 Register
        1208. 14.1.1.1208 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP2 Register
        1209. 14.1.1.1209 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP3 Register
        1210. 14.1.1.1210 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP4 Register
        1211. 14.1.1.1211 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP5 Register
        1212. 14.1.1.1212 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP6 Register
        1213. 14.1.1.1213 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP7 Register
        1214. 14.1.1.1214 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP8 Register
        1215. 14.1.1.1215 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP9 Register
        1216. 14.1.1.1216 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP10 Register
        1217. 14.1.1.1217 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP11 Register
        1218. 14.1.1.1218 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP12 Register
        1219. 14.1.1.1219 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP13 Register
        1220. 14.1.1.1220 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP14 Register
        1221. 14.1.1.1221 CBASS_QOS_IICSS_G_16FF_MAIN_1_PR1_EXT_VBUSM_MAP15 Register
        1222. 14.1.1.1222 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP0 Register
        1223. 14.1.1.1223 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP1 Register
        1224. 14.1.1.1224 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP2 Register
        1225. 14.1.1.1225 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP3 Register
        1226. 14.1.1.1226 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP4 Register
        1227. 14.1.1.1227 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP5 Register
        1228. 14.1.1.1228 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP6 Register
        1229. 14.1.1.1229 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_RD_MAP7 Register
        1230. 14.1.1.1230 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP0 Register
        1231. 14.1.1.1231 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP1 Register
        1232. 14.1.1.1232 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP2 Register
        1233. 14.1.1.1233 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP3 Register
        1234. 14.1.1.1234 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP4 Register
        1235. 14.1.1.1235 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP5 Register
        1236. 14.1.1.1236 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP6 Register
        1237. 14.1.1.1237 CBASS_QOS_IPCIE_G2X1_64_MAIN_0_PCIE_MST_WR_MAP7 Register
        1238. 14.1.1.1238 CBASS_QOS_IEMMCSD4SS_MAIN_0_EMMCSDSS_WR_MAP0 Register
        1239. 14.1.1.1239 CBASS_QOS_IEMMCSD4SS_MAIN_0_EMMCSDSS_RD_MAP0 Register
        1240. 14.1.1.1240 CBASS_QOS_ISA2_UL_MAIN_0_CTXCACH_EXT_DMA_MAP0 Register
        1241. 14.1.1.1241 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP0 Register
        1242. 14.1.1.1242 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP1 Register
        1243. 14.1.1.1243 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP2 Register
        1244. 14.1.1.1244 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP3 Register
        1245. 14.1.1.1245 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP4 Register
        1246. 14.1.1.1246 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP5 Register
        1247. 14.1.1.1247 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP6 Register
        1248. 14.1.1.1248 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTR0_MAP7 Register
        1249. 14.1.1.1249 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP0 Register
        1250. 14.1.1.1250 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP1 Register
        1251. 14.1.1.1251 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP2 Register
        1252. 14.1.1.1252 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP3 Register
        1253. 14.1.1.1253 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP4 Register
        1254. 14.1.1.1254 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP5 Register
        1255. 14.1.1.1255 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP6 Register
        1256. 14.1.1.1256 CBASS_QOS_IUSB3P0SS64_16FFC_MAIN_0_MSTW0_MAP7 Register
        1257. 14.1.1.1257 CBASS_QOS_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR_MAP0 Register
        1258. 14.1.1.1258 CBASS_QOS_IDEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW_MAP0 Register
      2. 14.1.2 MCU_CBASS Registers
        1. 14.1.2.1  MCU_CBASS Summary Table
        2. 14.1.2.2  CBASS_ERR_PID Register
        3. 14.1.2.3  CBASS_ERR_DESTINATION_ID Register
        4. 14.1.2.4  CBASS_ERR_EXCEPTION_LOGGING_HEADER0 Register
        5. 14.1.2.5  CBASS_ERR_EXCEPTION_LOGGING_HEADER1 Register
        6. 14.1.2.6  CBASS_ERR_EXCEPTION_LOGGING_DATA0 Register
        7. 14.1.2.7  CBASS_ERR_EXCEPTION_LOGGING_DATA1 Register
        8. 14.1.2.8  CBASS_ERR_EXCEPTION_LOGGING_DATA2 Register
        9. 14.1.2.9  CBASS_ERR_EXCEPTION_LOGGING_DATA3 Register
        10. 14.1.2.10 CBASS_ERR_ERR_INTR_RAW_STAT Register
        11. 14.1.2.11 CBASS_ERR_ERR_INTR_ENABLED_STAT Register
        12. 14.1.2.12 CBASS_ERR_ERR_INTR_ENABLE_SET Register
        13. 14.1.2.13 CBASS_ERR_ERR_INTR_ENABLE_CLR Register
        14. 14.1.2.14 CBASS_ERR_EOI Register
        15. 14.1.2.15 CBASS_ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_CONTROL Register
        16. 14.1.2.16 CBASS_ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_START_ADDRESS_L Register
        17. 14.1.2.17 CBASS_ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_START_ADDRESS_H Register
        18. 14.1.2.18 CBASS_ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_END_ADDRESS_L Register
        19. 14.1.2.19 CBASS_ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_0_END_ADDRESS_H Register
        20. 14.1.2.20 CBASS_ISC_IBLAZAR_MCU_0_VBUSP_M_ISC_REGION_DEF_CONTROL Register
        21. 14.1.2.21 CBASS_GLB_PID Register
        22. 14.1.2.22 CBASS_QOS_IBLAZAR_MCU_0_VBUSP_M_MAP0 Register
      3. 14.1.3 cbass_fw
        1. 14.1.3.1 cbass_fw Summaries
          1.        4027
        2. 14.1.3.2 cbass_fw Registers
          1. 14.1.3.2.1  CBASS_ERR_PID Register
          2. 14.1.3.2.2  CBASS_ERR_DESTINATION_ID Register
          3. 14.1.3.2.3  CBASS_ERR_EXCEPTION_LOGGING_HEADER0 Register
          4. 14.1.3.2.4  CBASS_ERR_EXCEPTION_LOGGING_HEADER1 Register
          5. 14.1.3.2.5  CBASS_ERR_EXCEPTION_LOGGING_DATA0 Register
          6. 14.1.3.2.6  CBASS_ERR_EXCEPTION_LOGGING_DATA1 Register
          7. 14.1.3.2.7  CBASS_ERR_EXCEPTION_LOGGING_DATA2 Register
          8. 14.1.3.2.8  CBASS_ERR_EXCEPTION_LOGGING_DATA3 Register
          9. 14.1.3.2.9  CBASS_ERR_ERR_INTR_RAW_STAT Register
          10. 14.1.3.2.10 CBASS_ERR_ERR_INTR_ENABLED_STAT Register
          11. 14.1.3.2.11 CBASS_ERR_ERR_INTR_ENABLE_SET Register
          12. 14.1.3.2.12 CBASS_ERR_ERR_INTR_ENABLE_CLR Register
          13. 14.1.3.2.13 CBASS_ERR_EOI Register
      4. 14.1.4 CBASS_INFRA Registers
        1. 14.1.4.1   CBASS_INFRA Summary Table
        2. 14.1.4.2   CBASS_ERR_PID Register
        3. 14.1.4.3   CBASS_ERR_DESTINATION_ID Register
        4. 14.1.4.4   CBASS_ERR_EXCEPTION_LOGGING_HEADER0 Register
        5. 14.1.4.5   CBASS_ERR_EXCEPTION_LOGGING_HEADER1 Register
        6. 14.1.4.6   CBASS_ERR_EXCEPTION_LOGGING_DATA0 Register
        7. 14.1.4.7   CBASS_ERR_EXCEPTION_LOGGING_DATA1 Register
        8. 14.1.4.8   CBASS_ERR_EXCEPTION_LOGGING_DATA2 Register
        9. 14.1.4.9   CBASS_ERR_EXCEPTION_LOGGING_DATA3 Register
        10. 14.1.4.10  CBASS_ERR_ERR_INTR_RAW_STAT Register
        11. 14.1.4.11  CBASS_ERR_ERR_INTR_ENABLED_STAT Register
        12. 14.1.4.12  CBASS_ERR_ERR_INTR_ENABLE_SET Register
        13. 14.1.4.13  CBASS_ERR_ERR_INTR_ENABLE_CLR Register
        14. 14.1.4.14  CBASS_ERR_EOI Register
        15. 14.1.4.15  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_CONTROL Register
        16. 14.1.4.16  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_0 Register
        17. 14.1.4.17  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_1 Register
        18. 14.1.4.18  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_PERMISSION_2 Register
        19. 14.1.4.19  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_START_ADDRESS_L Register
        20. 14.1.4.20  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_START_ADDRESS_H Register
        21. 14.1.4.21  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_END_ADDRESS_L Register
        22. 14.1.4.22  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_0_END_ADDRESS_H Register
        23. 14.1.4.23  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_CONTROL Register
        24. 14.1.4.24  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_0 Register
        25. 14.1.4.25  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_1 Register
        26. 14.1.4.26  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_PERMISSION_2 Register
        27. 14.1.4.27  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_START_ADDRESS_L Register
        28. 14.1.4.28  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_START_ADDRESS_H Register
        29. 14.1.4.29  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_END_ADDRESS_L Register
        30. 14.1.4.30  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_1_END_ADDRESS_H Register
        31. 14.1.4.31  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_CONTROL Register
        32. 14.1.4.32  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_0 Register
        33. 14.1.4.33  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_1 Register
        34. 14.1.4.34  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_PERMISSION_2 Register
        35. 14.1.4.35  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_START_ADDRESS_L Register
        36. 14.1.4.36  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_START_ADDRESS_H Register
        37. 14.1.4.37  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_END_ADDRESS_L Register
        38. 14.1.4.38  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_2_END_ADDRESS_H Register
        39. 14.1.4.39  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_CONTROL Register
        40. 14.1.4.40  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_0 Register
        41. 14.1.4.41  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_1 Register
        42. 14.1.4.42  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_PERMISSION_2 Register
        43. 14.1.4.43  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_START_ADDRESS_L Register
        44. 14.1.4.44  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_START_ADDRESS_H Register
        45. 14.1.4.45  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_END_ADDRESS_L Register
        46. 14.1.4.46  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_3_END_ADDRESS_H Register
        47. 14.1.4.47  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_CONTROL Register
        48. 14.1.4.48  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_0 Register
        49. 14.1.4.49  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_1 Register
        50. 14.1.4.50  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_PERMISSION_2 Register
        51. 14.1.4.51  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_START_ADDRESS_L Register
        52. 14.1.4.52  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_START_ADDRESS_H Register
        53. 14.1.4.53  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_END_ADDRESS_L Register
        54. 14.1.4.54  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_4_END_ADDRESS_H Register
        55. 14.1.4.55  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_CONTROL Register
        56. 14.1.4.56  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_0 Register
        57. 14.1.4.57  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_1 Register
        58. 14.1.4.58  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_PERMISSION_2 Register
        59. 14.1.4.59  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_START_ADDRESS_L Register
        60. 14.1.4.60  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_START_ADDRESS_H Register
        61. 14.1.4.61  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_END_ADDRESS_L Register
        62. 14.1.4.62  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_5_END_ADDRESS_H Register
        63. 14.1.4.63  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_CONTROL Register
        64. 14.1.4.64  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_0 Register
        65. 14.1.4.65  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_1 Register
        66. 14.1.4.66  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_PERMISSION_2 Register
        67. 14.1.4.67  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_START_ADDRESS_L Register
        68. 14.1.4.68  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_START_ADDRESS_H Register
        69. 14.1.4.69  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_END_ADDRESS_L Register
        70. 14.1.4.70  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_6_END_ADDRESS_H Register
        71. 14.1.4.71  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_CONTROL Register
        72. 14.1.4.72  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_0 Register
        73. 14.1.4.73  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_1 Register
        74. 14.1.4.74  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_PERMISSION_2 Register
        75. 14.1.4.75  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_START_ADDRESS_L Register
        76. 14.1.4.76  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_START_ADDRESS_H Register
        77. 14.1.4.77  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_END_ADDRESS_L Register
        78. 14.1.4.78  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP0_32B_CLK4_L0_FW_REGION_7_END_ADDRESS_H Register
        79. 14.1.4.79  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_CONTROL Register
        80. 14.1.4.80  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_0 Register
        81. 14.1.4.81  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_1 Register
        82. 14.1.4.82  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_PERMISSION_2 Register
        83. 14.1.4.83  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_START_ADDRESS_L Register
        84. 14.1.4.84  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_START_ADDRESS_H Register
        85. 14.1.4.85  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_END_ADDRESS_L Register
        86. 14.1.4.86  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_0_END_ADDRESS_H Register
        87. 14.1.4.87  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_CONTROL Register
        88. 14.1.4.88  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_0 Register
        89. 14.1.4.89  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_1 Register
        90. 14.1.4.90  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_PERMISSION_2 Register
        91. 14.1.4.91  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_START_ADDRESS_L Register
        92. 14.1.4.92  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_START_ADDRESS_H Register
        93. 14.1.4.93  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_END_ADDRESS_L Register
        94. 14.1.4.94  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_1_END_ADDRESS_H Register
        95. 14.1.4.95  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_CONTROL Register
        96. 14.1.4.96  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_0 Register
        97. 14.1.4.97  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_1 Register
        98. 14.1.4.98  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_PERMISSION_2 Register
        99. 14.1.4.99  CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_START_ADDRESS_L Register
        100. 14.1.4.100 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_START_ADDRESS_H Register
        101. 14.1.4.101 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_END_ADDRESS_L Register
        102. 14.1.4.102 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_2_END_ADDRESS_H Register
        103. 14.1.4.103 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_CONTROL Register
        104. 14.1.4.104 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_0 Register
        105. 14.1.4.105 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_1 Register
        106. 14.1.4.106 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_PERMISSION_2 Register
        107. 14.1.4.107 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_START_ADDRESS_L Register
        108. 14.1.4.108 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_START_ADDRESS_H Register
        109. 14.1.4.109 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_END_ADDRESS_L Register
        110. 14.1.4.110 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_3_END_ADDRESS_H Register
        111. 14.1.4.111 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_CONTROL Register
        112. 14.1.4.112 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_0 Register
        113. 14.1.4.113 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_1 Register
        114. 14.1.4.114 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_PERMISSION_2 Register
        115. 14.1.4.115 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_START_ADDRESS_L Register
        116. 14.1.4.116 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_START_ADDRESS_H Register
        117. 14.1.4.117 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_END_ADDRESS_L Register
        118. 14.1.4.118 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_4_END_ADDRESS_H Register
        119. 14.1.4.119 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_CONTROL Register
        120. 14.1.4.120 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_0 Register
        121. 14.1.4.121 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_1 Register
        122. 14.1.4.122 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_PERMISSION_2 Register
        123. 14.1.4.123 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_START_ADDRESS_L Register
        124. 14.1.4.124 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_START_ADDRESS_H Register
        125. 14.1.4.125 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_END_ADDRESS_L Register
        126. 14.1.4.126 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_5_END_ADDRESS_H Register
        127. 14.1.4.127 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_CONTROL Register
        128. 14.1.4.128 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_0 Register
        129. 14.1.4.129 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_1 Register
        130. 14.1.4.130 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_PERMISSION_2 Register
        131. 14.1.4.131 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_START_ADDRESS_L Register
        132. 14.1.4.132 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_START_ADDRESS_H Register
        133. 14.1.4.133 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_END_ADDRESS_L Register
        134. 14.1.4.134 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_6_END_ADDRESS_H Register
        135. 14.1.4.135 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_CONTROL Register
        136. 14.1.4.136 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_0 Register
        137. 14.1.4.137 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_1 Register
        138. 14.1.4.138 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_PERMISSION_2 Register
        139. 14.1.4.139 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_START_ADDRESS_L Register
        140. 14.1.4.140 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_START_ADDRESS_H Register
        141. 14.1.4.141 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_END_ADDRESS_L Register
        142. 14.1.4.142 CBASS_FW_BR_SCRP_32B_MOTOR_TO_SCRP_32B_MISCIO_L0_FW_REGION_7_END_ADDRESS_H Register
        143. 14.1.4.143 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_CONTROL Register
        144. 14.1.4.144 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_START_ADDRESS_L Register
        145. 14.1.4.145 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_START_ADDRESS_H Register
        146. 14.1.4.146 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_END_ADDRESS_L Register
        147. 14.1.4.147 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_0_END_ADDRESS_H Register
        148. 14.1.4.148 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU0_PMST_ISC_REGION_DEF_CONTROL Register
        149. 14.1.4.149 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_CONTROL Register
        150. 14.1.4.150 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_START_ADDRESS_L Register
        151. 14.1.4.151 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_START_ADDRESS_H Register
        152. 14.1.4.152 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_END_ADDRESS_L Register
        153. 14.1.4.153 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_0_END_ADDRESS_H Register
        154. 14.1.4.154 CBASS_ISC_IPULSAR_LITE_MAIN_0_CPU1_PMST_ISC_REGION_DEF_CONTROL Register
        155. 14.1.4.155 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_CONTROL Register
        156. 14.1.4.156 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_START_ADDRESS_L Register
        157. 14.1.4.157 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_START_ADDRESS_H Register
        158. 14.1.4.158 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_END_ADDRESS_L Register
        159. 14.1.4.159 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_0_END_ADDRESS_H Register
        160. 14.1.4.160 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU0_PMST_ISC_REGION_DEF_CONTROL Register
        161. 14.1.4.161 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_CONTROL Register
        162. 14.1.4.162 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_START_ADDRESS_L Register
        163. 14.1.4.163 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_START_ADDRESS_H Register
        164. 14.1.4.164 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_END_ADDRESS_L Register
        165. 14.1.4.165 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_0_END_ADDRESS_H Register
        166. 14.1.4.166 CBASS_ISC_IPULSAR_LITE_MAIN_1_CPU1_PMST_ISC_REGION_DEF_CONTROL Register
        167. 14.1.4.167 CBASS_GLB_PID Register
        168. 14.1.4.168 CBASS_GLB_DESTINATION_ID Register
        169. 14.1.4.169 CBASS_GLB_EXCEPTION_LOGGING_CONTROL Register
        170. 14.1.4.170 CBASS_GLB_EXCEPTION_LOGGING_HEADER0 Register
        171. 14.1.4.171 CBASS_GLB_EXCEPTION_LOGGING_HEADER1 Register
        172. 14.1.4.172 CBASS_GLB_EXCEPTION_LOGGING_DATA0 Register
        173. 14.1.4.173 CBASS_GLB_EXCEPTION_LOGGING_DATA1 Register
        174. 14.1.4.174 CBASS_GLB_EXCEPTION_LOGGING_DATA2 Register
        175. 14.1.4.175 CBASS_GLB_EXCEPTION_LOGGING_DATA3 Register
        176. 14.1.4.176 CBASS_GLB_EXCEPTION_PEND_SET Register
        177. 14.1.4.177 CBASS_GLB_EXCEPTION_PEND_CLEAR Register
        178. 14.1.4.178 CBASS_QOS_IPULSAR_LITE_MAIN_0_CPU0_PMST_MAP0 Register
        179. 14.1.4.179 CBASS_QOS_IPULSAR_LITE_MAIN_0_CPU1_PMST_MAP0 Register
        180. 14.1.4.180 CBASS_QOS_IPULSAR_LITE_MAIN_1_CPU0_PMST_MAP0 Register
        181. 14.1.4.181 CBASS_QOS_IPULSAR_LITE_MAIN_1_CPU1_PMST_MAP0 Register
      5. 14.1.5 cbass_dbg
        1. 14.1.5.1 cbass_dbg Summaries
          1.        4226
        2. 14.1.5.2 cbass_dbg Registers
          1. 14.1.5.2.1  CBASS_ERR_PID Register
          2. 14.1.5.2.2  CBASS_ERR_DESTINATION_ID Register
          3. 14.1.5.2.3  CBASS_ERR_EXCEPTION_LOGGING_HEADER0 Register
          4. 14.1.5.2.4  CBASS_ERR_EXCEPTION_LOGGING_HEADER1 Register
          5. 14.1.5.2.5  CBASS_ERR_EXCEPTION_LOGGING_DATA0 Register
          6. 14.1.5.2.6  CBASS_ERR_EXCEPTION_LOGGING_DATA1 Register
          7. 14.1.5.2.7  CBASS_ERR_EXCEPTION_LOGGING_DATA2 Register
          8. 14.1.5.2.8  CBASS_ERR_EXCEPTION_LOGGING_DATA3 Register
          9. 14.1.5.2.9  CBASS_ERR_ERR_INTR_RAW_STAT Register
          10. 14.1.5.2.10 CBASS_ERR_ERR_INTR_ENABLED_STAT Register
          11. 14.1.5.2.11 CBASS_ERR_ERR_INTR_ENABLE_SET Register
          12. 14.1.5.2.12 CBASS_ERR_ERR_INTR_ENABLE_CLR Register
          13. 14.1.5.2.13 CBASS_ERR_EOI Register
    2. 14.2  Device Configuration Registers
      1. 14.2.1 CTRL_MMR Registers
        1. 14.2.1.1 General Purpose Control Registers
          1. 14.2.1.1.1 main_ctrl_mmr
            1. 14.2.1.1.1.1 main_ctrl_mmr Summaries
              1.          4246
            2. 14.2.1.1.1.2 main_ctrl_mmr Registers
              1. 14.2.1.1.1.2.1   MAIN_CTRL_MMR_CFG0_PID Register
              2. 14.2.1.1.1.2.2   MAIN_CTRL_MMR_CFG0_MMR_CFG1 Register
              3. 14.2.1.1.1.2.3   MAIN_CTRL_MMR_CFG0_JTAGID Register
              4. 14.2.1.1.1.2.4   MAIN_CTRL_MMR_CFG0_JTAG_USER_ID Register
              5. 14.2.1.1.1.2.5   MAIN_CTRL_MMR_CFG0_MAIN_DEVSTAT Register
              6. 14.2.1.1.1.2.6   MAIN_CTRL_MMR_CFG0_MAIN_BOOTCFG Register
              7. 14.2.1.1.1.2.7   MAIN_CTRL_MMR_CFG0_BOOT_PROGRESS Register
              8. 14.2.1.1.1.2.8   MAIN_CTRL_MMR_CFG0_DEVICE_FEATURE0 Register
              9. 14.2.1.1.1.2.9   MAIN_CTRL_MMR_CFG0_DEVICE_FEATURE2 Register
              10. 14.2.1.1.1.2.10  MAIN_CTRL_MMR_CFG0_DEVICE_FEATURE6 Register
              11. 14.2.1.1.1.2.11  MAIN_CTRL_MMR_CFG0_MAC_ID0 Register
              12. 14.2.1.1.1.2.12  MAIN_CTRL_MMR_CFG0_MAC_ID1 Register
              13. 14.2.1.1.1.2.13  MAIN_CTRL_MMR_CFG0_PCI_DEVICE_ID0 Register
              14. 14.2.1.1.1.2.14  MAIN_CTRL_MMR_CFG0_PCI_DEVICE_ID1 Register
              15. 14.2.1.1.1.2.15  MAIN_CTRL_MMR_CFG0_USB_DEVICE_ID0 Register
              16. 14.2.1.1.1.2.16  MAIN_CTRL_MMR_CFG0_GP_SW0 Register
              17. 14.2.1.1.1.2.17  MAIN_CTRL_MMR_CFG0_GP_SW1 Register
              18. 14.2.1.1.1.2.18  MAIN_CTRL_MMR_CFG0_GP_SW2 Register
              19. 14.2.1.1.1.2.19  MAIN_CTRL_MMR_CFG0_GP_SW3 Register
              20. 14.2.1.1.1.2.20  MAIN_CTRL_MMR_CFG0_CBA_ERR_STAT Register
              21. 14.2.1.1.1.2.21  MAIN_CTRL_MMR_CFG0_LOCK0_KICK0 Register
              22. 14.2.1.1.1.2.22  MAIN_CTRL_MMR_CFG0_LOCK0_KICK1 Register
              23. 14.2.1.1.1.2.23  MAIN_CTRL_MMR_CFG0_INTR_RAW_STATUS Register
              24. 14.2.1.1.1.2.24  MAIN_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR Register
              25. 14.2.1.1.1.2.25  MAIN_CTRL_MMR_CFG0_INTR_ENABLE Register
              26. 14.2.1.1.1.2.26  MAIN_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR Register
              27. 14.2.1.1.1.2.27  MAIN_CTRL_MMR_CFG0_EOI Register
              28. 14.2.1.1.1.2.28  MAIN_CTRL_MMR_CFG0_FAULT_ADDRESS Register
              29. 14.2.1.1.1.2.29  MAIN_CTRL_MMR_CFG0_FAULT_TYPE_STATUS Register
              30. 14.2.1.1.1.2.30  MAIN_CTRL_MMR_CFG0_FAULT_ATTR_STATUS Register
              31. 14.2.1.1.1.2.31  MAIN_CTRL_MMR_CFG0_FAULT_CLEAR Register
              32. 14.2.1.1.1.2.32  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R0_READONLY Register
              33. 14.2.1.1.1.2.33  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R1_READONLY Register
              34. 14.2.1.1.1.2.34  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R2_READONLY Register
              35. 14.2.1.1.1.2.35  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R3_READONLY Register
              36. 14.2.1.1.1.2.36  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R4_READONLY Register
              37. 14.2.1.1.1.2.37  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R5_READONLY Register
              38. 14.2.1.1.1.2.38  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R6_READONLY Register
              39. 14.2.1.1.1.2.39  MAIN_CTRL_MMR_CFG0_PID_PROXY Register
              40. 14.2.1.1.1.2.40  MAIN_CTRL_MMR_CFG0_MMR_CFG1_PROXY Register
              41. 14.2.1.1.1.2.41  MAIN_CTRL_MMR_CFG0_JTAGID_PROXY Register
              42. 14.2.1.1.1.2.42  MAIN_CTRL_MMR_CFG0_JTAG_USER_ID_PROXY Register
              43. 14.2.1.1.1.2.43  MAIN_CTRL_MMR_CFG0_MAIN_DEVSTAT_PROXY Register
              44. 14.2.1.1.1.2.44  MAIN_CTRL_MMR_CFG0_MAIN_BOOTCFG_PROXY Register
              45. 14.2.1.1.1.2.45  MAIN_CTRL_MMR_CFG0_BOOT_PROGRESS_PROXY Register
              46. 14.2.1.1.1.2.46  MAIN_CTRL_MMR_CFG0_DEVICE_FEATURE0_PROXY Register
              47. 14.2.1.1.1.2.47  MAIN_CTRL_MMR_CFG0_DEVICE_FEATURE2_PROXY Register
              48. 14.2.1.1.1.2.48  MAIN_CTRL_MMR_CFG0_DEVICE_FEATURE6_PROXY Register
              49. 14.2.1.1.1.2.49  MAIN_CTRL_MMR_CFG0_MAC_ID0_PROXY Register
              50. 14.2.1.1.1.2.50  MAIN_CTRL_MMR_CFG0_MAC_ID1_PROXY Register
              51. 14.2.1.1.1.2.51  MAIN_CTRL_MMR_CFG0_PCI_DEVICE_ID0_PROXY Register
              52. 14.2.1.1.1.2.52  MAIN_CTRL_MMR_CFG0_PCI_DEVICE_ID1_PROXY Register
              53. 14.2.1.1.1.2.53  MAIN_CTRL_MMR_CFG0_USB_DEVICE_ID0_PROXY Register
              54. 14.2.1.1.1.2.54  MAIN_CTRL_MMR_CFG0_GP_SW0_PROXY Register
              55. 14.2.1.1.1.2.55  MAIN_CTRL_MMR_CFG0_GP_SW1_PROXY Register
              56. 14.2.1.1.1.2.56  MAIN_CTRL_MMR_CFG0_GP_SW2_PROXY Register
              57. 14.2.1.1.1.2.57  MAIN_CTRL_MMR_CFG0_GP_SW3_PROXY Register
              58. 14.2.1.1.1.2.58  MAIN_CTRL_MMR_CFG0_CBA_ERR_STAT_PROXY Register
              59. 14.2.1.1.1.2.59  MAIN_CTRL_MMR_CFG0_LOCK0_KICK0_PROXY Register
              60. 14.2.1.1.1.2.60  MAIN_CTRL_MMR_CFG0_LOCK0_KICK1_PROXY Register
              61. 14.2.1.1.1.2.61  MAIN_CTRL_MMR_CFG0_INTR_RAW_STATUS_PROXY Register
              62. 14.2.1.1.1.2.62  MAIN_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR_PROXY Register
              63. 14.2.1.1.1.2.63  MAIN_CTRL_MMR_CFG0_INTR_ENABLE_PROXY Register
              64. 14.2.1.1.1.2.64  MAIN_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR_PROXY Register
              65. 14.2.1.1.1.2.65  MAIN_CTRL_MMR_CFG0_EOI_PROXY Register
              66. 14.2.1.1.1.2.66  MAIN_CTRL_MMR_CFG0_FAULT_ADDRESS_PROXY Register
              67. 14.2.1.1.1.2.67  MAIN_CTRL_MMR_CFG0_FAULT_TYPE_STATUS_PROXY Register
              68. 14.2.1.1.1.2.68  MAIN_CTRL_MMR_CFG0_FAULT_ATTR_STATUS_PROXY Register
              69. 14.2.1.1.1.2.69  MAIN_CTRL_MMR_CFG0_FAULT_CLEAR_PROXY Register
              70. 14.2.1.1.1.2.70  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R0 Register
              71. 14.2.1.1.1.2.71  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R1 Register
              72. 14.2.1.1.1.2.72  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R2 Register
              73. 14.2.1.1.1.2.73  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R3 Register
              74. 14.2.1.1.1.2.74  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R4 Register
              75. 14.2.1.1.1.2.75  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R5 Register
              76. 14.2.1.1.1.2.76  MAIN_CTRL_MMR_CFG0_CLAIMREG_P0_R6 Register
              77. 14.2.1.1.1.2.77  MAIN_CTRL_MMR_CFG0_USB0_PHY_CTRL Register
              78. 14.2.1.1.1.2.78  MAIN_CTRL_MMR_CFG0_ENET1_CTRL Register
              79. 14.2.1.1.1.2.79  MAIN_CTRL_MMR_CFG0_ENET2_CTRL Register
              80. 14.2.1.1.1.2.80  MAIN_CTRL_MMR_CFG0_PCIE0_CTRL Register
              81. 14.2.1.1.1.2.81  MAIN_CTRL_MMR_CFG0_SERDES0_LN0_CTRL Register
              82. 14.2.1.1.1.2.82  MAIN_CTRL_MMR_CFG0_ADC0_TRIM Register
              83. 14.2.1.1.1.2.83  MAIN_CTRL_MMR_CFG0_SERDES0_CTRL Register
              84. 14.2.1.1.1.2.84  MAIN_CTRL_MMR_CFG0_ICSSG0_CTRL0 Register
              85. 14.2.1.1.1.2.85  MAIN_CTRL_MMR_CFG0_ICSSG0_CTRL1 Register
              86. 14.2.1.1.1.2.86  MAIN_CTRL_MMR_CFG0_ICSSG1_CTRL0 Register
              87. 14.2.1.1.1.2.87  MAIN_CTRL_MMR_CFG0_ICSSG1_CTRL1 Register
              88. 14.2.1.1.1.2.88  MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN Register
              89. 14.2.1.1.1.2.89  MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN_SET Register
              90. 14.2.1.1.1.2.90  MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN_CLR Register
              91. 14.2.1.1.1.2.91  MAIN_CTRL_MMR_CFG0_EPWM0_CTRL Register
              92. 14.2.1.1.1.2.92  MAIN_CTRL_MMR_CFG0_EPWM1_CTRL Register
              93. 14.2.1.1.1.2.93  MAIN_CTRL_MMR_CFG0_EPWM2_CTRL Register
              94. 14.2.1.1.1.2.94  MAIN_CTRL_MMR_CFG0_EPWM3_CTRL Register
              95. 14.2.1.1.1.2.95  MAIN_CTRL_MMR_CFG0_EPWM4_CTRL Register
              96. 14.2.1.1.1.2.96  MAIN_CTRL_MMR_CFG0_EPWM5_CTRL Register
              97. 14.2.1.1.1.2.97  MAIN_CTRL_MMR_CFG0_EPWM6_CTRL Register
              98. 14.2.1.1.1.2.98  MAIN_CTRL_MMR_CFG0_EPWM7_CTRL Register
              99. 14.2.1.1.1.2.99  MAIN_CTRL_MMR_CFG0_EPWM8_CTRL Register
              100. 14.2.1.1.1.2.100 MAIN_CTRL_MMR_CFG0_SOCA_SEL Register
              101. 14.2.1.1.1.2.101 MAIN_CTRL_MMR_CFG0_SOCB_SEL Register
              102. 14.2.1.1.1.2.102 MAIN_CTRL_MMR_CFG0_EQEP0_CTRL Register
              103. 14.2.1.1.1.2.103 MAIN_CTRL_MMR_CFG0_EQEP1_CTRL Register
              104. 14.2.1.1.1.2.104 MAIN_CTRL_MMR_CFG0_EQEP2_CTRL Register
              105. 14.2.1.1.1.2.105 MAIN_CTRL_MMR_CFG0_EQEP_STAT Register
              106. 14.2.1.1.1.2.106 MAIN_CTRL_MMR_CFG0_SDIO1_CTRL Register
              107. 14.2.1.1.1.2.107 MAIN_CTRL_MMR_CFG0_TIMER1_CTRL Register
              108. 14.2.1.1.1.2.108 MAIN_CTRL_MMR_CFG0_TIMER3_CTRL Register
              109. 14.2.1.1.1.2.109 MAIN_CTRL_MMR_CFG0_TIMER5_CTRL Register
              110. 14.2.1.1.1.2.110 MAIN_CTRL_MMR_CFG0_TIMER7_CTRL Register
              111. 14.2.1.1.1.2.111 MAIN_CTRL_MMR_CFG0_TIMER9_CTRL Register
              112. 14.2.1.1.1.2.112 MAIN_CTRL_MMR_CFG0_TIMER11_CTRL Register
              113. 14.2.1.1.1.2.113 MAIN_CTRL_MMR_CFG0_I2C0_CTRL Register
              114. 14.2.1.1.1.2.114 MAIN_CTRL_MMR_CFG0_FSS_CTRL Register
              115. 14.2.1.1.1.2.115 MAIN_CTRL_MMR_CFG0_ADC0_CTRL Register
              116. 14.2.1.1.1.2.116 MAIN_CTRL_MMR_CFG0_DCC_STAT Register
              117. 14.2.1.1.1.2.117 MAIN_CTRL_MMR_CFG0_LOCK1_KICK0 Register
              118. 14.2.1.1.1.2.118 MAIN_CTRL_MMR_CFG0_LOCK1_KICK1 Register
              119. 14.2.1.1.1.2.119 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R0_READONLY Register
              120. 14.2.1.1.1.2.120 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R1_READONLY Register
              121. 14.2.1.1.1.2.121 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R2_READONLY Register
              122. 14.2.1.1.1.2.122 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R3_READONLY Register
              123. 14.2.1.1.1.2.123 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R4_READONLY Register
              124. 14.2.1.1.1.2.124 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R5_READONLY Register
              125. 14.2.1.1.1.2.125 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R6_READONLY Register
              126. 14.2.1.1.1.2.126 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R7_READONLY Register
              127. 14.2.1.1.1.2.127 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R8_READONLY Register
              128. 14.2.1.1.1.2.128 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R9_READONLY Register
              129. 14.2.1.1.1.2.129 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R10_READONLY Register
              130. 14.2.1.1.1.2.130 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R11_READONLY Register
              131. 14.2.1.1.1.2.131 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R12_READONLY Register
              132. 14.2.1.1.1.2.132 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R13_READONLY Register
              133. 14.2.1.1.1.2.133 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R14_READONLY Register
              134. 14.2.1.1.1.2.134 MAIN_CTRL_MMR_CFG0_USB0_PHY_CTRL_PROXY Register
              135. 14.2.1.1.1.2.135 MAIN_CTRL_MMR_CFG0_ENET1_CTRL_PROXY Register
              136. 14.2.1.1.1.2.136 MAIN_CTRL_MMR_CFG0_ENET2_CTRL_PROXY Register
              137. 14.2.1.1.1.2.137 MAIN_CTRL_MMR_CFG0_PCIE0_CTRL_PROXY Register
              138. 14.2.1.1.1.2.138 MAIN_CTRL_MMR_CFG0_SERDES0_LN0_CTRL_PROXY Register
              139. 14.2.1.1.1.2.139 MAIN_CTRL_MMR_CFG0_ADC0_TRIM_PROXY Register
              140. 14.2.1.1.1.2.140 MAIN_CTRL_MMR_CFG0_SERDES0_CTRL_PROXY Register
              141. 14.2.1.1.1.2.141 MAIN_CTRL_MMR_CFG0_ICSSG0_CTRL0_PROXY Register
              142. 14.2.1.1.1.2.142 MAIN_CTRL_MMR_CFG0_ICSSG0_CTRL1_PROXY Register
              143. 14.2.1.1.1.2.143 MAIN_CTRL_MMR_CFG0_ICSSG1_CTRL0_PROXY Register
              144. 14.2.1.1.1.2.144 MAIN_CTRL_MMR_CFG0_ICSSG1_CTRL1_PROXY Register
              145. 14.2.1.1.1.2.145 MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN_PROXY Register
              146. 14.2.1.1.1.2.146 MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN_SET_PROXY Register
              147. 14.2.1.1.1.2.147 MAIN_CTRL_MMR_CFG0_EPWM_TB_CLKEN_CLR_PROXY Register
              148. 14.2.1.1.1.2.148 MAIN_CTRL_MMR_CFG0_EPWM0_CTRL_PROXY Register
              149. 14.2.1.1.1.2.149 MAIN_CTRL_MMR_CFG0_EPWM1_CTRL_PROXY Register
              150. 14.2.1.1.1.2.150 MAIN_CTRL_MMR_CFG0_EPWM2_CTRL_PROXY Register
              151. 14.2.1.1.1.2.151 MAIN_CTRL_MMR_CFG0_EPWM3_CTRL_PROXY Register
              152. 14.2.1.1.1.2.152 MAIN_CTRL_MMR_CFG0_EPWM4_CTRL_PROXY Register
              153. 14.2.1.1.1.2.153 MAIN_CTRL_MMR_CFG0_EPWM5_CTRL_PROXY Register
              154. 14.2.1.1.1.2.154 MAIN_CTRL_MMR_CFG0_EPWM6_CTRL_PROXY Register
              155. 14.2.1.1.1.2.155 MAIN_CTRL_MMR_CFG0_EPWM7_CTRL_PROXY Register
              156. 14.2.1.1.1.2.156 MAIN_CTRL_MMR_CFG0_EPWM8_CTRL_PROXY Register
              157. 14.2.1.1.1.2.157 MAIN_CTRL_MMR_CFG0_SOCA_SEL_PROXY Register
              158. 14.2.1.1.1.2.158 MAIN_CTRL_MMR_CFG0_SOCB_SEL_PROXY Register
              159. 14.2.1.1.1.2.159 MAIN_CTRL_MMR_CFG0_EQEP0_CTRL_PROXY Register
              160. 14.2.1.1.1.2.160 MAIN_CTRL_MMR_CFG0_EQEP1_CTRL_PROXY Register
              161. 14.2.1.1.1.2.161 MAIN_CTRL_MMR_CFG0_EQEP2_CTRL_PROXY Register
              162. 14.2.1.1.1.2.162 MAIN_CTRL_MMR_CFG0_EQEP_STAT_PROXY Register
              163. 14.2.1.1.1.2.163 MAIN_CTRL_MMR_CFG0_SDIO1_CTRL_PROXY Register
              164. 14.2.1.1.1.2.164 MAIN_CTRL_MMR_CFG0_TIMER1_CTRL_PROXY Register
              165. 14.2.1.1.1.2.165 MAIN_CTRL_MMR_CFG0_TIMER3_CTRL_PROXY Register
              166. 14.2.1.1.1.2.166 MAIN_CTRL_MMR_CFG0_TIMER5_CTRL_PROXY Register
              167. 14.2.1.1.1.2.167 MAIN_CTRL_MMR_CFG0_TIMER7_CTRL_PROXY Register
              168. 14.2.1.1.1.2.168 MAIN_CTRL_MMR_CFG0_TIMER9_CTRL_PROXY Register
              169. 14.2.1.1.1.2.169 MAIN_CTRL_MMR_CFG0_TIMER11_CTRL_PROXY Register
              170. 14.2.1.1.1.2.170 MAIN_CTRL_MMR_CFG0_I2C0_CTRL_PROXY Register
              171. 14.2.1.1.1.2.171 MAIN_CTRL_MMR_CFG0_FSS_CTRL_PROXY Register
              172. 14.2.1.1.1.2.172 MAIN_CTRL_MMR_CFG0_ADC0_CTRL_PROXY Register
              173. 14.2.1.1.1.2.173 MAIN_CTRL_MMR_CFG0_DCC_STAT_PROXY Register
              174. 14.2.1.1.1.2.174 MAIN_CTRL_MMR_CFG0_LOCK1_KICK0_PROXY Register
              175. 14.2.1.1.1.2.175 MAIN_CTRL_MMR_CFG0_LOCK1_KICK1_PROXY Register
              176. 14.2.1.1.1.2.176 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R0 Register
              177. 14.2.1.1.1.2.177 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R1 Register
              178. 14.2.1.1.1.2.178 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R2 Register
              179. 14.2.1.1.1.2.179 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R3 Register
              180. 14.2.1.1.1.2.180 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R4 Register
              181. 14.2.1.1.1.2.181 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R5 Register
              182. 14.2.1.1.1.2.182 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R6 Register
              183. 14.2.1.1.1.2.183 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R7 Register
              184. 14.2.1.1.1.2.184 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R8 Register
              185. 14.2.1.1.1.2.185 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R9 Register
              186. 14.2.1.1.1.2.186 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R10 Register
              187. 14.2.1.1.1.2.187 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R11 Register
              188. 14.2.1.1.1.2.188 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R12 Register
              189. 14.2.1.1.1.2.189 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R13 Register
              190. 14.2.1.1.1.2.190 MAIN_CTRL_MMR_CFG0_CLAIMREG_P1_R14 Register
              191. 14.2.1.1.1.2.191 MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL Register
              192. 14.2.1.1.1.2.192 MAIN_CTRL_MMR_CFG0_CLKOUT_CTRL Register
              193. 14.2.1.1.1.2.193 MAIN_CTRL_MMR_CFG0_GTC_CLKSEL Register
              194. 14.2.1.1.1.2.194 MAIN_CTRL_MMR_CFG0_EFUSE_CLKSEL Register
              195. 14.2.1.1.1.2.195 MAIN_CTRL_MMR_CFG0_ICSSG0_CLKSEL Register
              196. 14.2.1.1.1.2.196 MAIN_CTRL_MMR_CFG0_ICSSG1_CLKSEL Register
              197. 14.2.1.1.1.2.197 MAIN_CTRL_MMR_CFG0_MAIN_PLL0_CLKSEL Register
              198. 14.2.1.1.1.2.198 MAIN_CTRL_MMR_CFG0_MAIN_PLL1_CLKSEL Register
              199. 14.2.1.1.1.2.199 MAIN_CTRL_MMR_CFG0_MAIN_PLL2_CLKSEL Register
              200. 14.2.1.1.1.2.200 MAIN_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL Register
              201. 14.2.1.1.1.2.201 MAIN_CTRL_MMR_CFG0_MAIN_PLL12_CLKSEL Register
              202. 14.2.1.1.1.2.202 MAIN_CTRL_MMR_CFG0_MAIN_PLL14_CLKSEL Register
              203. 14.2.1.1.1.2.203 MAIN_CTRL_MMR_CFG0_PCIE0_CLKSEL Register
              204. 14.2.1.1.1.2.204 MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL Register
              205. 14.2.1.1.1.2.205 MAIN_CTRL_MMR_CFG0_CPTS_CLKSEL Register
              206. 14.2.1.1.1.2.206 MAIN_CTRL_MMR_CFG0_EMMC0_CLKSEL Register
              207. 14.2.1.1.1.2.207 MAIN_CTRL_MMR_CFG0_EMMC1_CLKSEL Register
              208. 14.2.1.1.1.2.208 MAIN_CTRL_MMR_CFG0_GPMC_CLKSEL Register
              209. 14.2.1.1.1.2.209 MAIN_CTRL_MMR_CFG0_USB0_CLKSEL Register
              210. 14.2.1.1.1.2.210 MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL Register
              211. 14.2.1.1.1.2.211 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL Register
              212. 14.2.1.1.1.2.212 MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL Register
              213. 14.2.1.1.1.2.213 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL Register
              214. 14.2.1.1.1.2.214 MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL Register
              215. 14.2.1.1.1.2.215 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL Register
              216. 14.2.1.1.1.2.216 MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL Register
              217. 14.2.1.1.1.2.217 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL Register
              218. 14.2.1.1.1.2.218 MAIN_CTRL_MMR_CFG0_TIMER8_CLKSEL Register
              219. 14.2.1.1.1.2.219 MAIN_CTRL_MMR_CFG0_TIMER9_CLKSEL Register
              220. 14.2.1.1.1.2.220 MAIN_CTRL_MMR_CFG0_TIMER10_CLKSEL Register
              221. 14.2.1.1.1.2.221 MAIN_CTRL_MMR_CFG0_TIMER11_CLKSEL Register
              222. 14.2.1.1.1.2.222 MAIN_CTRL_MMR_CFG0_SPI0_CLKSEL Register
              223. 14.2.1.1.1.2.223 MAIN_CTRL_MMR_CFG0_SPI1_CLKSEL Register
              224. 14.2.1.1.1.2.224 MAIN_CTRL_MMR_CFG0_SPI2_CLKSEL Register
              225. 14.2.1.1.1.2.225 MAIN_CTRL_MMR_CFG0_SPI3_CLKSEL Register
              226. 14.2.1.1.1.2.226 MAIN_CTRL_MMR_CFG0_SPI4_CLKSEL Register
              227. 14.2.1.1.1.2.227 MAIN_CTRL_MMR_CFG0_USART0_CLK_CTRL Register
              228. 14.2.1.1.1.2.228 MAIN_CTRL_MMR_CFG0_USART1_CLK_CTRL Register
              229. 14.2.1.1.1.2.229 MAIN_CTRL_MMR_CFG0_USART2_CLK_CTRL Register
              230. 14.2.1.1.1.2.230 MAIN_CTRL_MMR_CFG0_USART3_CLK_CTRL Register
              231. 14.2.1.1.1.2.231 MAIN_CTRL_MMR_CFG0_USART4_CLK_CTRL Register
              232. 14.2.1.1.1.2.232 MAIN_CTRL_MMR_CFG0_USART5_CLK_CTRL Register
              233. 14.2.1.1.1.2.233 MAIN_CTRL_MMR_CFG0_USART6_CLK_CTRL Register
              234. 14.2.1.1.1.2.234 MAIN_CTRL_MMR_CFG0_USART0_CLKSEL Register
              235. 14.2.1.1.1.2.235 MAIN_CTRL_MMR_CFG0_USART1_CLKSEL Register
              236. 14.2.1.1.1.2.236 MAIN_CTRL_MMR_CFG0_USART2_CLKSEL Register
              237. 14.2.1.1.1.2.237 MAIN_CTRL_MMR_CFG0_USART3_CLKSEL Register
              238. 14.2.1.1.1.2.238 MAIN_CTRL_MMR_CFG0_USART4_CLKSEL Register
              239. 14.2.1.1.1.2.239 MAIN_CTRL_MMR_CFG0_USART5_CLKSEL Register
              240. 14.2.1.1.1.2.240 MAIN_CTRL_MMR_CFG0_USART6_CLKSEL Register
              241. 14.2.1.1.1.2.241 MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL Register
              242. 14.2.1.1.1.2.242 MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL Register
              243. 14.2.1.1.1.2.243 MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL Register
              244. 14.2.1.1.1.2.244 MAIN_CTRL_MMR_CFG0_WWD9_CLKSEL Register
              245. 14.2.1.1.1.2.245 MAIN_CTRL_MMR_CFG0_WWD10_CLKSEL Register
              246. 14.2.1.1.1.2.246 MAIN_CTRL_MMR_CFG0_WWD11_CLKSEL Register
              247. 14.2.1.1.1.2.247 MAIN_CTRL_MMR_CFG0_SERDES0_CLKSEL Register
              248. 14.2.1.1.1.2.248 MAIN_CTRL_MMR_CFG0_MCAN0_CLKSEL Register
              249. 14.2.1.1.1.2.249 MAIN_CTRL_MMR_CFG0_MCAN1_CLKSEL Register
              250. 14.2.1.1.1.2.250 MAIN_CTRL_MMR_CFG0_OSPI0_CLKSEL Register
              251. 14.2.1.1.1.2.251 MAIN_CTRL_MMR_CFG0_ADC0_CLKSEL Register
              252. 14.2.1.1.1.2.252 MAIN_CTRL_MMR_CFG0_LOCK2_KICK0 Register
              253. 14.2.1.1.1.2.253 MAIN_CTRL_MMR_CFG0_LOCK2_KICK1 Register
              254. 14.2.1.1.1.2.254 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R0_READONLY Register
              255. 14.2.1.1.1.2.255 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R1_READONLY Register
              256. 14.2.1.1.1.2.256 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R2_READONLY Register
              257. 14.2.1.1.1.2.257 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R3_READONLY Register
              258. 14.2.1.1.1.2.258 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R4_READONLY Register
              259. 14.2.1.1.1.2.259 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R5_READONLY Register
              260. 14.2.1.1.1.2.260 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R6_READONLY Register
              261. 14.2.1.1.1.2.261 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R7_READONLY Register
              262. 14.2.1.1.1.2.262 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R8_READONLY Register
              263. 14.2.1.1.1.2.263 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R9_READONLY Register
              264. 14.2.1.1.1.2.264 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R10_READONLY Register
              265. 14.2.1.1.1.2.265 MAIN_CTRL_MMR_CFG0_OBSCLK0_CTRL_PROXY Register
              266. 14.2.1.1.1.2.266 MAIN_CTRL_MMR_CFG0_CLKOUT_CTRL_PROXY Register
              267. 14.2.1.1.1.2.267 MAIN_CTRL_MMR_CFG0_GTC_CLKSEL_PROXY Register
              268. 14.2.1.1.1.2.268 MAIN_CTRL_MMR_CFG0_EFUSE_CLKSEL_PROXY Register
              269. 14.2.1.1.1.2.269 MAIN_CTRL_MMR_CFG0_ICSSG0_CLKSEL_PROXY Register
              270. 14.2.1.1.1.2.270 MAIN_CTRL_MMR_CFG0_ICSSG1_CLKSEL_PROXY Register
              271. 14.2.1.1.1.2.271 MAIN_CTRL_MMR_CFG0_MAIN_PLL0_CLKSEL_PROXY Register
              272. 14.2.1.1.1.2.272 MAIN_CTRL_MMR_CFG0_MAIN_PLL1_CLKSEL_PROXY Register
              273. 14.2.1.1.1.2.273 MAIN_CTRL_MMR_CFG0_MAIN_PLL2_CLKSEL_PROXY Register
              274. 14.2.1.1.1.2.274 MAIN_CTRL_MMR_CFG0_MAIN_PLL8_CLKSEL_PROXY Register
              275. 14.2.1.1.1.2.275 MAIN_CTRL_MMR_CFG0_MAIN_PLL12_CLKSEL_PROXY Register
              276. 14.2.1.1.1.2.276 MAIN_CTRL_MMR_CFG0_MAIN_PLL14_CLKSEL_PROXY Register
              277. 14.2.1.1.1.2.277 MAIN_CTRL_MMR_CFG0_PCIE0_CLKSEL_PROXY Register
              278. 14.2.1.1.1.2.278 MAIN_CTRL_MMR_CFG0_CPSW_CLKSEL_PROXY Register
              279. 14.2.1.1.1.2.279 MAIN_CTRL_MMR_CFG0_CPTS_CLKSEL_PROXY Register
              280. 14.2.1.1.1.2.280 MAIN_CTRL_MMR_CFG0_EMMC0_CLKSEL_PROXY Register
              281. 14.2.1.1.1.2.281 MAIN_CTRL_MMR_CFG0_EMMC1_CLKSEL_PROXY Register
              282. 14.2.1.1.1.2.282 MAIN_CTRL_MMR_CFG0_GPMC_CLKSEL_PROXY Register
              283. 14.2.1.1.1.2.283 MAIN_CTRL_MMR_CFG0_USB0_CLKSEL_PROXY Register
              284. 14.2.1.1.1.2.284 MAIN_CTRL_MMR_CFG0_TIMER0_CLKSEL_PROXY Register
              285. 14.2.1.1.1.2.285 MAIN_CTRL_MMR_CFG0_TIMER1_CLKSEL_PROXY Register
              286. 14.2.1.1.1.2.286 MAIN_CTRL_MMR_CFG0_TIMER2_CLKSEL_PROXY Register
              287. 14.2.1.1.1.2.287 MAIN_CTRL_MMR_CFG0_TIMER3_CLKSEL_PROXY Register
              288. 14.2.1.1.1.2.288 MAIN_CTRL_MMR_CFG0_TIMER4_CLKSEL_PROXY Register
              289. 14.2.1.1.1.2.289 MAIN_CTRL_MMR_CFG0_TIMER5_CLKSEL_PROXY Register
              290. 14.2.1.1.1.2.290 MAIN_CTRL_MMR_CFG0_TIMER6_CLKSEL_PROXY Register
              291. 14.2.1.1.1.2.291 MAIN_CTRL_MMR_CFG0_TIMER7_CLKSEL_PROXY Register
              292. 14.2.1.1.1.2.292 MAIN_CTRL_MMR_CFG0_TIMER8_CLKSEL_PROXY Register
              293. 14.2.1.1.1.2.293 MAIN_CTRL_MMR_CFG0_TIMER9_CLKSEL_PROXY Register
              294. 14.2.1.1.1.2.294 MAIN_CTRL_MMR_CFG0_TIMER10_CLKSEL_PROXY Register
              295. 14.2.1.1.1.2.295 MAIN_CTRL_MMR_CFG0_TIMER11_CLKSEL_PROXY Register
              296. 14.2.1.1.1.2.296 MAIN_CTRL_MMR_CFG0_SPI0_CLKSEL_PROXY Register
              297. 14.2.1.1.1.2.297 MAIN_CTRL_MMR_CFG0_SPI1_CLKSEL_PROXY Register
              298. 14.2.1.1.1.2.298 MAIN_CTRL_MMR_CFG0_SPI2_CLKSEL_PROXY Register
              299. 14.2.1.1.1.2.299 MAIN_CTRL_MMR_CFG0_SPI3_CLKSEL_PROXY Register
              300. 14.2.1.1.1.2.300 MAIN_CTRL_MMR_CFG0_SPI4_CLKSEL_PROXY Register
              301. 14.2.1.1.1.2.301 MAIN_CTRL_MMR_CFG0_USART0_CLK_CTRL_PROXY Register
              302. 14.2.1.1.1.2.302 MAIN_CTRL_MMR_CFG0_USART1_CLK_CTRL_PROXY Register
              303. 14.2.1.1.1.2.303 MAIN_CTRL_MMR_CFG0_USART2_CLK_CTRL_PROXY Register
              304. 14.2.1.1.1.2.304 MAIN_CTRL_MMR_CFG0_USART3_CLK_CTRL_PROXY Register
              305. 14.2.1.1.1.2.305 MAIN_CTRL_MMR_CFG0_USART4_CLK_CTRL_PROXY Register
              306. 14.2.1.1.1.2.306 MAIN_CTRL_MMR_CFG0_USART5_CLK_CTRL_PROXY Register
              307. 14.2.1.1.1.2.307 MAIN_CTRL_MMR_CFG0_USART6_CLK_CTRL_PROXY Register
              308. 14.2.1.1.1.2.308 MAIN_CTRL_MMR_CFG0_USART0_CLKSEL_PROXY Register
              309. 14.2.1.1.1.2.309 MAIN_CTRL_MMR_CFG0_USART1_CLKSEL_PROXY Register
              310. 14.2.1.1.1.2.310 MAIN_CTRL_MMR_CFG0_USART2_CLKSEL_PROXY Register
              311. 14.2.1.1.1.2.311 MAIN_CTRL_MMR_CFG0_USART3_CLKSEL_PROXY Register
              312. 14.2.1.1.1.2.312 MAIN_CTRL_MMR_CFG0_USART4_CLKSEL_PROXY Register
              313. 14.2.1.1.1.2.313 MAIN_CTRL_MMR_CFG0_USART5_CLKSEL_PROXY Register
              314. 14.2.1.1.1.2.314 MAIN_CTRL_MMR_CFG0_USART6_CLKSEL_PROXY Register
              315. 14.2.1.1.1.2.315 MAIN_CTRL_MMR_CFG0_WWD0_CLKSEL_PROXY Register
              316. 14.2.1.1.1.2.316 MAIN_CTRL_MMR_CFG0_WWD1_CLKSEL_PROXY Register
              317. 14.2.1.1.1.2.317 MAIN_CTRL_MMR_CFG0_WWD8_CLKSEL_PROXY Register
              318. 14.2.1.1.1.2.318 MAIN_CTRL_MMR_CFG0_WWD9_CLKSEL_PROXY Register
              319. 14.2.1.1.1.2.319 MAIN_CTRL_MMR_CFG0_WWD10_CLKSEL_PROXY Register
              320. 14.2.1.1.1.2.320 MAIN_CTRL_MMR_CFG0_WWD11_CLKSEL_PROXY Register
              321. 14.2.1.1.1.2.321 MAIN_CTRL_MMR_CFG0_SERDES0_CLKSEL_PROXY Register
              322. 14.2.1.1.1.2.322 MAIN_CTRL_MMR_CFG0_MCAN0_CLKSEL_PROXY Register
              323. 14.2.1.1.1.2.323 MAIN_CTRL_MMR_CFG0_MCAN1_CLKSEL_PROXY Register
              324. 14.2.1.1.1.2.324 MAIN_CTRL_MMR_CFG0_OSPI0_CLKSEL_PROXY Register
              325. 14.2.1.1.1.2.325 MAIN_CTRL_MMR_CFG0_ADC0_CLKSEL_PROXY Register
              326. 14.2.1.1.1.2.326 MAIN_CTRL_MMR_CFG0_LOCK2_KICK0_PROXY Register
              327. 14.2.1.1.1.2.327 MAIN_CTRL_MMR_CFG0_LOCK2_KICK1_PROXY Register
              328. 14.2.1.1.1.2.328 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R0 Register
              329. 14.2.1.1.1.2.329 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R1 Register
              330. 14.2.1.1.1.2.330 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R2 Register
              331. 14.2.1.1.1.2.331 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R3 Register
              332. 14.2.1.1.1.2.332 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R4 Register
              333. 14.2.1.1.1.2.333 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R5 Register
              334. 14.2.1.1.1.2.334 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R6 Register
              335. 14.2.1.1.1.2.335 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R7 Register
              336. 14.2.1.1.1.2.336 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R8 Register
              337. 14.2.1.1.1.2.337 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R9 Register
              338. 14.2.1.1.1.2.338 MAIN_CTRL_MMR_CFG0_CLAIMREG_P2_R10 Register
              339. 14.2.1.1.1.2.339 MAIN_CTRL_MMR_CFG0_CHAIN1_CRC_FUSE Register
              340. 14.2.1.1.1.2.340 MAIN_CTRL_MMR_CFG0_CHAIN4_CRC_FUSE Register
              341. 14.2.1.1.1.2.341 MAIN_CTRL_MMR_CFG0_CHAIN5_CRC_FUSE Register
              342. 14.2.1.1.1.2.342 MAIN_CTRL_MMR_CFG0_CHAIN6_CRC_FUSE Register
              343. 14.2.1.1.1.2.343 MAIN_CTRL_MMR_CFG0_CHAIN7_CRC_FUSE Register
              344. 14.2.1.1.1.2.344 MAIN_CTRL_MMR_CFG0_FUSE_CRC_STAT Register
              345. 14.2.1.1.1.2.345 MAIN_CTRL_MMR_CFG0_CHAIN1_CRC_CALC Register
              346. 14.2.1.1.1.2.346 MAIN_CTRL_MMR_CFG0_CHAIN4_CRC_CALC Register
              347. 14.2.1.1.1.2.347 MAIN_CTRL_MMR_CFG0_CHAIN5_CRC_CALC Register
              348. 14.2.1.1.1.2.348 MAIN_CTRL_MMR_CFG0_CHAIN6_CRC_CALC Register
              349. 14.2.1.1.1.2.349 MAIN_CTRL_MMR_CFG0_CHAIN7_CRC_CALC Register
              350. 14.2.1.1.1.2.350 MAIN_CTRL_MMR_CFG0_PBIST_EN Register
              351. 14.2.1.1.1.2.351 MAIN_CTRL_MMR_CFG0_LOCK3_KICK0 Register
              352. 14.2.1.1.1.2.352 MAIN_CTRL_MMR_CFG0_LOCK3_KICK1 Register
              353. 14.2.1.1.1.2.353 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R0_READONLY Register
              354. 14.2.1.1.1.2.354 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R1_READONLY Register
              355. 14.2.1.1.1.2.355 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R2_READONLY Register
              356. 14.2.1.1.1.2.356 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R3_READONLY Register
              357. 14.2.1.1.1.2.357 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R4_READONLY Register
              358. 14.2.1.1.1.2.358 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R5_READONLY Register
              359. 14.2.1.1.1.2.359 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R6_READONLY Register
              360. 14.2.1.1.1.2.360 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R7_READONLY Register
              361. 14.2.1.1.1.2.361 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R8_READONLY Register
              362. 14.2.1.1.1.2.362 MAIN_CTRL_MMR_CFG0_CHAIN1_CRC_FUSE_PROXY Register
              363. 14.2.1.1.1.2.363 MAIN_CTRL_MMR_CFG0_CHAIN4_CRC_FUSE_PROXY Register
              364. 14.2.1.1.1.2.364 MAIN_CTRL_MMR_CFG0_CHAIN5_CRC_FUSE_PROXY Register
              365. 14.2.1.1.1.2.365 MAIN_CTRL_MMR_CFG0_CHAIN6_CRC_FUSE_PROXY Register
              366. 14.2.1.1.1.2.366 MAIN_CTRL_MMR_CFG0_CHAIN7_CRC_FUSE_PROXY Register
              367. 14.2.1.1.1.2.367 MAIN_CTRL_MMR_CFG0_FUSE_CRC_STAT_PROXY Register
              368. 14.2.1.1.1.2.368 MAIN_CTRL_MMR_CFG0_CHAIN1_CRC_CALC_PROXY Register
              369. 14.2.1.1.1.2.369 MAIN_CTRL_MMR_CFG0_CHAIN4_CRC_CALC_PROXY Register
              370. 14.2.1.1.1.2.370 MAIN_CTRL_MMR_CFG0_CHAIN5_CRC_CALC_PROXY Register
              371. 14.2.1.1.1.2.371 MAIN_CTRL_MMR_CFG0_CHAIN6_CRC_CALC_PROXY Register
              372. 14.2.1.1.1.2.372 MAIN_CTRL_MMR_CFG0_CHAIN7_CRC_CALC_PROXY Register
              373. 14.2.1.1.1.2.373 MAIN_CTRL_MMR_CFG0_PBIST_EN_PROXY Register
              374. 14.2.1.1.1.2.374 MAIN_CTRL_MMR_CFG0_LOCK3_KICK0_PROXY Register
              375. 14.2.1.1.1.2.375 MAIN_CTRL_MMR_CFG0_LOCK3_KICK1_PROXY Register
              376. 14.2.1.1.1.2.376 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R0 Register
              377. 14.2.1.1.1.2.377 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R1 Register
              378. 14.2.1.1.1.2.378 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R2 Register
              379. 14.2.1.1.1.2.379 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R3 Register
              380. 14.2.1.1.1.2.380 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R4 Register
              381. 14.2.1.1.1.2.381 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R5 Register
              382. 14.2.1.1.1.2.382 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R6 Register
              383. 14.2.1.1.1.2.383 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R7 Register
              384. 14.2.1.1.1.2.384 MAIN_CTRL_MMR_CFG0_CLAIMREG_P3_R8 Register
              385. 14.2.1.1.1.2.385 MAIN_CTRL_MMR_CFG0_LOCK4_KICK0 Register
              386. 14.2.1.1.1.2.386 MAIN_CTRL_MMR_CFG0_LOCK4_KICK1 Register
              387. 14.2.1.1.1.2.387 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R0_READONLY Register
              388. 14.2.1.1.1.2.388 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R1_READONLY Register
              389. 14.2.1.1.1.2.389 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R2_READONLY Register
              390. 14.2.1.1.1.2.390 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R3_READONLY Register
              391. 14.2.1.1.1.2.391 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R4_READONLY Register
              392. 14.2.1.1.1.2.392 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R5_READONLY Register
              393. 14.2.1.1.1.2.393 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R6_READONLY Register
              394. 14.2.1.1.1.2.394 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R7_READONLY Register
              395. 14.2.1.1.1.2.395 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R8_READONLY Register
              396. 14.2.1.1.1.2.396 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R9_READONLY Register
              397. 14.2.1.1.1.2.397 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R10_READONLY Register
              398. 14.2.1.1.1.2.398 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R11_READONLY Register
              399. 14.2.1.1.1.2.399 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R12_READONLY Register
              400. 14.2.1.1.1.2.400 MAIN_CTRL_MMR_CFG0_LOCK4_KICK0_PROXY Register
              401. 14.2.1.1.1.2.401 MAIN_CTRL_MMR_CFG0_LOCK4_KICK1_PROXY Register
              402. 14.2.1.1.1.2.402 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R0 Register
              403. 14.2.1.1.1.2.403 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R1 Register
              404. 14.2.1.1.1.2.404 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R2 Register
              405. 14.2.1.1.1.2.405 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R3 Register
              406. 14.2.1.1.1.2.406 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R4 Register
              407. 14.2.1.1.1.2.407 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R5 Register
              408. 14.2.1.1.1.2.408 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R6 Register
              409. 14.2.1.1.1.2.409 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R7 Register
              410. 14.2.1.1.1.2.410 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R8 Register
              411. 14.2.1.1.1.2.411 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R9 Register
              412. 14.2.1.1.1.2.412 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R10 Register
              413. 14.2.1.1.1.2.413 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R11 Register
              414. 14.2.1.1.1.2.414 MAIN_CTRL_MMR_CFG0_CLAIMREG_P4_R12 Register
              415. 14.2.1.1.1.2.415 MAIN_CTRL_MMR_CFG0_CHNG_DDR4_FSP_REQ Register
              416. 14.2.1.1.1.2.416 MAIN_CTRL_MMR_CFG0_CHNG_DDR4_FSP_ACK Register
              417. 14.2.1.1.1.2.417 MAIN_CTRL_MMR_CFG0_DDR4_FSP_CLKCHNG_REQ Register
              418. 14.2.1.1.1.2.418 MAIN_CTRL_MMR_CFG0_DDR4_FSP_CLKCHNG_ACK Register
              419. 14.2.1.1.1.2.419 MAIN_CTRL_MMR_CFG0_LOCK5_KICK0 Register
              420. 14.2.1.1.1.2.420 MAIN_CTRL_MMR_CFG0_LOCK5_KICK1 Register
              421. 14.2.1.1.1.2.421 MAIN_CTRL_MMR_CFG0_CLAIMREG_P5_R0_READONLY Register
              422. 14.2.1.1.1.2.422 MAIN_CTRL_MMR_CFG0_CLAIMREG_P5_R1_READONLY Register
              423. 14.2.1.1.1.2.423 MAIN_CTRL_MMR_CFG0_CHNG_DDR4_FSP_REQ_PROXY Register
              424. 14.2.1.1.1.2.424 MAIN_CTRL_MMR_CFG0_CHNG_DDR4_FSP_ACK_PROXY Register
              425. 14.2.1.1.1.2.425 MAIN_CTRL_MMR_CFG0_DDR4_FSP_CLKCHNG_REQ_PROXY Register
              426. 14.2.1.1.1.2.426 MAIN_CTRL_MMR_CFG0_DDR4_FSP_CLKCHNG_ACK_PROXY Register
              427. 14.2.1.1.1.2.427 MAIN_CTRL_MMR_CFG0_LOCK5_KICK0_PROXY Register
              428. 14.2.1.1.1.2.428 MAIN_CTRL_MMR_CFG0_LOCK5_KICK1_PROXY Register
              429. 14.2.1.1.1.2.429 MAIN_CTRL_MMR_CFG0_CLAIMREG_P5_R0 Register
              430. 14.2.1.1.1.2.430 MAIN_CTRL_MMR_CFG0_CLAIMREG_P5_R1 Register
              431. 14.2.1.1.1.2.431 MAIN_CTRL_MMR_CFG0_RST_CTRL Register
              432. 14.2.1.1.1.2.432 MAIN_CTRL_MMR_CFG0_RST_STAT Register
              433. 14.2.1.1.1.2.433 MAIN_CTRL_MMR_CFG0_RST_SRC Register
              434. 14.2.1.1.1.2.434 MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD Register
              435. 14.2.1.1.1.2.435 MAIN_CTRL_MMR_CFG0_LOCK6_KICK0 Register
              436. 14.2.1.1.1.2.436 MAIN_CTRL_MMR_CFG0_LOCK6_KICK1 Register
              437. 14.2.1.1.1.2.437 MAIN_CTRL_MMR_CFG0_CLAIMREG_P6_R0_READONLY Register
              438. 14.2.1.1.1.2.438 MAIN_CTRL_MMR_CFG0_CLAIMREG_P6_R1_READONLY Register
              439. 14.2.1.1.1.2.439 MAIN_CTRL_MMR_CFG0_CLAIMREG_P6_R2_READONLY Register
              440. 14.2.1.1.1.2.440 MAIN_CTRL_MMR_CFG0_RST_CTRL_PROXY Register
              441. 14.2.1.1.1.2.441 MAIN_CTRL_MMR_CFG0_RST_STAT_PROXY Register
              442. 14.2.1.1.1.2.442 MAIN_CTRL_MMR_CFG0_RST_SRC_PROXY Register
              443. 14.2.1.1.1.2.443 MAIN_CTRL_MMR_CFG0_RST_MAGIC_WORD_PROXY Register
              444. 14.2.1.1.1.2.444 MAIN_CTRL_MMR_CFG0_LOCK6_KICK0_PROXY Register
              445. 14.2.1.1.1.2.445 MAIN_CTRL_MMR_CFG0_LOCK6_KICK1_PROXY Register
              446. 14.2.1.1.1.2.446 MAIN_CTRL_MMR_CFG0_CLAIMREG_P6_R0 Register
              447. 14.2.1.1.1.2.447 MAIN_CTRL_MMR_CFG0_CLAIMREG_P6_R1 Register
              448. 14.2.1.1.1.2.448 MAIN_CTRL_MMR_CFG0_CLAIMREG_P6_R2 Register
          2. 14.2.1.1.2 mcu_ctrl_mmr
            1. 14.2.1.1.2.1 mcu_ctrl_mmr Summaries
              1.          4698
            2. 14.2.1.1.2.2 mcu_ctrl_mmr Registers
              1. 14.2.1.1.2.2.1   MCU_CTRL_MMR_CFG0_PID Register
              2. 14.2.1.1.2.2.2   MCU_CTRL_MMR_CFG0_MMR_CFG1 Register
              3. 14.2.1.1.2.2.3   MCU_CTRL_MMR_CFG0_LOCK0_KICK0 Register
              4. 14.2.1.1.2.2.4   MCU_CTRL_MMR_CFG0_LOCK0_KICK1 Register
              5. 14.2.1.1.2.2.5   MCU_CTRL_MMR_CFG0_INTR_RAW_STATUS Register
              6. 14.2.1.1.2.2.6   MCU_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR Register
              7. 14.2.1.1.2.2.7   MCU_CTRL_MMR_CFG0_INTR_ENABLE Register
              8. 14.2.1.1.2.2.8   MCU_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR Register
              9. 14.2.1.1.2.2.9   MCU_CTRL_MMR_CFG0_EOI Register
              10. 14.2.1.1.2.2.10  MCU_CTRL_MMR_CFG0_FAULT_ADDRESS Register
              11. 14.2.1.1.2.2.11  MCU_CTRL_MMR_CFG0_FAULT_TYPE_STATUS Register
              12. 14.2.1.1.2.2.12  MCU_CTRL_MMR_CFG0_FAULT_ATTR_STATUS Register
              13. 14.2.1.1.2.2.13  MCU_CTRL_MMR_CFG0_FAULT_CLEAR Register
              14. 14.2.1.1.2.2.14  MCU_CTRL_MMR_CFG0_CLAIMREG_P0_R0_READONLY Register
              15. 14.2.1.1.2.2.15  MCU_CTRL_MMR_CFG0_PID_PROXY Register
              16. 14.2.1.1.2.2.16  MCU_CTRL_MMR_CFG0_MMR_CFG1_PROXY Register
              17. 14.2.1.1.2.2.17  MCU_CTRL_MMR_CFG0_LOCK0_KICK0_PROXY Register
              18. 14.2.1.1.2.2.18  MCU_CTRL_MMR_CFG0_LOCK0_KICK1_PROXY Register
              19. 14.2.1.1.2.2.19  MCU_CTRL_MMR_CFG0_INTR_RAW_STATUS_PROXY Register
              20. 14.2.1.1.2.2.20  MCU_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR_PROXY Register
              21. 14.2.1.1.2.2.21  MCU_CTRL_MMR_CFG0_INTR_ENABLE_PROXY Register
              22. 14.2.1.1.2.2.22  MCU_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR_PROXY Register
              23. 14.2.1.1.2.2.23  MCU_CTRL_MMR_CFG0_EOI_PROXY Register
              24. 14.2.1.1.2.2.24  MCU_CTRL_MMR_CFG0_FAULT_ADDRESS_PROXY Register
              25. 14.2.1.1.2.2.25  MCU_CTRL_MMR_CFG0_FAULT_TYPE_STATUS_PROXY Register
              26. 14.2.1.1.2.2.26  MCU_CTRL_MMR_CFG0_FAULT_ATTR_STATUS_PROXY Register
              27. 14.2.1.1.2.2.27  MCU_CTRL_MMR_CFG0_FAULT_CLEAR_PROXY Register
              28. 14.2.1.1.2.2.28  MCU_CTRL_MMR_CFG0_CLAIMREG_P0_R0 Register
              29. 14.2.1.1.2.2.29  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG1 Register
              30. 14.2.1.1.2.2.30  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG2 Register
              31. 14.2.1.1.2.2.31  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG3 Register
              32. 14.2.1.1.2.2.32  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG4 Register
              33. 14.2.1.1.2.2.33  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG5 Register
              34. 14.2.1.1.2.2.34  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG6 Register
              35. 14.2.1.1.2.2.35  MCU_CTRL_MMR_CFG0_TEMP_DIODE_TRIM Register
              36. 14.2.1.1.2.2.36  MCU_CTRL_MMR_CFG0_IO_VOLTAGE_STAT Register
              37. 14.2.1.1.2.2.37  MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL Register
              38. 14.2.1.1.2.2.38  MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL Register
              39. 14.2.1.1.2.2.39  MCU_CTRL_MMR_CFG0_MCU_I2C0_CTRL Register
              40. 14.2.1.1.2.2.40  MCU_CTRL_MMR_CFG0_MCU_MTOG_CTRL Register
              41. 14.2.1.1.2.2.41  MCU_CTRL_MMR_CFG0_LOCK1_KICK0 Register
              42. 14.2.1.1.2.2.42  MCU_CTRL_MMR_CFG0_LOCK1_KICK1 Register
              43. 14.2.1.1.2.2.43  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R0_READONLY Register
              44. 14.2.1.1.2.2.44  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R1_READONLY Register
              45. 14.2.1.1.2.2.45  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R2_READONLY Register
              46. 14.2.1.1.2.2.46  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R3_READONLY Register
              47. 14.2.1.1.2.2.47  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R4_READONLY Register
              48. 14.2.1.1.2.2.48  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R5_READONLY Register
              49. 14.2.1.1.2.2.49  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R6_READONLY Register
              50. 14.2.1.1.2.2.50  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R7_READONLY Register
              51. 14.2.1.1.2.2.51  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R8_READONLY Register
              52. 14.2.1.1.2.2.52  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R9_READONLY Register
              53. 14.2.1.1.2.2.53  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R10_READONLY Register
              54. 14.2.1.1.2.2.54  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R11_READONLY Register
              55. 14.2.1.1.2.2.55  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R12_READONLY Register
              56. 14.2.1.1.2.2.56  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG1_PROXY Register
              57. 14.2.1.1.2.2.57  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG2_PROXY Register
              58. 14.2.1.1.2.2.58  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG3_PROXY Register
              59. 14.2.1.1.2.2.59  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG4_PROXY Register
              60. 14.2.1.1.2.2.60  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG5_PROXY Register
              61. 14.2.1.1.2.2.61  MCU_CTRL_MMR_CFG0_DBOUNCE_CFG6_PROXY Register
              62. 14.2.1.1.2.2.62  MCU_CTRL_MMR_CFG0_TEMP_DIODE_TRIM_PROXY Register
              63. 14.2.1.1.2.2.63  MCU_CTRL_MMR_CFG0_IO_VOLTAGE_STAT_PROXY Register
              64. 14.2.1.1.2.2.64  MCU_CTRL_MMR_CFG0_MCU_TIMER1_CTRL_PROXY Register
              65. 14.2.1.1.2.2.65  MCU_CTRL_MMR_CFG0_MCU_TIMER3_CTRL_PROXY Register
              66. 14.2.1.1.2.2.66  MCU_CTRL_MMR_CFG0_MCU_I2C0_CTRL_PROXY Register
              67. 14.2.1.1.2.2.67  MCU_CTRL_MMR_CFG0_MCU_MTOG_CTRL_PROXY Register
              68. 14.2.1.1.2.2.68  MCU_CTRL_MMR_CFG0_LOCK1_KICK0_PROXY Register
              69. 14.2.1.1.2.2.69  MCU_CTRL_MMR_CFG0_LOCK1_KICK1_PROXY Register
              70. 14.2.1.1.2.2.70  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R0 Register
              71. 14.2.1.1.2.2.71  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R1 Register
              72. 14.2.1.1.2.2.72  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R2 Register
              73. 14.2.1.1.2.2.73  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R3 Register
              74. 14.2.1.1.2.2.74  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R4 Register
              75. 14.2.1.1.2.2.75  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R5 Register
              76. 14.2.1.1.2.2.76  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R6 Register
              77. 14.2.1.1.2.2.77  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R7 Register
              78. 14.2.1.1.2.2.78  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R8 Register
              79. 14.2.1.1.2.2.79  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R9 Register
              80. 14.2.1.1.2.2.80  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R10 Register
              81. 14.2.1.1.2.2.81  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R11 Register
              82. 14.2.1.1.2.2.82  MCU_CTRL_MMR_CFG0_CLAIMREG_P1_R12 Register
              83. 14.2.1.1.2.2.83  MCU_CTRL_MMR_CFG0_MCU_OBSCLK_CTRL Register
              84. 14.2.1.1.2.2.84  MCU_CTRL_MMR_CFG0_HFOSC0_CTRL Register
              85. 14.2.1.1.2.2.85  MCU_CTRL_MMR_CFG0_HFOSC0_TRIM Register
              86. 14.2.1.1.2.2.86  MCU_CTRL_MMR_CFG0_RC12M_OSC_TRIM Register
              87. 14.2.1.1.2.2.87  MCU_CTRL_MMR_CFG0_HFOSC0_CLKOUT_32K_CTRL Register
              88. 14.2.1.1.2.2.88  MCU_CTRL_MMR_CFG0_MCU_M4FSS_CLKSEL Register
              89. 14.2.1.1.2.2.89  MCU_CTRL_MMR_CFG0_MCU_M4FSS_SYSTICK Register
              90. 14.2.1.1.2.2.90  MCU_CTRL_MMR_CFG0_MCU_PLL_CLKSEL Register
              91. 14.2.1.1.2.2.91  MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL Register
              92. 14.2.1.1.2.2.92  MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL Register
              93. 14.2.1.1.2.2.93  MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL Register
              94. 14.2.1.1.2.2.94  MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL Register
              95. 14.2.1.1.2.2.95  MCU_CTRL_MMR_CFG0_MCU_SPI0_CLKSEL Register
              96. 14.2.1.1.2.2.96  MCU_CTRL_MMR_CFG0_MCU_SPI1_CLKSEL Register
              97. 14.2.1.1.2.2.97  MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL Register
              98. 14.2.1.1.2.2.98  MCU_CTRL_MMR_CFG0_DDR16SS_PMCTRL Register
              99. 14.2.1.1.2.2.99  MCU_CTRL_MMR_CFG0_LOCK2_KICK0 Register
              100. 14.2.1.1.2.2.100 MCU_CTRL_MMR_CFG0_LOCK2_KICK1 Register
              101. 14.2.1.1.2.2.101 MCU_CTRL_MMR_CFG0_CLAIMREG_P2_R0_READONLY Register
              102. 14.2.1.1.2.2.102 MCU_CTRL_MMR_CFG0_CLAIMREG_P2_R1_READONLY Register
              103. 14.2.1.1.2.2.103 MCU_CTRL_MMR_CFG0_MCU_OBSCLK_CTRL_PROXY Register
              104. 14.2.1.1.2.2.104 MCU_CTRL_MMR_CFG0_HFOSC0_CTRL_PROXY Register
              105. 14.2.1.1.2.2.105 MCU_CTRL_MMR_CFG0_HFOSC0_TRIM_PROXY Register
              106. 14.2.1.1.2.2.106 MCU_CTRL_MMR_CFG0_RC12M_OSC_TRIM_PROXY Register
              107. 14.2.1.1.2.2.107 MCU_CTRL_MMR_CFG0_HFOSC0_CLKOUT_32K_CTRL_PROXY Register
              108. 14.2.1.1.2.2.108 MCU_CTRL_MMR_CFG0_MCU_M4FSS_CLKSEL_PROXY Register
              109. 14.2.1.1.2.2.109 MCU_CTRL_MMR_CFG0_MCU_M4FSS_SYSTICK_PROXY Register
              110. 14.2.1.1.2.2.110 MCU_CTRL_MMR_CFG0_MCU_PLL_CLKSEL_PROXY Register
              111. 14.2.1.1.2.2.111 MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL_PROXY Register
              112. 14.2.1.1.2.2.112 MCU_CTRL_MMR_CFG0_MCU_TIMER1_CLKSEL_PROXY Register
              113. 14.2.1.1.2.2.113 MCU_CTRL_MMR_CFG0_MCU_TIMER2_CLKSEL_PROXY Register
              114. 14.2.1.1.2.2.114 MCU_CTRL_MMR_CFG0_MCU_TIMER3_CLKSEL_PROXY Register
              115. 14.2.1.1.2.2.115 MCU_CTRL_MMR_CFG0_MCU_SPI0_CLKSEL_PROXY Register
              116. 14.2.1.1.2.2.116 MCU_CTRL_MMR_CFG0_MCU_SPI1_CLKSEL_PROXY Register
              117. 14.2.1.1.2.2.117 MCU_CTRL_MMR_CFG0_MCU_WWD0_CLKSEL_PROXY Register
              118. 14.2.1.1.2.2.118 MCU_CTRL_MMR_CFG0_DDR16SS_PMCTRL_PROXY Register
              119. 14.2.1.1.2.2.119 MCU_CTRL_MMR_CFG0_LOCK2_KICK0_PROXY Register
              120. 14.2.1.1.2.2.120 MCU_CTRL_MMR_CFG0_LOCK2_KICK1_PROXY Register
              121. 14.2.1.1.2.2.121 MCU_CTRL_MMR_CFG0_CLAIMREG_P2_R0 Register
              122. 14.2.1.1.2.2.122 MCU_CTRL_MMR_CFG0_CLAIMREG_P2_R1 Register
              123. 14.2.1.1.2.2.123 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_CTRL Register
              124. 14.2.1.1.2.2.124 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_PATCOUNT Register
              125. 14.2.1.1.2.2.125 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_SEED0 Register
              126. 14.2.1.1.2.2.126 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_SEED1 Register
              127. 14.2.1.1.2.2.127 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_SPARE0 Register
              128. 14.2.1.1.2.2.128 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_SPARE1 Register
              129. 14.2.1.1.2.2.129 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_STAT Register
              130. 14.2.1.1.2.2.130 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_MISR Register
              131. 14.2.1.1.2.2.131 MCU_CTRL_MMR_CFG0_LOCK3_KICK0 Register
              132. 14.2.1.1.2.2.132 MCU_CTRL_MMR_CFG0_LOCK3_KICK1 Register
              133. 14.2.1.1.2.2.133 MCU_CTRL_MMR_CFG0_CLAIMREG_P3_R0_READONLY Register
              134. 14.2.1.1.2.2.134 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_CTRL_PROXY Register
              135. 14.2.1.1.2.2.135 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_PATCOUNT_PROXY Register
              136. 14.2.1.1.2.2.136 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_SEED0_PROXY Register
              137. 14.2.1.1.2.2.137 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_SEED1_PROXY Register
              138. 14.2.1.1.2.2.138 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_SPARE0_PROXY Register
              139. 14.2.1.1.2.2.139 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_SPARE1_PROXY Register
              140. 14.2.1.1.2.2.140 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_STAT_PROXY Register
              141. 14.2.1.1.2.2.141 MCU_CTRL_MMR_CFG0_MCU_M4FSS0_LBIST_MISR_PROXY Register
              142. 14.2.1.1.2.2.142 MCU_CTRL_MMR_CFG0_LOCK3_KICK0_PROXY Register
              143. 14.2.1.1.2.2.143 MCU_CTRL_MMR_CFG0_LOCK3_KICK1_PROXY Register
              144. 14.2.1.1.2.2.144 MCU_CTRL_MMR_CFG0_CLAIMREG_P3_R0 Register
              145. 14.2.1.1.2.2.145 MCU_CTRL_MMR_CFG0_LOCK4_KICK0 Register
              146. 14.2.1.1.2.2.146 MCU_CTRL_MMR_CFG0_LOCK4_KICK1 Register
              147. 14.2.1.1.2.2.147 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R0_READONLY Register
              148. 14.2.1.1.2.2.148 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R1_READONLY Register
              149. 14.2.1.1.2.2.149 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R2_READONLY Register
              150. 14.2.1.1.2.2.150 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R3_READONLY Register
              151. 14.2.1.1.2.2.151 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R4_READONLY Register
              152. 14.2.1.1.2.2.152 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R5_READONLY Register
              153. 14.2.1.1.2.2.153 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R6_READONLY Register
              154. 14.2.1.1.2.2.154 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R7_READONLY Register
              155. 14.2.1.1.2.2.155 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R8_READONLY Register
              156. 14.2.1.1.2.2.156 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R9_READONLY Register
              157. 14.2.1.1.2.2.157 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R10_READONLY Register
              158. 14.2.1.1.2.2.158 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R11_READONLY Register
              159. 14.2.1.1.2.2.159 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R12_READONLY Register
              160. 14.2.1.1.2.2.160 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R13_READONLY Register
              161. 14.2.1.1.2.2.161 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R14_READONLY Register
              162. 14.2.1.1.2.2.162 MCU_CTRL_MMR_CFG0_LOCK4_KICK0_PROXY Register
              163. 14.2.1.1.2.2.163 MCU_CTRL_MMR_CFG0_LOCK4_KICK1_PROXY Register
              164. 14.2.1.1.2.2.164 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R0 Register
              165. 14.2.1.1.2.2.165 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R1 Register
              166. 14.2.1.1.2.2.166 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R2 Register
              167. 14.2.1.1.2.2.167 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R3 Register
              168. 14.2.1.1.2.2.168 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R4 Register
              169. 14.2.1.1.2.2.169 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R5 Register
              170. 14.2.1.1.2.2.170 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R6 Register
              171. 14.2.1.1.2.2.171 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R7 Register
              172. 14.2.1.1.2.2.172 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R8 Register
              173. 14.2.1.1.2.2.173 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R9 Register
              174. 14.2.1.1.2.2.174 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R10 Register
              175. 14.2.1.1.2.2.175 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R11 Register
              176. 14.2.1.1.2.2.176 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R12 Register
              177. 14.2.1.1.2.2.177 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R13 Register
              178. 14.2.1.1.2.2.178 MCU_CTRL_MMR_CFG0_CLAIMREG_P4_R14 Register
              179. 14.2.1.1.2.2.179 MCU_CTRL_MMR_CFG0_POR_CTRL Register
              180. 14.2.1.1.2.2.180 MCU_CTRL_MMR_CFG0_POR_STAT Register
              181. 14.2.1.1.2.2.181 MCU_CTRL_MMR_CFG0_POR_BANDGAP_CTRL Register
              182. 14.2.1.1.2.2.182 MCU_CTRL_MMR_CFG0_POK_VDDA_MCU_UV_CTRL Register
              183. 14.2.1.1.2.2.183 MCU_CTRL_MMR_CFG0_POK_VDDA_MCU_OV_CTRL Register
              184. 14.2.1.1.2.2.184 MCU_CTRL_MMR_CFG0_POK_VDD_CORE_UV_CTRL Register
              185. 14.2.1.1.2.2.185 MCU_CTRL_MMR_CFG0_POK_VDD_CORE_OV_CTRL Register
              186. 14.2.1.1.2.2.186 MCU_CTRL_MMR_CFG0_POK_VDDR_CORE_UV_CTRL Register
              187. 14.2.1.1.2.2.187 MCU_CTRL_MMR_CFG0_POK_VDDR_CORE_OV_CTRL Register
              188. 14.2.1.1.2.2.188 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MCU_1P8_UV_CTRL Register
              189. 14.2.1.1.2.2.189 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MCU_1P8_OV_CTRL Register
              190. 14.2.1.1.2.2.190 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MCU_3P3_UV_CTRL Register
              191. 14.2.1.1.2.2.191 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MCU_3P3_OV_CTRL Register
              192. 14.2.1.1.2.2.192 MCU_CTRL_MMR_CFG0_POK_VMON_CAP_MCU_GENERAL_UV_CTRL Register
              193. 14.2.1.1.2.2.193 MCU_CTRL_MMR_CFG0_POK_VMON_CAP_MCU_GENERAL_OV_CTRL Register
              194. 14.2.1.1.2.2.194 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MAIN_1P8_UV_CTRL Register
              195. 14.2.1.1.2.2.195 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MAIN_1P8_OV_CTRL Register
              196. 14.2.1.1.2.2.196 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MAIN_3P3_UV_CTRL Register
              197. 14.2.1.1.2.2.197 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MAIN_3P3_OV_CTRL Register
              198. 14.2.1.1.2.2.198 MCU_CTRL_MMR_CFG0_POK_VDDS_DDRIO_UV_CTRL Register
              199. 14.2.1.1.2.2.199 MCU_CTRL_MMR_CFG0_POK_VDDS_DDRIO_OV_CTRL Register
              200. 14.2.1.1.2.2.200 MCU_CTRL_MMR_CFG0_POK_VDDA_PMIC_IN_CTRL Register
              201. 14.2.1.1.2.2.201 MCU_CTRL_MMR_CFG0_RST_CTRL Register
              202. 14.2.1.1.2.2.202 MCU_CTRL_MMR_CFG0_RST_STAT Register
              203. 14.2.1.1.2.2.203 MCU_CTRL_MMR_CFG0_RST_SRC Register
              204. 14.2.1.1.2.2.204 MCU_CTRL_MMR_CFG0_RST_MAGIC_WORD Register
              205. 14.2.1.1.2.2.205 MCU_CTRL_MMR_CFG0_ISO_CTRL Register
              206. 14.2.1.1.2.2.206 MCU_CTRL_MMR_CFG0_VDD_CORE_GLDTC_CTRL Register
              207. 14.2.1.1.2.2.207 MCU_CTRL_MMR_CFG0_VDD_CORE_GLDTC_STAT Register
              208. 14.2.1.1.2.2.208 MCU_CTRL_MMR_CFG0_PRG_PP_0_CTRL Register
              209. 14.2.1.1.2.2.209 MCU_CTRL_MMR_CFG0_PRG_PP_1_CTRL Register
              210. 14.2.1.1.2.2.210 MCU_CTRL_MMR_CFG0_MCU_CLKGATE_CTRL Register
              211. 14.2.1.1.2.2.211 MCU_CTRL_MMR_CFG0_MAIN_CLKGATE_CTRL0 Register
              212. 14.2.1.1.2.2.212 MCU_CTRL_MMR_CFG0_LOCK6_KICK0 Register
              213. 14.2.1.1.2.2.213 MCU_CTRL_MMR_CFG0_LOCK6_KICK1 Register
              214. 14.2.1.1.2.2.214 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R0_READONLY Register
              215. 14.2.1.1.2.2.215 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R1_READONLY Register
              216. 14.2.1.1.2.2.216 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R2_READONLY Register
              217. 14.2.1.1.2.2.217 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R3_READONLY Register
              218. 14.2.1.1.2.2.218 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R4_READONLY Register
              219. 14.2.1.1.2.2.219 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R5_READONLY Register
              220. 14.2.1.1.2.2.220 MCU_CTRL_MMR_CFG0_POR_CTRL_PROXY Register
              221. 14.2.1.1.2.2.221 MCU_CTRL_MMR_CFG0_POR_STAT_PROXY Register
              222. 14.2.1.1.2.2.222 MCU_CTRL_MMR_CFG0_POR_BANDGAP_CTRL_PROXY Register
              223. 14.2.1.1.2.2.223 MCU_CTRL_MMR_CFG0_POK_VDDA_MCU_UV_CTRL_PROXY Register
              224. 14.2.1.1.2.2.224 MCU_CTRL_MMR_CFG0_POK_VDDA_MCU_OV_CTRL_PROXY Register
              225. 14.2.1.1.2.2.225 MCU_CTRL_MMR_CFG0_POK_VDD_CORE_UV_CTRL_PROXY Register
              226. 14.2.1.1.2.2.226 MCU_CTRL_MMR_CFG0_POK_VDD_CORE_OV_CTRL_PROXY Register
              227. 14.2.1.1.2.2.227 MCU_CTRL_MMR_CFG0_POK_VDDR_CORE_UV_CTRL_PROXY Register
              228. 14.2.1.1.2.2.228 MCU_CTRL_MMR_CFG0_POK_VDDR_CORE_OV_CTRL_PROXY Register
              229. 14.2.1.1.2.2.229 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MCU_1P8_UV_CTRL_PROXY Register
              230. 14.2.1.1.2.2.230 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MCU_1P8_OV_CTRL_PROXY Register
              231. 14.2.1.1.2.2.231 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MCU_3P3_UV_CTRL_PROXY Register
              232. 14.2.1.1.2.2.232 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MCU_3P3_OV_CTRL_PROXY Register
              233. 14.2.1.1.2.2.233 MCU_CTRL_MMR_CFG0_POK_VMON_CAP_MCU_GENERAL_UV_CTRL_PROXY Register
              234. 14.2.1.1.2.2.234 MCU_CTRL_MMR_CFG0_POK_VMON_CAP_MCU_GENERAL_OV_CTRL_PROXY Register
              235. 14.2.1.1.2.2.235 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MAIN_1P8_UV_CTRL_PROXY Register
              236. 14.2.1.1.2.2.236 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MAIN_1P8_OV_CTRL_PROXY Register
              237. 14.2.1.1.2.2.237 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MAIN_3P3_UV_CTRL_PROXY Register
              238. 14.2.1.1.2.2.238 MCU_CTRL_MMR_CFG0_POK_VDDSHV_MAIN_3P3_OV_CTRL_PROXY Register
              239. 14.2.1.1.2.2.239 MCU_CTRL_MMR_CFG0_POK_VDDS_DDRIO_UV_CTRL_PROXY Register
              240. 14.2.1.1.2.2.240 MCU_CTRL_MMR_CFG0_POK_VDDS_DDRIO_OV_CTRL_PROXY Register
              241. 14.2.1.1.2.2.241 MCU_CTRL_MMR_CFG0_POK_VDDA_PMIC_IN_CTRL_PROXY Register
              242. 14.2.1.1.2.2.242 MCU_CTRL_MMR_CFG0_RST_CTRL_PROXY Register
              243. 14.2.1.1.2.2.243 MCU_CTRL_MMR_CFG0_RST_STAT_PROXY Register
              244. 14.2.1.1.2.2.244 MCU_CTRL_MMR_CFG0_RST_SRC_PROXY Register
              245. 14.2.1.1.2.2.245 MCU_CTRL_MMR_CFG0_RST_MAGIC_WORD_PROXY Register
              246. 14.2.1.1.2.2.246 MCU_CTRL_MMR_CFG0_ISO_CTRL_PROXY Register
              247. 14.2.1.1.2.2.247 MCU_CTRL_MMR_CFG0_VDD_CORE_GLDTC_CTRL_PROXY Register
              248. 14.2.1.1.2.2.248 MCU_CTRL_MMR_CFG0_VDD_CORE_GLDTC_STAT_PROXY Register
              249. 14.2.1.1.2.2.249 MCU_CTRL_MMR_CFG0_PRG_PP_0_CTRL_PROXY Register
              250. 14.2.1.1.2.2.250 MCU_CTRL_MMR_CFG0_PRG_PP_1_CTRL_PROXY Register
              251. 14.2.1.1.2.2.251 MCU_CTRL_MMR_CFG0_MCU_CLKGATE_CTRL_PROXY Register
              252. 14.2.1.1.2.2.252 MCU_CTRL_MMR_CFG0_MAIN_CLKGATE_CTRL0_PROXY Register
              253. 14.2.1.1.2.2.253 MCU_CTRL_MMR_CFG0_LOCK6_KICK0_PROXY Register
              254. 14.2.1.1.2.2.254 MCU_CTRL_MMR_CFG0_LOCK6_KICK1_PROXY Register
              255. 14.2.1.1.2.2.255 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R0 Register
              256. 14.2.1.1.2.2.256 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R1 Register
              257. 14.2.1.1.2.2.257 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R2 Register
              258. 14.2.1.1.2.2.258 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R3 Register
              259. 14.2.1.1.2.2.259 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R4 Register
              260. 14.2.1.1.2.2.260 MCU_CTRL_MMR_CFG0_CLAIMREG_P6_R5 Register
        2. 14.2.1.2 Pad Configuration Registers
          1. 14.2.1.2.1 Pad Configuration Register Functional Description
          2. 14.2.1.2.2 Pad Configuration PADCONFIG Registers
          3. 14.2.1.2.3 main_padcfg_ctrl_mmr
            1. 14.2.1.2.3.1 main_padcfg_ctrl_mmr Summaries
              1.          4965
            2. 14.2.1.2.3.2 main_padcfg_ctrl_mmr Registers
              1. 14.2.1.2.3.2.1  MAIN_PADCFG_CTRL_MMR_CFG0_PID Register
              2. 14.2.1.2.3.2.2  MAIN_PADCFG_CTRL_MMR_CFG0_MMR_CFG0 Register
              3. 14.2.1.2.3.2.3  MAIN_PADCFG_CTRL_MMR_CFG0_MMR_CFG1 Register
              4. 14.2.1.2.3.2.4  MAIN_PADCFG_CTRL_MMR_CFG0_LOCK0_KICK0 Register
              5. 14.2.1.2.3.2.5  MAIN_PADCFG_CTRL_MMR_CFG0_LOCK0_KICK1 Register
              6. 14.2.1.2.3.2.6  MAIN_PADCFG_CTRL_MMR_CFG0_INTR_RAW_STATUS Register
              7. 14.2.1.2.3.2.7  MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR Register
              8. 14.2.1.2.3.2.8  MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE Register
              9. 14.2.1.2.3.2.9  MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR Register
              10. 14.2.1.2.3.2.10 MAIN_PADCFG_CTRL_MMR_CFG0_EOI Register
              11. 14.2.1.2.3.2.11 MAIN_PADCFG_CTRL_MMR_CFG0_FAULT_ADDRESS Register
              12. 14.2.1.2.3.2.12 MAIN_PADCFG_CTRL_MMR_CFG0_FAULT_TYPE_STATUS Register
              13. 14.2.1.2.3.2.13 MAIN_PADCFG_CTRL_MMR_CFG0_FAULT_ATTR_STATUS Register
              14. 14.2.1.2.3.2.14 MAIN_PADCFG_CTRL_MMR_CFG0_FAULT_CLEAR Register
              15. 14.2.1.2.3.2.15 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P0_R0_READONLY Register
              16. 14.2.1.2.3.2.16 MAIN_PADCFG_CTRL_MMR_CFG0_PID_PROXY Register
              17. 14.2.1.2.3.2.17 MAIN_PADCFG_CTRL_MMR_CFG0_MMR_CFG0_PROXY Register
              18. 14.2.1.2.3.2.18 MAIN_PADCFG_CTRL_MMR_CFG0_MMR_CFG1_PROXY Register
              19. 14.2.1.2.3.2.19 MAIN_PADCFG_CTRL_MMR_CFG0_LOCK0_KICK0_PROXY Register
              20. 14.2.1.2.3.2.20 MAIN_PADCFG_CTRL_MMR_CFG0_LOCK0_KICK1_PROXY Register
              21. 14.2.1.2.3.2.21 MAIN_PADCFG_CTRL_MMR_CFG0_INTR_RAW_STATUS_PROXY Register
              22. 14.2.1.2.3.2.22 MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR_PROXY Register
              23. 14.2.1.2.3.2.23 MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_PROXY Register
              24. 14.2.1.2.3.2.24 MAIN_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR_PROXY Register
              25. 14.2.1.2.3.2.25 MAIN_PADCFG_CTRL_MMR_CFG0_EOI_PROXY Register
              26. 14.2.1.2.3.2.26 MAIN_PADCFG_CTRL_MMR_CFG0_FAULT_ADDRESS_PROXY Register
              27. 14.2.1.2.3.2.27 MAIN_PADCFG_CTRL_MMR_CFG0_FAULT_TYPE_STATUS_PROXY Register
              28. 14.2.1.2.3.2.28 MAIN_PADCFG_CTRL_MMR_CFG0_FAULT_ATTR_STATUS_PROXY Register
              29. 14.2.1.2.3.2.29 MAIN_PADCFG_CTRL_MMR_CFG0_FAULT_CLEAR_PROXY Register
              30. 14.2.1.2.3.2.30 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P0_R0 Register
              31. 14.2.1.2.3.2.31 MAIN_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK0 Register
              32. 14.2.1.2.3.2.32 MAIN_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK1 Register
              33. 14.2.1.2.3.2.33 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R0_READONLY Register
              34. 14.2.1.2.3.2.34 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R1_READONLY Register
              35. 14.2.1.2.3.2.35 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R2_READONLY Register
              36. 14.2.1.2.3.2.36 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R3_READONLY Register
              37. 14.2.1.2.3.2.37 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R4_READONLY Register
              38. 14.2.1.2.3.2.38 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R5_READONLY Register
              39. 14.2.1.2.3.2.39 MAIN_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK0_PROXY Register
              40. 14.2.1.2.3.2.40 MAIN_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK1_PROXY Register
              41. 14.2.1.2.3.2.41 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R0 Register
              42. 14.2.1.2.3.2.42 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R1 Register
              43. 14.2.1.2.3.2.43 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R2 Register
              44. 14.2.1.2.3.2.44 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R3 Register
              45. 14.2.1.2.3.2.45 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R4 Register
              46. 14.2.1.2.3.2.46 MAIN_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R5 Register
          4. 14.2.1.2.4 mcu_padcfg_ctrl_mmr
            1. 14.2.1.2.4.1 mcu_padcfg_ctrl_mmr Summaries
              1.          5015
            2. 14.2.1.2.4.2 mcu_padcfg_ctrl_mmr Registers
              1. 14.2.1.2.4.2.1  MCU_PADCFG_CTRL_MMR_CFG0_PID Register
              2. 14.2.1.2.4.2.2  MCU_PADCFG_CTRL_MMR_CFG0_MMR_CFG0 Register
              3. 14.2.1.2.4.2.3  MCU_PADCFG_CTRL_MMR_CFG0_MMR_CFG1 Register
              4. 14.2.1.2.4.2.4  MCU_PADCFG_CTRL_MMR_CFG0_LOCK0_KICK0 Register
              5. 14.2.1.2.4.2.5  MCU_PADCFG_CTRL_MMR_CFG0_LOCK0_KICK1 Register
              6. 14.2.1.2.4.2.6  MCU_PADCFG_CTRL_MMR_CFG0_INTR_RAW_STATUS Register
              7. 14.2.1.2.4.2.7  MCU_PADCFG_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR Register
              8. 14.2.1.2.4.2.8  MCU_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE Register
              9. 14.2.1.2.4.2.9  MCU_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR Register
              10. 14.2.1.2.4.2.10 MCU_PADCFG_CTRL_MMR_CFG0_EOI Register
              11. 14.2.1.2.4.2.11 MCU_PADCFG_CTRL_MMR_CFG0_FAULT_ADDRESS Register
              12. 14.2.1.2.4.2.12 MCU_PADCFG_CTRL_MMR_CFG0_FAULT_TYPE_STATUS Register
              13. 14.2.1.2.4.2.13 MCU_PADCFG_CTRL_MMR_CFG0_FAULT_ATTR_STATUS Register
              14. 14.2.1.2.4.2.14 MCU_PADCFG_CTRL_MMR_CFG0_FAULT_CLEAR Register
              15. 14.2.1.2.4.2.15 MCU_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P0_R0_READONLY Register
              16. 14.2.1.2.4.2.16 MCU_PADCFG_CTRL_MMR_CFG0_PID_PROXY Register
              17. 14.2.1.2.4.2.17 MCU_PADCFG_CTRL_MMR_CFG0_MMR_CFG0_PROXY Register
              18. 14.2.1.2.4.2.18 MCU_PADCFG_CTRL_MMR_CFG0_MMR_CFG1_PROXY Register
              19. 14.2.1.2.4.2.19 MCU_PADCFG_CTRL_MMR_CFG0_LOCK0_KICK0_PROXY Register
              20. 14.2.1.2.4.2.20 MCU_PADCFG_CTRL_MMR_CFG0_LOCK0_KICK1_PROXY Register
              21. 14.2.1.2.4.2.21 MCU_PADCFG_CTRL_MMR_CFG0_INTR_RAW_STATUS_PROXY Register
              22. 14.2.1.2.4.2.22 MCU_PADCFG_CTRL_MMR_CFG0_INTR_ENABLED_STATUS_CLEAR_PROXY Register
              23. 14.2.1.2.4.2.23 MCU_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_PROXY Register
              24. 14.2.1.2.4.2.24 MCU_PADCFG_CTRL_MMR_CFG0_INTR_ENABLE_CLEAR_PROXY Register
              25. 14.2.1.2.4.2.25 MCU_PADCFG_CTRL_MMR_CFG0_EOI_PROXY Register
              26. 14.2.1.2.4.2.26 MCU_PADCFG_CTRL_MMR_CFG0_FAULT_ADDRESS_PROXY Register
              27. 14.2.1.2.4.2.27 MCU_PADCFG_CTRL_MMR_CFG0_FAULT_TYPE_STATUS_PROXY Register
              28. 14.2.1.2.4.2.28 MCU_PADCFG_CTRL_MMR_CFG0_FAULT_ATTR_STATUS_PROXY Register
              29. 14.2.1.2.4.2.29 MCU_PADCFG_CTRL_MMR_CFG0_FAULT_CLEAR_PROXY Register
              30. 14.2.1.2.4.2.30 MCU_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P0_R0 Register
              31. 14.2.1.2.4.2.31 MCU_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK0 Register
              32. 14.2.1.2.4.2.32 MCU_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK1 Register
              33. 14.2.1.2.4.2.33 MCU_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R0_READONLY Register
              34. 14.2.1.2.4.2.34 MCU_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R1_READONLY Register
              35. 14.2.1.2.4.2.35 MCU_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK0_PROXY Register
              36. 14.2.1.2.4.2.36 MCU_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK1_PROXY Register
              37. 14.2.1.2.4.2.37 MCU_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R0 Register
              38. 14.2.1.2.4.2.38 MCU_PADCFG_CTRL_MMR_CFG0_CLAIMREG_P1_R1 Register
        3. 14.2.1.3 Kick Protection Registers
          1. 14.2.1.3.1 Kick Protection Registers
        4. 14.2.1.4 Security Control Registers
          1. 14.2.1.4.1 main_sec_mmr
            1. 14.2.1.4.1.1 main_sec_mmr Summaries
              1.          5060
              2.          5061
            2. 14.2.1.4.1.2 main_sec_mmr Registers
              1. 14.2.1.4.1.2.1  MAIN_SEC_MMR_CFG2_CLSTR0_CORE0_DBG_CFG Register
              2. 14.2.1.4.1.2.2  MAIN_SEC_MMR_CFG2_CLSTR0_CORE1_DBG_CFG Register
              3. 14.2.1.4.1.2.3  MAIN_SEC_MMR_CFG2_CLSTR1_CORE0_DBG_CFG Register
              4. 14.2.1.4.1.2.4  MAIN_SEC_MMR_CFG2_CLSTR1_CORE1_DBG_CFG Register
              5. 14.2.1.4.1.2.5  MAIN_SEC_MMR_CFG2_CLSTR9_CORE0_DBG_CFG Register
              6. 14.2.1.4.1.2.6  MAIN_SEC_MMR_CFG2_CLSTR9_CORE1_DBG_CFG Register
              7. 14.2.1.4.1.2.7  MAIN_SEC_MMR_CFG2_CLSTR16_CORE0_DBG_CFG Register
              8. 14.2.1.4.1.2.8  MAIN_SEC_MMR_CFG0_PID Register
              9. 14.2.1.4.1.2.9  MAIN_SEC_MMR_CFG0_CLSTR0_DEF Register
              10. 14.2.1.4.1.2.10 MAIN_SEC_MMR_CFG0_CLSTR0_CFG Register
              11. 14.2.1.4.1.2.11 MAIN_SEC_MMR_CFG0_CLSTR0_PMCTRL Register
              12. 14.2.1.4.1.2.12 MAIN_SEC_MMR_CFG0_CLSTR0_PMSTAT Register
              13. 14.2.1.4.1.2.13 MAIN_SEC_MMR_CFG0_CLSTR0_CORE0_CFG Register
              14. 14.2.1.4.1.2.14 MAIN_SEC_MMR_CFG0_CLSTR0_CORE0_BOOTVECT_LO Register
              15. 14.2.1.4.1.2.15 MAIN_SEC_MMR_CFG0_CLSTR0_CORE0_BOOTVECT_HI Register
              16. 14.2.1.4.1.2.16 MAIN_SEC_MMR_CFG0_CLSTR0_CORE0_PMCTRL Register
              17. 14.2.1.4.1.2.17 MAIN_SEC_MMR_CFG0_CLSTR0_CORE0_PMSTAT Register
              18. 14.2.1.4.1.2.18 MAIN_SEC_MMR_CFG0_CLSTR0_CORE1_CFG Register
              19. 14.2.1.4.1.2.19 MAIN_SEC_MMR_CFG0_CLSTR0_CORE1_BOOTVECT_LO Register
              20. 14.2.1.4.1.2.20 MAIN_SEC_MMR_CFG0_CLSTR0_CORE1_BOOTVECT_HI Register
              21. 14.2.1.4.1.2.21 MAIN_SEC_MMR_CFG0_CLSTR0_CORE1_PMCTRL Register
              22. 14.2.1.4.1.2.22 MAIN_SEC_MMR_CFG0_CLSTR0_CORE1_PMSTAT Register
              23. 14.2.1.4.1.2.23 MAIN_SEC_MMR_CFG0_CLSTR1_DEF Register
              24. 14.2.1.4.1.2.24 MAIN_SEC_MMR_CFG0_CLSTR1_CFG Register
              25. 14.2.1.4.1.2.25 MAIN_SEC_MMR_CFG0_CLSTR1_PMCTRL Register
              26. 14.2.1.4.1.2.26 MAIN_SEC_MMR_CFG0_CLSTR1_PMSTAT Register
              27. 14.2.1.4.1.2.27 MAIN_SEC_MMR_CFG0_CLSTR1_CORE0_CFG Register
              28. 14.2.1.4.1.2.28 MAIN_SEC_MMR_CFG0_CLSTR1_CORE0_BOOTVECT_LO Register
              29. 14.2.1.4.1.2.29 MAIN_SEC_MMR_CFG0_CLSTR1_CORE0_BOOTVECT_HI Register
              30. 14.2.1.4.1.2.30 MAIN_SEC_MMR_CFG0_CLSTR1_CORE0_PMCTRL Register
              31. 14.2.1.4.1.2.31 MAIN_SEC_MMR_CFG0_CLSTR1_CORE0_PMSTAT Register
              32. 14.2.1.4.1.2.32 MAIN_SEC_MMR_CFG0_CLSTR1_CORE1_CFG Register
              33. 14.2.1.4.1.2.33 MAIN_SEC_MMR_CFG0_CLSTR1_CORE1_BOOTVECT_LO Register
              34. 14.2.1.4.1.2.34 MAIN_SEC_MMR_CFG0_CLSTR1_CORE1_BOOTVECT_HI Register
              35. 14.2.1.4.1.2.35 MAIN_SEC_MMR_CFG0_CLSTR1_CORE1_PMCTRL Register
              36. 14.2.1.4.1.2.36 MAIN_SEC_MMR_CFG0_CLSTR1_CORE1_PMSTAT Register
              37. 14.2.1.4.1.2.37 MAIN_SEC_MMR_CFG0_CLSTR9_DEF Register
              38. 14.2.1.4.1.2.38 MAIN_SEC_MMR_CFG0_CLSTR9_CFG Register
              39. 14.2.1.4.1.2.39 MAIN_SEC_MMR_CFG0_CLSTR9_PMCTRL Register
              40. 14.2.1.4.1.2.40 MAIN_SEC_MMR_CFG0_CLSTR9_PMSTAT Register
              41. 14.2.1.4.1.2.41 MAIN_SEC_MMR_CFG0_CLSTR9_CORE0_BOOTVECT_LO Register
              42. 14.2.1.4.1.2.42 MAIN_SEC_MMR_CFG0_CLSTR9_CORE0_BOOTVECT_HI Register
              43. 14.2.1.4.1.2.43 MAIN_SEC_MMR_CFG0_CLSTR9_CORE1_BOOTVECT_LO Register
              44. 14.2.1.4.1.2.44 MAIN_SEC_MMR_CFG0_CLSTR9_CORE1_BOOTVECT_HI Register
              45. 14.2.1.4.1.2.45 MAIN_SEC_MMR_CFG0_CLSTR16_DEF Register
              46. 14.2.1.4.1.2.46 MAIN_SEC_MMR_CFG0_CLSTR16_CORE0_PMSTAT Register
              47. 14.2.1.4.1.2.47 MAIN_SEC_MMR_CFG0_GIC_CONFIG Register
      2. 14.2.2 Power Registers
        1. 14.2.2.1 VTM
          1. 14.2.2.1.1 VTM Summaries
            1.         5113
            2.         5114
            3.         5115
          2. 14.2.2.1.2 VTM Registers
            1. 14.2.2.1.2.1  VTM_CFG1_PID Register
            2. 14.2.2.1.2.2  VTM_CFG1_DEVINFO_PWR0 Register
            3. 14.2.2.1.2.3  VTM_CFG1_GT_TH1_INT_RAW_STAT_SET Register
            4. 14.2.2.1.2.4  VTM_CFG1_GT_TH1_INT_EN_STAT_CLR Register
            5. 14.2.2.1.2.5  VTM_CFG1_GT_TH1_INT_EN_SET Register
            6. 14.2.2.1.2.6  VTM_CFG1_GT_TH1_INT_EN_CLR Register
            7. 14.2.2.1.2.7  VTM_CFG1_GT_TH2_INT_RAW_STAT_SET Register
            8. 14.2.2.1.2.8  VTM_CFG1_GT_TH2_INT_EN_STAT_CLR Register
            9. 14.2.2.1.2.9  VTM_CFG1_GT_TH2_INT_EN_SET Register
            10. 14.2.2.1.2.10 VTM_CFG1_GT_TH2_INT_EN_CLR Register
            11. 14.2.2.1.2.11 VTM_CFG1_LT_TH0_INT_RAW_STAT_SET Register
            12. 14.2.2.1.2.12 VTM_CFG1_LT_TH0_INT_EN_STAT_CLR Register
            13. 14.2.2.1.2.13 VTM_CFG1_LT_TH0_INT_EN_SET Register
            14. 14.2.2.1.2.14 VTM_CFG1_LT_TH0_INT_EN_CLR Register
            15. 14.2.2.1.2.15 VTM_CFG1_VD_DEVINFO_j Register
            16. 14.2.2.1.2.16 VTM_CFG1_VD_OPPVID_j Register
            17. 14.2.2.1.2.17 VTM_CFG1_VD_EVT_STAT_j Register
            18. 14.2.2.1.2.18 VTM_CFG1_VD_EVT_SET_j Register
            19. 14.2.2.1.2.19 VTM_CFG1_VD_EVT_CLR_j Register
            20. 14.2.2.1.2.20 VTM_CFG1_TMPSENS_CTRL_j Register
            21. 14.2.2.1.2.21 VTM_CFG1_TMPSENS_STAT_j Register
            22. 14.2.2.1.2.22 VTM_CFG1_TMPSENS_TH_j Register
            23. 14.2.2.1.2.23 VTM_CFG1_TMPSENS_TH2_j Register
            24. 14.2.2.1.2.24 VTM_CFG2_CLK_CTRL Register
            25. 14.2.2.1.2.25 VTM_CFG2_MISC_CTRL Register
            26. 14.2.2.1.2.26 VTM_CFG2_MISC_CTRL2 Register
            27. 14.2.2.1.2.27 VTM_CFG2_SAMPLE_CTRL Register
            28. 14.2.2.1.2.28 VTM_CFG2_TMPSENS_CTRL_j Register
            29. 14.2.2.1.2.29 VTM_CFG2_TMPSENS_TRIM_j Register
            30. 14.2.2.1.2.30 ECC_AGGR_REV Register
            31. 14.2.2.1.2.31 ECC_AGGR_VECTOR Register
            32. 14.2.2.1.2.32 ECC_AGGR_STAT Register
            33. 14.2.2.1.2.33 ECC_AGGR_RESERVED_SVBUS_j Register
            34. 14.2.2.1.2.34 ECC_AGGR_SEC_EOI_REG Register
            35. 14.2.2.1.2.35 ECC_AGGR_SEC_STATUS_REG0 Register
            36. 14.2.2.1.2.36 ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            37. 14.2.2.1.2.37 ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            38. 14.2.2.1.2.38 ECC_AGGR_DED_EOI_REG Register
            39. 14.2.2.1.2.39 ECC_AGGR_DED_STATUS_REG0 Register
            40. 14.2.2.1.2.40 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            41. 14.2.2.1.2.41 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            42. 14.2.2.1.2.42 ECC_AGGR_AGGR_ENABLE_SET Register
            43. 14.2.2.1.2.43 ECC_AGGR_AGGR_ENABLE_CLR Register
            44. 14.2.2.1.2.44 ECC_AGGR_AGGR_STATUS_SET Register
            45. 14.2.2.1.2.45 ECC_AGGR_AGGR_STATUS_CLR Register
        2. 14.2.2.2 PSC
          1. 14.2.2.2.1 PSC Summaries
            1.         5164
          2. 14.2.2.2.2 PSC Registers
            1. 14.2.2.2.2.1  PSC_PID Register
            2. 14.2.2.2.2.2  PSC_GBLCTL Register
            3. 14.2.2.2.2.3  PSC_GBLSTAT Register
            4. 14.2.2.2.2.4  PSC_INTEVAL Register
            5. 14.2.2.2.2.5  PSC_MERRPR_j Register
            6. 14.2.2.2.2.6  PSC_MERRCR_j Register
            7. 14.2.2.2.2.7  PSC_PERRPR Register
            8. 14.2.2.2.2.8  PSC_PERRCR Register
            9. 14.2.2.2.2.9  PSC_EPCPR Register
            10. 14.2.2.2.2.10 PSC_EPCCR Register
            11. 14.2.2.2.2.11 PSC_RAILSTAT Register
            12. 14.2.2.2.2.12 PSC_RAILCTL Register
            13. 14.2.2.2.2.13 PSC_RAILSEL Register
            14. 14.2.2.2.2.14 PSC_PTCMD Register
            15. 14.2.2.2.2.15 PSC_PTSTAT Register
            16. 14.2.2.2.2.16 PSC_PDSTAT_j Register
            17. 14.2.2.2.2.17 PSC_PDCTL_j Register
            18. 14.2.2.2.2.18 PSC_PDCFG_j Register
            19. 14.2.2.2.2.19 PSC_MDCFG_j Register
            20. 14.2.2.2.2.20 PSC_MDSTAT_j Register
            21. 14.2.2.2.2.21 PSC_MDCTL_j Register
        3. 14.2.2.3 PSC
          1. 14.2.2.3.1 PSC Summaries
            1.         5189
          2. 14.2.2.3.2 PSC Registers
            1. 14.2.2.3.2.1  PSC_PID Register
            2. 14.2.2.3.2.2  PSC_GBLCTL Register
            3. 14.2.2.3.2.3  PSC_GBLSTAT Register
            4. 14.2.2.3.2.4  PSC_INTEVAL Register
            5. 14.2.2.3.2.5  PSC_MERRPR Register
            6. 14.2.2.3.2.6  PSC_MERRCR Register
            7. 14.2.2.3.2.7  PSC_PERRPR Register
            8. 14.2.2.3.2.8  PSC_PERRCR Register
            9. 14.2.2.3.2.9  PSC_EPCPR Register
            10. 14.2.2.3.2.10 PSC_EPCCR Register
            11. 14.2.2.3.2.11 PSC_RAILSTAT Register
            12. 14.2.2.3.2.12 PSC_RAILCTL Register
            13. 14.2.2.3.2.13 PSC_RAILSEL Register
            14. 14.2.2.3.2.14 PSC_PTCMD Register
            15. 14.2.2.3.2.15 PSC_PTSTAT Register
            16. 14.2.2.3.2.16 PSC_PDSTAT_j Register
            17. 14.2.2.3.2.17 PSC_PDCTL_j Register
            18. 14.2.2.3.2.18 PSC_PDCFG_j Register
            19. 14.2.2.3.2.19 PSC_MDCFG_j Register
            20. 14.2.2.3.2.20 PSC_MDSTAT_j Register
            21. 14.2.2.3.2.21 PSC_MDCTL_j Register
      3. 14.2.3 Clocking Registers
        1. 14.2.3.1 MAIN_PLL_MMR_CFG Registers
          1. 14.2.3.1.1 MAIN_PLL_MMR Registers
            1. 14.2.3.1.1.1   MAIN_PLL_MMR Summary Table
            2. 14.2.3.1.1.2   MAIN_PLL_MMR_CFG_PLL0_PID Register
            3. 14.2.3.1.1.3   MAIN_PLL_MMR_CFG_PLL0_CFG Register
            4. 14.2.3.1.1.4   MAIN_PLL_MMR_CFG_PLL0_LOCKKEY0 Register
            5. 14.2.3.1.1.5   MAIN_PLL_MMR_CFG_PLL0_LOCKKEY1 Register
            6. 14.2.3.1.1.6   MAIN_PLL_MMR_CFG_PLL0_CTRL Register
            7. 14.2.3.1.1.7   MAIN_PLL_MMR_CFG_PLL0_STAT Register
            8. 14.2.3.1.1.8   MAIN_PLL_MMR_CFG_PLL0_FREQ_CTRL0 Register
            9. 14.2.3.1.1.9   MAIN_PLL_MMR_CFG_PLL0_FREQ_CTRL1 Register
            10. 14.2.3.1.1.10  MAIN_PLL_MMR_CFG_PLL0_DIV_CTRL Register
            11. 14.2.3.1.1.11  MAIN_PLL_MMR_CFG_PLL0_SS_CTRL Register
            12. 14.2.3.1.1.12  MAIN_PLL_MMR_CFG_PLL0_SS_SPREAD Register
            13. 14.2.3.1.1.13  MAIN_PLL_MMR_CFG_PLL0_CAL_CTRL Register
            14. 14.2.3.1.1.14  MAIN_PLL_MMR_CFG_PLL0_CAL_STAT Register
            15. 14.2.3.1.1.15  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL0 Register
            16. 14.2.3.1.1.16  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL1 Register
            17. 14.2.3.1.1.17  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL2 Register
            18. 14.2.3.1.1.18  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL3 Register
            19. 14.2.3.1.1.19  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL4 Register
            20. 14.2.3.1.1.20  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL5 Register
            21. 14.2.3.1.1.21  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL6 Register
            22. 14.2.3.1.1.22  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL7 Register
            23. 14.2.3.1.1.23  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL8 Register
            24. 14.2.3.1.1.24  MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL9 Register
            25. 14.2.3.1.1.25  MAIN_PLL_MMR_CFG_PLL1_PID Register
            26. 14.2.3.1.1.26  MAIN_PLL_MMR_CFG_PLL1_CFG Register
            27. 14.2.3.1.1.27  MAIN_PLL_MMR_CFG_PLL1_LOCKKEY0 Register
            28. 14.2.3.1.1.28  MAIN_PLL_MMR_CFG_PLL1_LOCKKEY1 Register
            29. 14.2.3.1.1.29  MAIN_PLL_MMR_CFG_PLL1_CTRL Register
            30. 14.2.3.1.1.30  MAIN_PLL_MMR_CFG_PLL1_STAT Register
            31. 14.2.3.1.1.31  MAIN_PLL_MMR_CFG_PLL1_FREQ_CTRL0 Register
            32. 14.2.3.1.1.32  MAIN_PLL_MMR_CFG_PLL1_FREQ_CTRL1 Register
            33. 14.2.3.1.1.33  MAIN_PLL_MMR_CFG_PLL1_DIV_CTRL Register
            34. 14.2.3.1.1.34  MAIN_PLL_MMR_CFG_PLL1_SS_CTRL Register
            35. 14.2.3.1.1.35  MAIN_PLL_MMR_CFG_PLL1_SS_SPREAD Register
            36. 14.2.3.1.1.36  MAIN_PLL_MMR_CFG_PLL1_CAL_CTRL Register
            37. 14.2.3.1.1.37  MAIN_PLL_MMR_CFG_PLL1_CAL_STAT Register
            38. 14.2.3.1.1.38  MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL0 Register
            39. 14.2.3.1.1.39  MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL1 Register
            40. 14.2.3.1.1.40  MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL2 Register
            41. 14.2.3.1.1.41  MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL3 Register
            42. 14.2.3.1.1.42  MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL4 Register
            43. 14.2.3.1.1.43  MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL5 Register
            44. 14.2.3.1.1.44  MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL6 Register
            45. 14.2.3.1.1.45  MAIN_PLL_MMR_CFG_PLL2_PID Register
            46. 14.2.3.1.1.46  MAIN_PLL_MMR_CFG_PLL2_CFG Register
            47. 14.2.3.1.1.47  MAIN_PLL_MMR_CFG_PLL2_LOCKKEY0 Register
            48. 14.2.3.1.1.48  MAIN_PLL_MMR_CFG_PLL2_LOCKKEY1 Register
            49. 14.2.3.1.1.49  MAIN_PLL_MMR_CFG_PLL2_CTRL Register
            50. 14.2.3.1.1.50  MAIN_PLL_MMR_CFG_PLL2_STAT Register
            51. 14.2.3.1.1.51  MAIN_PLL_MMR_CFG_PLL2_FREQ_CTRL0 Register
            52. 14.2.3.1.1.52  MAIN_PLL_MMR_CFG_PLL2_FREQ_CTRL1 Register
            53. 14.2.3.1.1.53  MAIN_PLL_MMR_CFG_PLL2_DIV_CTRL Register
            54. 14.2.3.1.1.54  MAIN_PLL_MMR_CFG_PLL2_SS_CTRL Register
            55. 14.2.3.1.1.55  MAIN_PLL_MMR_CFG_PLL2_SS_SPREAD Register
            56. 14.2.3.1.1.56  MAIN_PLL_MMR_CFG_PLL2_CAL_CTRL Register
            57. 14.2.3.1.1.57  MAIN_PLL_MMR_CFG_PLL2_CAL_STAT Register
            58. 14.2.3.1.1.58  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL0 Register
            59. 14.2.3.1.1.59  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL1 Register
            60. 14.2.3.1.1.60  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL2 Register
            61. 14.2.3.1.1.61  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL3 Register
            62. 14.2.3.1.1.62  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL4 Register
            63. 14.2.3.1.1.63  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL5 Register
            64. 14.2.3.1.1.64  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL6 Register
            65. 14.2.3.1.1.65  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL7 Register
            66. 14.2.3.1.1.66  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL8 Register
            67. 14.2.3.1.1.67  MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL9 Register
            68. 14.2.3.1.1.68  MAIN_PLL_MMR_CFG_PLL8_PID Register
            69. 14.2.3.1.1.69  MAIN_PLL_MMR_CFG_PLL8_CFG Register
            70. 14.2.3.1.1.70  MAIN_PLL_MMR_CFG_PLL8_LOCKKEY0 Register
            71. 14.2.3.1.1.71  MAIN_PLL_MMR_CFG_PLL8_LOCKKEY1 Register
            72. 14.2.3.1.1.72  MAIN_PLL_MMR_CFG_PLL8_CTRL Register
            73. 14.2.3.1.1.73  MAIN_PLL_MMR_CFG_PLL8_STAT Register
            74. 14.2.3.1.1.74  MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL0 Register
            75. 14.2.3.1.1.75  MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL1 Register
            76. 14.2.3.1.1.76  MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL Register
            77. 14.2.3.1.1.77  MAIN_PLL_MMR_CFG_PLL8_SS_CTRL Register
            78. 14.2.3.1.1.78  MAIN_PLL_MMR_CFG_PLL8_SS_SPREAD Register
            79. 14.2.3.1.1.79  MAIN_PLL_MMR_CFG_PLL8_CAL_CTRL Register
            80. 14.2.3.1.1.80  MAIN_PLL_MMR_CFG_PLL8_CAL_STAT Register
            81. 14.2.3.1.1.81  MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0 Register
            82. 14.2.3.1.1.82  MAIN_PLL_MMR_CFG_PLL12_PID Register
            83. 14.2.3.1.1.83  MAIN_PLL_MMR_CFG_PLL12_CFG Register
            84. 14.2.3.1.1.84  MAIN_PLL_MMR_CFG_PLL12_LOCKKEY0 Register
            85. 14.2.3.1.1.85  MAIN_PLL_MMR_CFG_PLL12_LOCKKEY1 Register
            86. 14.2.3.1.1.86  MAIN_PLL_MMR_CFG_PLL12_CTRL Register
            87. 14.2.3.1.1.87  MAIN_PLL_MMR_CFG_PLL12_STAT Register
            88. 14.2.3.1.1.88  MAIN_PLL_MMR_CFG_PLL12_FREQ_CTRL0 Register
            89. 14.2.3.1.1.89  MAIN_PLL_MMR_CFG_PLL12_FREQ_CTRL1 Register
            90. 14.2.3.1.1.90  MAIN_PLL_MMR_CFG_PLL12_DIV_CTRL Register
            91. 14.2.3.1.1.91  MAIN_PLL_MMR_CFG_PLL12_SS_CTRL Register
            92. 14.2.3.1.1.92  MAIN_PLL_MMR_CFG_PLL12_SS_SPREAD Register
            93. 14.2.3.1.1.93  MAIN_PLL_MMR_CFG_PLL12_CAL_CTRL Register
            94. 14.2.3.1.1.94  MAIN_PLL_MMR_CFG_PLL12_CAL_STAT Register
            95. 14.2.3.1.1.95  MAIN_PLL_MMR_CFG_PLL12_HSDIV_CTRL0 Register
            96. 14.2.3.1.1.96  MAIN_PLL_MMR_CFG_PLL14_PID Register
            97. 14.2.3.1.1.97  MAIN_PLL_MMR_CFG_PLL14_CFG Register
            98. 14.2.3.1.1.98  MAIN_PLL_MMR_CFG_PLL14_LOCKKEY0 Register
            99. 14.2.3.1.1.99  MAIN_PLL_MMR_CFG_PLL14_LOCKKEY1 Register
            100. 14.2.3.1.1.100 MAIN_PLL_MMR_CFG_PLL14_CTRL Register
            101. 14.2.3.1.1.101 MAIN_PLL_MMR_CFG_PLL14_STAT Register
            102. 14.2.3.1.1.102 MAIN_PLL_MMR_CFG_PLL14_FREQ_CTRL0 Register
            103. 14.2.3.1.1.103 MAIN_PLL_MMR_CFG_PLL14_FREQ_CTRL1 Register
            104. 14.2.3.1.1.104 MAIN_PLL_MMR_CFG_PLL14_DIV_CTRL Register
            105. 14.2.3.1.1.105 MAIN_PLL_MMR_CFG_PLL14_SS_CTRL Register
            106. 14.2.3.1.1.106 MAIN_PLL_MMR_CFG_PLL14_SS_SPREAD Register
            107. 14.2.3.1.1.107 MAIN_PLL_MMR_CFG_PLL14_CAL_CTRL Register
            108. 14.2.3.1.1.108 MAIN_PLL_MMR_CFG_PLL14_CAL_STAT Register
            109. 14.2.3.1.1.109 MAIN_PLL_MMR_CFG_PLL14_HSDIV_CTRL0 Register
            110. 14.2.3.1.1.110 MAIN_PLL_MMR_CFG_PLL14_HSDIV_CTRL1 Register
        2. 14.2.3.2 MCU_PLL_MMR_CFG Registers
          1. 14.2.3.2.1 MCU_PLL_MMR Registers
            1. 14.2.3.2.1.1  MCU_PLL_MMR Summary Table
            2. 14.2.3.2.1.2  MCU_PLL_MMR_CFG_PLL0_PID Register
            3. 14.2.3.2.1.3  MCU_PLL_MMR_CFG_PLL0_CFG Register
            4. 14.2.3.2.1.4  MCU_PLL_MMR_CFG_PLL0_LOCKKEY0 Register
            5. 14.2.3.2.1.5  MCU_PLL_MMR_CFG_PLL0_LOCKKEY1 Register
            6. 14.2.3.2.1.6  MCU_PLL_MMR_CFG_PLL0_CTRL Register
            7. 14.2.3.2.1.7  MCU_PLL_MMR_CFG_PLL0_STAT Register
            8. 14.2.3.2.1.8  MCU_PLL_MMR_CFG_PLL0_FREQ_CTRL0 Register
            9. 14.2.3.2.1.9  MCU_PLL_MMR_CFG_PLL0_FREQ_CTRL1 Register
            10. 14.2.3.2.1.10 MCU_PLL_MMR_CFG_PLL0_DIV_CTRL Register
            11. 14.2.3.2.1.11 MCU_PLL_MMR_CFG_PLL0_SS_CTRL Register
            12. 14.2.3.2.1.12 MCU_PLL_MMR_CFG_PLL0_SS_SPREAD Register
            13. 14.2.3.2.1.13 MCU_PLL_MMR_CFG_PLL0_CAL_CTRL Register
            14. 14.2.3.2.1.14 MCU_PLL_MMR_CFG_PLL0_CAL_STAT Register
            15. 14.2.3.2.1.15 MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL0 Register
            16. 14.2.3.2.1.16 MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL1 Register
            17. 14.2.3.2.1.17 MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL2 Register
            18. 14.2.3.2.1.18 MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL3 Register
            19. 14.2.3.2.1.19 MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL4 Register
        3. 14.2.3.3 PLLCTRL Registers
          1. 14.2.3.3.1 PLLCTRL0 Registers
    3. 14.3  Processors and Accelerators Registers
      1. 14.3.1 A53SS Registers
        1. 14.3.1.1 A53SS
          1. 14.3.1.1.1 A53SS Summaries
            1.         5352
            2.         5353
            3.         5354
            4.         5355
            5.         5356
            6.         5357
            7.         5358
            8.         5359
            9.         5360
            10.         5361
            11.         5362
            12.         5363
          2. 14.3.1.1.2 A53SS Registers
            1. 14.3.1.1.2.1   ECC_AGGR_REV Register
            2. 14.3.1.1.2.2   ECC_AGGR_VECTOR Register
            3. 14.3.1.1.2.3   ECC_AGGR_STAT Register
            4. 14.3.1.1.2.4   ECC_AGGR_RESERVED_SVBUS_j Register
            5. 14.3.1.1.2.5   ECC_AGGR_SEC_EOI_REG Register
            6. 14.3.1.1.2.6   ECC_AGGR_SEC_STATUS_REG0 Register
            7. 14.3.1.1.2.7   ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            8. 14.3.1.1.2.8   ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            9. 14.3.1.1.2.9   ECC_AGGR_DED_EOI_REG Register
            10. 14.3.1.1.2.10  ECC_AGGR_DED_STATUS_REG0 Register
            11. 14.3.1.1.2.11  ECC_AGGR_DED_ENABLE_SET_REG0 Register
            12. 14.3.1.1.2.12  ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            13. 14.3.1.1.2.13  ECC_AGGR_AGGR_ENABLE_SET Register
            14. 14.3.1.1.2.14  ECC_AGGR_AGGR_ENABLE_CLR Register
            15. 14.3.1.1.2.15  ECC_AGGR_AGGR_STATUS_SET Register
            16. 14.3.1.1.2.16  ECC_AGGR_AGGR_STATUS_CLR Register
            17. 14.3.1.1.2.17  ECC_AGGR_REV Register
            18. 14.3.1.1.2.18  ECC_AGGR_VECTOR Register
            19. 14.3.1.1.2.19  ECC_AGGR_STAT Register
            20. 14.3.1.1.2.20  ECC_AGGR_RESERVED_SVBUS_j Register
            21. 14.3.1.1.2.21  ECC_AGGR_SEC_EOI_REG Register
            22. 14.3.1.1.2.22  ECC_AGGR_SEC_STATUS_REG0 Register
            23. 14.3.1.1.2.23  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            24. 14.3.1.1.2.24  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            25. 14.3.1.1.2.25  ECC_AGGR_DED_EOI_REG Register
            26. 14.3.1.1.2.26  ECC_AGGR_DED_STATUS_REG0 Register
            27. 14.3.1.1.2.27  ECC_AGGR_DED_ENABLE_SET_REG0 Register
            28. 14.3.1.1.2.28  ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            29. 14.3.1.1.2.29  ECC_AGGR_AGGR_ENABLE_SET Register
            30. 14.3.1.1.2.30  ECC_AGGR_AGGR_ENABLE_CLR Register
            31. 14.3.1.1.2.31  ECC_AGGR_AGGR_STATUS_SET Register
            32. 14.3.1.1.2.32  ECC_AGGR_AGGR_STATUS_CLR Register
            33. 14.3.1.1.2.33  ECC_AGGR_REV Register
            34. 14.3.1.1.2.34  ECC_AGGR_VECTOR Register
            35. 14.3.1.1.2.35  ECC_AGGR_STAT Register
            36. 14.3.1.1.2.36  ECC_AGGR_RESERVED_SVBUS_j Register
            37. 14.3.1.1.2.37  ECC_AGGR_SEC_EOI_REG Register
            38. 14.3.1.1.2.38  ECC_AGGR_SEC_STATUS_REG0 Register
            39. 14.3.1.1.2.39  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            40. 14.3.1.1.2.40  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            41. 14.3.1.1.2.41  ECC_AGGR_DED_EOI_REG Register
            42. 14.3.1.1.2.42  ECC_AGGR_DED_STATUS_REG0 Register
            43. 14.3.1.1.2.43  ECC_AGGR_DED_ENABLE_SET_REG0 Register
            44. 14.3.1.1.2.44  ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            45. 14.3.1.1.2.45  ECC_AGGR_AGGR_ENABLE_SET Register
            46. 14.3.1.1.2.46  ECC_AGGR_AGGR_ENABLE_CLR Register
            47. 14.3.1.1.2.47  ECC_AGGR_AGGR_STATUS_SET Register
            48. 14.3.1.1.2.48  ECC_AGGR_AGGR_STATUS_CLR Register
            49. 14.3.1.1.2.49  A53SS_APBADDR_ROMV8_ROMENTRY0 Register
            50. 14.3.1.1.2.50  A53SS_APBADDR_ROMV8_ROMENTRY1 Register
            51. 14.3.1.1.2.51  A53SS_APBADDR_ROMV8_ROMENTRY2 Register
            52. 14.3.1.1.2.52  A53SS_APBADDR_ROMV8_ROMENTRY3 Register
            53. 14.3.1.1.2.53  A53SS_APBADDR_ROMV8_ROMENTRY4 Register
            54. 14.3.1.1.2.54  A53SS_APBADDR_ROMV8_ROMENTRY5 Register
            55. 14.3.1.1.2.55  A53SS_APBADDR_ROMV8_ROMENTRY6 Register
            56. 14.3.1.1.2.56  A53SS_APBADDR_ROMV8_ROMENTRY7 Register
            57. 14.3.1.1.2.57  A53SS_APBADDR_ROMV8_ROM_PERIPHID4_VAL Register
            58. 14.3.1.1.2.58  A53SS_APBADDR_ROMV8_ROM_PERIPHID5_VAL Register
            59. 14.3.1.1.2.59  A53SS_APBADDR_ROMV8_ROM_PERIPHID6_VAL Register
            60. 14.3.1.1.2.60  A53SS_APBADDR_ROMV8_ROM_PERIPHID7_VAL Register
            61. 14.3.1.1.2.61  A53SS_APBADDR_ROMV8_ROM_PERIPHID0_VAL Register
            62. 14.3.1.1.2.62  A53SS_APBADDR_ROMV8_ROM_PERIPHID1_VAL Register
            63. 14.3.1.1.2.63  A53SS_APBADDR_ROMV8_ROM_PERIPHID2_VAL Register
            64. 14.3.1.1.2.64  A53SS_APBADDR_ROMV8_ROM_PERIPHID3_VAL Register
            65. 14.3.1.1.2.65  A53SS_APBADDR_ROMV8_ROM_COMPONID0_VAL Register
            66. 14.3.1.1.2.66  A53SS_APBADDR_ROMV8_ROM_COMPONID1_VAL Register
            67. 14.3.1.1.2.67  A53SS_APBADDR_ROMV8_ROM_COMPONID2_VAL Register
            68. 14.3.1.1.2.68  A53SS_APBADDR_ROMV8_ROM_COMPONID3_VAL Register
            69. 14.3.1.1.2.69  A53SS_APBADDR_DBG_CPU0_EDESR Register
            70. 14.3.1.1.2.70  A53SS_APBADDR_DBG_CPU0_EDECR Register
            71. 14.3.1.1.2.71  A53SS_APBADDR_DBG_CPU0_EDWAR_31_0 Register
            72. 14.3.1.1.2.72  A53SS_APBADDR_DBG_CPU0_EDWAR_63_32 Register
            73. 14.3.1.1.2.73  A53SS_APBADDR_DBG_CPU0_DBGDTRRX_EL0 Register
            74. 14.3.1.1.2.74  A53SS_APBADDR_DBG_CPU0_EDITR Register
            75. 14.3.1.1.2.75  A53SS_APBADDR_DBG_CPU0_EDSCR Register
            76. 14.3.1.1.2.76  A53SS_APBADDR_DBG_CPU0_DBGDTRTX_EL0 Register
            77. 14.3.1.1.2.77  A53SS_APBADDR_DBG_CPU0_EDRCR Register
            78. 14.3.1.1.2.78  A53SS_APBADDR_DBG_CPU0_EDACR Register
            79. 14.3.1.1.2.79  A53SS_APBADDR_DBG_CPU0_EDECCR Register
            80. 14.3.1.1.2.80  A53SS_APBADDR_DBG_CPU0_EDPCSR_31_0 Register
            81. 14.3.1.1.2.81  A53SS_APBADDR_DBG_CPU0_EDCIDSR Register
            82. 14.3.1.1.2.82  A53SS_APBADDR_DBG_CPU0_EDVIDSR Register
            83. 14.3.1.1.2.83  A53SS_APBADDR_DBG_CPU0_EDPCSR_63_32 Register
            84. 14.3.1.1.2.84  A53SS_APBADDR_DBG_CPU0_OSLAR_EL1 Register
            85. 14.3.1.1.2.85  A53SS_APBADDR_DBG_CPU0_EDPRCR Register
            86. 14.3.1.1.2.86  A53SS_APBADDR_DBG_CPU0_EDPRSR Register
            87. 14.3.1.1.2.87  A53SS_APBADDR_DBG_CPU0_DBGBVR0_EL1_31_0 Register
            88. 14.3.1.1.2.88  A53SS_APBADDR_DBG_CPU0_DBGBVR0_EL1_63_32 Register
            89. 14.3.1.1.2.89  A53SS_APBADDR_DBG_CPU0_DBGBCR0_EL1 Register
            90. 14.3.1.1.2.90  A53SS_APBADDR_DBG_CPU0_DBGBVR1_EL1_31_0 Register
            91. 14.3.1.1.2.91  A53SS_APBADDR_DBG_CPU0_DBGBVR1_EL1_63_32 Register
            92. 14.3.1.1.2.92  A53SS_APBADDR_DBG_CPU0_DBGBCR1_EL1 Register
            93. 14.3.1.1.2.93  A53SS_APBADDR_DBG_CPU0_DBGBVR2_EL1_31_0 Register
            94. 14.3.1.1.2.94  A53SS_APBADDR_DBG_CPU0_DBGBVR2_EL1_63_32 Register
            95. 14.3.1.1.2.95  A53SS_APBADDR_DBG_CPU0_DBGBCR2_EL1 Register
            96. 14.3.1.1.2.96  A53SS_APBADDR_DBG_CPU0_DBGBVR3_EL1_31_0 Register
            97. 14.3.1.1.2.97  A53SS_APBADDR_DBG_CPU0_DBGBVR3_EL1_63_32 Register
            98. 14.3.1.1.2.98  A53SS_APBADDR_DBG_CPU0_DBGBCR3_EL1 Register
            99. 14.3.1.1.2.99  A53SS_APBADDR_DBG_CPU0_DBGBVR4_EL1_31_0 Register
            100. 14.3.1.1.2.100 A53SS_APBADDR_DBG_CPU0_DBGBVR4_EL1_63_32 Register
            101. 14.3.1.1.2.101 A53SS_APBADDR_DBG_CPU0_DBGBCR4_EL1 Register
            102. 14.3.1.1.2.102 A53SS_APBADDR_DBG_CPU0_DBGBVR5_EL1_31_0 Register
            103. 14.3.1.1.2.103 A53SS_APBADDR_DBG_CPU0_DBGBVR5_EL1_63_32 Register
            104. 14.3.1.1.2.104 A53SS_APBADDR_DBG_CPU0_DBGBCR5_EL1 Register
            105. 14.3.1.1.2.105 A53SS_APBADDR_DBG_CPU0_DBGWVR0_EL1_31_0 Register
            106. 14.3.1.1.2.106 A53SS_APBADDR_DBG_CPU0_DBGWVR0_EL1_63_32 Register
            107. 14.3.1.1.2.107 A53SS_APBADDR_DBG_CPU0_DBGWCR0_EL1 Register
            108. 14.3.1.1.2.108 A53SS_APBADDR_DBG_CPU0_DBGWVR1_EL1_31_0 Register
            109. 14.3.1.1.2.109 A53SS_APBADDR_DBG_CPU0_DBGWVR1_EL1_63_32 Register
            110. 14.3.1.1.2.110 A53SS_APBADDR_DBG_CPU0_DBGWCR1_EL1 Register
            111. 14.3.1.1.2.111 A53SS_APBADDR_DBG_CPU0_DBGWVR2_EL1_31_0 Register
            112. 14.3.1.1.2.112 A53SS_APBADDR_DBG_CPU0_DBGWVR2_EL1_63_32 Register
            113. 14.3.1.1.2.113 A53SS_APBADDR_DBG_CPU0_DBGWCR2_EL1 Register
            114. 14.3.1.1.2.114 A53SS_APBADDR_DBG_CPU0_DBGWVR3_EL1_31_0 Register
            115. 14.3.1.1.2.115 A53SS_APBADDR_DBG_CPU0_DBGWVR3_EL1_63_32 Register
            116. 14.3.1.1.2.116 A53SS_APBADDR_DBG_CPU0_DBGWCR3_EL1 Register
            117. 14.3.1.1.2.117 A53SS_APBADDR_DBG_CPU0_MIDR_EL1 Register
            118. 14.3.1.1.2.118 A53SS_APBADDR_DBG_CPU0_ID_AA64PFR0_EL1_31_0 Register
            119. 14.3.1.1.2.119 A53SS_APBADDR_DBG_CPU0_ID_AA64PFR0_EL1_63_32 Register
            120. 14.3.1.1.2.120 A53SS_APBADDR_DBG_CPU0_ID_AA64DFR0_EL1_31_0 Register
            121. 14.3.1.1.2.121 A53SS_APBADDR_DBG_CPU0_ID_AA64DFR0_EL1_63_32 Register
            122. 14.3.1.1.2.122 A53SS_APBADDR_DBG_CPU0_ID_AA64ISAR0_EL1_31_0 Register
            123. 14.3.1.1.2.123 A53SS_APBADDR_DBG_CPU0_ID_AA64ISAR0_EL1_63_32 Register
            124. 14.3.1.1.2.124 A53SS_APBADDR_DBG_CPU0_ID_AA64MMFR0_EL1_31_0 Register
            125. 14.3.1.1.2.125 A53SS_APBADDR_DBG_CPU0_ID_AA64MMFR0_EL1_63_32 Register
            126. 14.3.1.1.2.126 A53SS_APBADDR_DBG_CPU0_ID_AA64PFR1_EL1_31_0 Register
            127. 14.3.1.1.2.127 A53SS_APBADDR_DBG_CPU0_ID_AA64PFR1_EL1_63_32 Register
            128. 14.3.1.1.2.128 A53SS_APBADDR_DBG_CPU0_ID_AA64DFR1_EL1_31_0 Register
            129. 14.3.1.1.2.129 A53SS_APBADDR_DBG_CPU0_ID_AA64DFR1_EL1_63_32 Register
            130. 14.3.1.1.2.130 A53SS_APBADDR_DBG_CPU0_ID_AA64ISAR1_EL1_31_0 Register
            131. 14.3.1.1.2.131 A53SS_APBADDR_DBG_CPU0_ID_AA64ISAR1_EL1_63_32 Register
            132. 14.3.1.1.2.132 A53SS_APBADDR_DBG_CPU0_ID_AA64MMFR1_EL1_31_0 Register
            133. 14.3.1.1.2.133 A53SS_APBADDR_DBG_CPU0_ID_AA64MMFR1_EL1_63_32 Register
            134. 14.3.1.1.2.134 A53SS_APBADDR_DBG_CPU0_EDITCTRL Register
            135. 14.3.1.1.2.135 A53SS_APBADDR_DBG_CPU0_DBGCLAIMSET_EL1 Register
            136. 14.3.1.1.2.136 A53SS_APBADDR_DBG_CPU0_DBGCLAIMCLR_EL1 Register
            137. 14.3.1.1.2.137 A53SS_APBADDR_DBG_CPU0_EDDEVAFF0 Register
            138. 14.3.1.1.2.138 A53SS_APBADDR_DBG_CPU0_EDDEVAFF1 Register
            139. 14.3.1.1.2.139 A53SS_APBADDR_DBG_CPU0_EDLAR Register
            140. 14.3.1.1.2.140 A53SS_APBADDR_DBG_CPU0_EDLSR Register
            141. 14.3.1.1.2.141 A53SS_APBADDR_DBG_CPU0_DBGAUTHSTATUS_EL1 Register
            142. 14.3.1.1.2.142 A53SS_APBADDR_DBG_CPU0_EDDEVARCH Register
            143. 14.3.1.1.2.143 A53SS_APBADDR_DBG_CPU0_EDDEVID2 Register
            144. 14.3.1.1.2.144 A53SS_APBADDR_DBG_CPU0_EDDEVID1 Register
            145. 14.3.1.1.2.145 A53SS_APBADDR_DBG_CPU0_EDDEVID Register
            146. 14.3.1.1.2.146 A53SS_APBADDR_DBG_CPU0_EDDEVTYPE Register
            147. 14.3.1.1.2.147 A53SS_APBADDR_DBG_CPU0_EDPIDR4 Register
            148. 14.3.1.1.2.148 A53SS_APBADDR_DBG_CPU0_EDPIDR0 Register
            149. 14.3.1.1.2.149 A53SS_APBADDR_DBG_CPU0_EDPIDR1 Register
            150. 14.3.1.1.2.150 A53SS_APBADDR_DBG_CPU0_EDPIDR2 Register
            151. 14.3.1.1.2.151 A53SS_APBADDR_DBG_CPU0_EDPIDR3 Register
            152. 14.3.1.1.2.152 A53SS_APBADDR_DBG_CPU0_EDCIDR0 Register
            153. 14.3.1.1.2.153 A53SS_APBADDR_DBG_CPU0_EDCIDR1 Register
            154. 14.3.1.1.2.154 A53SS_APBADDR_DBG_CPU0_EDCIDR2 Register
            155. 14.3.1.1.2.155 A53SS_APBADDR_DBG_CPU0_EDCIDR3 Register
            156. 14.3.1.1.2.156 A53SS_APBADDR_CTI_CPU0_CTICONTROL Register
            157. 14.3.1.1.2.157 A53SS_APBADDR_CTI_CPU0_CTIINTACK Register
            158. 14.3.1.1.2.158 A53SS_APBADDR_CTI_CPU0_CTIAPPSET Register
            159. 14.3.1.1.2.159 A53SS_APBADDR_CTI_CPU0_CTIAPPCLEAR Register
            160. 14.3.1.1.2.160 A53SS_APBADDR_CTI_CPU0_CTIAPPPULSE Register
            161. 14.3.1.1.2.161 A53SS_APBADDR_CTI_CPU0_CTIINEN0 Register
            162. 14.3.1.1.2.162 A53SS_APBADDR_CTI_CPU0_CTIINEN1 Register
            163. 14.3.1.1.2.163 A53SS_APBADDR_CTI_CPU0_CTIINEN2 Register
            164. 14.3.1.1.2.164 A53SS_APBADDR_CTI_CPU0_CTIINEN3 Register
            165. 14.3.1.1.2.165 A53SS_APBADDR_CTI_CPU0_CTIINEN4 Register
            166. 14.3.1.1.2.166 A53SS_APBADDR_CTI_CPU0_CTIINEN5 Register
            167. 14.3.1.1.2.167 A53SS_APBADDR_CTI_CPU0_CTIINEN6 Register
            168. 14.3.1.1.2.168 A53SS_APBADDR_CTI_CPU0_CTIINEN7 Register
            169. 14.3.1.1.2.169 A53SS_APBADDR_CTI_CPU0_CTIOUTEN0 Register
            170. 14.3.1.1.2.170 A53SS_APBADDR_CTI_CPU0_CTIOUTEN1 Register
            171. 14.3.1.1.2.171 A53SS_APBADDR_CTI_CPU0_CTIOUTEN2 Register
            172. 14.3.1.1.2.172 A53SS_APBADDR_CTI_CPU0_CTIOUTEN3 Register
            173. 14.3.1.1.2.173 A53SS_APBADDR_CTI_CPU0_CTIOUTEN4 Register
            174. 14.3.1.1.2.174 A53SS_APBADDR_CTI_CPU0_CTIOUTEN5 Register
            175. 14.3.1.1.2.175 A53SS_APBADDR_CTI_CPU0_CTIOUTEN6 Register
            176. 14.3.1.1.2.176 A53SS_APBADDR_CTI_CPU0_CTIOUTEN7 Register
            177. 14.3.1.1.2.177 A53SS_APBADDR_CTI_CPU0_CTITRIGINSTATUS Register
            178. 14.3.1.1.2.178 A53SS_APBADDR_CTI_CPU0_CTITRIGOUTSTATUS Register
            179. 14.3.1.1.2.179 A53SS_APBADDR_CTI_CPU0_CTICHINSTATUS Register
            180. 14.3.1.1.2.180 A53SS_APBADDR_CTI_CPU0_CTICHOUTSTATUS Register
            181. 14.3.1.1.2.181 A53SS_APBADDR_CTI_CPU0_CTIGATE Register
            182. 14.3.1.1.2.182 A53SS_APBADDR_CTI_CPU0_ASICCTL Register
            183. 14.3.1.1.2.183 A53SS_APBADDR_CTI_CPU0_CTIITCTRL Register
            184. 14.3.1.1.2.184 A53SS_APBADDR_CTI_CPU0_CTICLAIMSET Register
            185. 14.3.1.1.2.185 A53SS_APBADDR_CTI_CPU0_CTICLAIMCLR Register
            186. 14.3.1.1.2.186 A53SS_APBADDR_CTI_CPU0_CTIDEVAFF0 Register
            187. 14.3.1.1.2.187 A53SS_APBADDR_CTI_CPU0_CTIDEVAFF1 Register
            188. 14.3.1.1.2.188 A53SS_APBADDR_CTI_CPU0_CTILAR Register
            189. 14.3.1.1.2.189 A53SS_APBADDR_CTI_CPU0_CTILSR Register
            190. 14.3.1.1.2.190 A53SS_APBADDR_CTI_CPU0_CTIAUTHSTATUS Register
            191. 14.3.1.1.2.191 A53SS_APBADDR_CTI_CPU0_CTIDEVARCH Register
            192. 14.3.1.1.2.192 A53SS_APBADDR_CTI_CPU0_CTIDEVID2 Register
            193. 14.3.1.1.2.193 A53SS_APBADDR_CTI_CPU0_CTIDEVID1 Register
            194. 14.3.1.1.2.194 A53SS_APBADDR_CTI_CPU0_CTIDEVID Register
            195. 14.3.1.1.2.195 A53SS_APBADDR_CTI_CPU0_CTIDEVTYPE Register
            196. 14.3.1.1.2.196 A53SS_APBADDR_CTI_CPU0_CTIPIDR4 Register
            197. 14.3.1.1.2.197 A53SS_APBADDR_CTI_CPU0_CTIPIDR5 Register
            198. 14.3.1.1.2.198 A53SS_APBADDR_CTI_CPU0_CTIPIDR6 Register
            199. 14.3.1.1.2.199 A53SS_APBADDR_CTI_CPU0_CTIPIDR7 Register
            200. 14.3.1.1.2.200 A53SS_APBADDR_CTI_CPU0_CTIPIDR0 Register
            201. 14.3.1.1.2.201 A53SS_APBADDR_CTI_CPU0_CTIPIDR1 Register
            202. 14.3.1.1.2.202 A53SS_APBADDR_CTI_CPU0_CTIPIDR2 Register
            203. 14.3.1.1.2.203 A53SS_APBADDR_CTI_CPU0_CTIPIDR3 Register
            204. 14.3.1.1.2.204 A53SS_APBADDR_CTI_CPU0_CTICIDR0 Register
            205. 14.3.1.1.2.205 A53SS_APBADDR_CTI_CPU0_CTICIDR1 Register
            206. 14.3.1.1.2.206 A53SS_APBADDR_CTI_CPU0_CTICIDR2 Register
            207. 14.3.1.1.2.207 A53SS_APBADDR_CTI_CPU0_CTICIDR3 Register
            208. 14.3.1.1.2.208 A53SS_APBADDR_PMU_CPU0_PMEVCNTR0_EL0 Register
            209. 14.3.1.1.2.209 A53SS_APBADDR_PMU_CPU0_PMEVCNTR1_EL0 Register
            210. 14.3.1.1.2.210 A53SS_APBADDR_PMU_CPU0_PMEVCNTR2_EL0 Register
            211. 14.3.1.1.2.211 A53SS_APBADDR_PMU_CPU0_PMEVCNTR3_EL0 Register
            212. 14.3.1.1.2.212 A53SS_APBADDR_PMU_CPU0_PMEVCNTR4_EL0 Register
            213. 14.3.1.1.2.213 A53SS_APBADDR_PMU_CPU0_PMEVCNTR5_EL0 Register
            214. 14.3.1.1.2.214 A53SS_APBADDR_PMU_CPU0_PMCCNTR_EL0_31_0 Register
            215. 14.3.1.1.2.215 A53SS_APBADDR_PMU_CPU0_PMCCNTR_EL0_63_32 Register
            216. 14.3.1.1.2.216 A53SS_APBADDR_PMU_CPU0_PMEVTYPER0_EL0 Register
            217. 14.3.1.1.2.217 A53SS_APBADDR_PMU_CPU0_PMEVTYPER1_EL0 Register
            218. 14.3.1.1.2.218 A53SS_APBADDR_PMU_CPU0_PMEVTYPER2_EL0 Register
            219. 14.3.1.1.2.219 A53SS_APBADDR_PMU_CPU0_PMEVTYPER3_EL0 Register
            220. 14.3.1.1.2.220 A53SS_APBADDR_PMU_CPU0_PMEVTYPER4_EL0 Register
            221. 14.3.1.1.2.221 A53SS_APBADDR_PMU_CPU0_PMEVTYPER5_EL0 Register
            222. 14.3.1.1.2.222 A53SS_APBADDR_PMU_CPU0_PMCCFILTR_EL0 Register
            223. 14.3.1.1.2.223 A53SS_APBADDR_PMU_CPU0_PMCNTENSET_EL0 Register
            224. 14.3.1.1.2.224 A53SS_APBADDR_PMU_CPU0_PMCNTENCLR_EL0 Register
            225. 14.3.1.1.2.225 A53SS_APBADDR_PMU_CPU0_PMINTENSET_EL1 Register
            226. 14.3.1.1.2.226 A53SS_APBADDR_PMU_CPU0_PMINTENCLR_EL1 Register
            227. 14.3.1.1.2.227 A53SS_APBADDR_PMU_CPU0_PMOVSCLR_EL0 Register
            228. 14.3.1.1.2.228 A53SS_APBADDR_PMU_CPU0_PMSWINC_EL0 Register
            229. 14.3.1.1.2.229 A53SS_APBADDR_PMU_CPU0_PMOVSSET_EL0 Register
            230. 14.3.1.1.2.230 A53SS_APBADDR_PMU_CPU0_PMCFGR Register
            231. 14.3.1.1.2.231 A53SS_APBADDR_PMU_CPU0_PMCR_EL0 Register
            232. 14.3.1.1.2.232 A53SS_APBADDR_PMU_CPU0_PMCEID0_EL0 Register
            233. 14.3.1.1.2.233 A53SS_APBADDR_PMU_CPU0_PMCEID1_EL0 Register
            234. 14.3.1.1.2.234 A53SS_APBADDR_PMU_CPU0_PMITCTRL Register
            235. 14.3.1.1.2.235 A53SS_APBADDR_PMU_CPU0_PMDEVAFF0 Register
            236. 14.3.1.1.2.236 A53SS_APBADDR_PMU_CPU0_PMDEVAFF1 Register
            237. 14.3.1.1.2.237 A53SS_APBADDR_PMU_CPU0_PMLAR Register
            238. 14.3.1.1.2.238 A53SS_APBADDR_PMU_CPU0_PMLSR Register
            239. 14.3.1.1.2.239 A53SS_APBADDR_PMU_CPU0_PMAUTHSTATUS Register
            240. 14.3.1.1.2.240 A53SS_APBADDR_PMU_CPU0_PMDEVARCH Register
            241. 14.3.1.1.2.241 A53SS_APBADDR_PMU_CPU0_PMDEVTYPE Register
            242. 14.3.1.1.2.242 A53SS_APBADDR_PMU_CPU0_PMPIDR4 Register
            243. 14.3.1.1.2.243 A53SS_APBADDR_PMU_CPU0_PMPIDR5 Register
            244. 14.3.1.1.2.244 A53SS_APBADDR_PMU_CPU0_PMPIDR6 Register
            245. 14.3.1.1.2.245 A53SS_APBADDR_PMU_CPU0_PMPIDR7 Register
            246. 14.3.1.1.2.246 A53SS_APBADDR_PMU_CPU0_PMPIDR0 Register
            247. 14.3.1.1.2.247 A53SS_APBADDR_PMU_CPU0_PMPIDR1 Register
            248. 14.3.1.1.2.248 A53SS_APBADDR_PMU_CPU0_PMPIDR2 Register
            249. 14.3.1.1.2.249 A53SS_APBADDR_PMU_CPU0_PMPIDR3 Register
            250. 14.3.1.1.2.250 A53SS_APBADDR_PMU_CPU0_PMCIDR0 Register
            251. 14.3.1.1.2.251 A53SS_APBADDR_PMU_CPU0_PMCIDR1 Register
            252. 14.3.1.1.2.252 A53SS_APBADDR_PMU_CPU0_PMCIDR2 Register
            253. 14.3.1.1.2.253 A53SS_APBADDR_PMU_CPU0_PMCIDR3 Register
            254. 14.3.1.1.2.254 A53SS_APBADDR_ETM_CPU0_TRCPRGCTLR Register
            255. 14.3.1.1.2.255 A53SS_APBADDR_ETM_CPU0_TRCSTATR Register
            256. 14.3.1.1.2.256 A53SS_APBADDR_ETM_CPU0_TRCCONFIGR Register
            257. 14.3.1.1.2.257 A53SS_APBADDR_ETM_CPU0_TRCAUXCTLR Register
            258. 14.3.1.1.2.258 A53SS_APBADDR_ETM_CPU0_TRCEVENTCTL0R Register
            259. 14.3.1.1.2.259 A53SS_APBADDR_ETM_CPU0_TRCEVENTCTL1R Register
            260. 14.3.1.1.2.260 A53SS_APBADDR_ETM_CPU0_TRCSTALLCTLR Register
            261. 14.3.1.1.2.261 A53SS_APBADDR_ETM_CPU0_TRCTSCTLR Register
            262. 14.3.1.1.2.262 A53SS_APBADDR_ETM_CPU0_TRCSYNCPR Register
            263. 14.3.1.1.2.263 A53SS_APBADDR_ETM_CPU0_TRCCCCTLR Register
            264. 14.3.1.1.2.264 A53SS_APBADDR_ETM_CPU0_TRCBBCTLR Register
            265. 14.3.1.1.2.265 A53SS_APBADDR_ETM_CPU0_TRCTRACEIDR Register
            266. 14.3.1.1.2.266 A53SS_APBADDR_ETM_CPU0_TRCVICTLR Register
            267. 14.3.1.1.2.267 A53SS_APBADDR_ETM_CPU0_TRCVIIECTLR Register
            268. 14.3.1.1.2.268 A53SS_APBADDR_ETM_CPU0_TRCVISSCTLR Register
            269. 14.3.1.1.2.269 A53SS_APBADDR_ETM_CPU0_TRCSEQEVR0 Register
            270. 14.3.1.1.2.270 A53SS_APBADDR_ETM_CPU0_TRCSEQEVR1 Register
            271. 14.3.1.1.2.271 A53SS_APBADDR_ETM_CPU0_TRCSEQEVR2 Register
            272. 14.3.1.1.2.272 A53SS_APBADDR_ETM_CPU0_TRCSEQRSTEVR Register
            273. 14.3.1.1.2.273 A53SS_APBADDR_ETM_CPU0_TRCSEQSTR Register
            274. 14.3.1.1.2.274 A53SS_APBADDR_ETM_CPU0_TRCEXTINSELR Register
            275. 14.3.1.1.2.275 A53SS_APBADDR_ETM_CPU0_TRCCNTRLDVR0 Register
            276. 14.3.1.1.2.276 A53SS_APBADDR_ETM_CPU0_TRCCNTRLDVR1 Register
            277. 14.3.1.1.2.277 A53SS_APBADDR_ETM_CPU0_TRCCNTCTLR0 Register
            278. 14.3.1.1.2.278 A53SS_APBADDR_ETM_CPU0_TRCCNTCTLR1 Register
            279. 14.3.1.1.2.279 A53SS_APBADDR_ETM_CPU0_TRCCNTVR0 Register
            280. 14.3.1.1.2.280 A53SS_APBADDR_ETM_CPU0_TRCCNTVR1 Register
            281. 14.3.1.1.2.281 A53SS_APBADDR_ETM_CPU0_TRCIDR8 Register
            282. 14.3.1.1.2.282 A53SS_APBADDR_ETM_CPU0_TRCIDR9 Register
            283. 14.3.1.1.2.283 A53SS_APBADDR_ETM_CPU0_TRCIDR10 Register
            284. 14.3.1.1.2.284 A53SS_APBADDR_ETM_CPU0_TRCIDR11 Register
            285. 14.3.1.1.2.285 A53SS_APBADDR_ETM_CPU0_TRCIDR12 Register
            286. 14.3.1.1.2.286 A53SS_APBADDR_ETM_CPU0_TRCIDR13 Register
            287. 14.3.1.1.2.287 A53SS_APBADDR_ETM_CPU0_TRCIMSPEC0 Register
            288. 14.3.1.1.2.288 A53SS_APBADDR_ETM_CPU0_TRCIDR0 Register
            289. 14.3.1.1.2.289 A53SS_APBADDR_ETM_CPU0_TRCIDR1 Register
            290. 14.3.1.1.2.290 A53SS_APBADDR_ETM_CPU0_TRCIDR2 Register
            291. 14.3.1.1.2.291 A53SS_APBADDR_ETM_CPU0_TRCIDR3 Register
            292. 14.3.1.1.2.292 A53SS_APBADDR_ETM_CPU0_TRCIDR4 Register
            293. 14.3.1.1.2.293 A53SS_APBADDR_ETM_CPU0_TRCIDR5 Register
            294. 14.3.1.1.2.294 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR2 Register
            295. 14.3.1.1.2.295 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR3 Register
            296. 14.3.1.1.2.296 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR4 Register
            297. 14.3.1.1.2.297 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR5 Register
            298. 14.3.1.1.2.298 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR6 Register
            299. 14.3.1.1.2.299 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR7 Register
            300. 14.3.1.1.2.300 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR8 Register
            301. 14.3.1.1.2.301 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR9 Register
            302. 14.3.1.1.2.302 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR10 Register
            303. 14.3.1.1.2.303 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR11 Register
            304. 14.3.1.1.2.304 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR12 Register
            305. 14.3.1.1.2.305 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR13 Register
            306. 14.3.1.1.2.306 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR14 Register
            307. 14.3.1.1.2.307 A53SS_APBADDR_ETM_CPU0_TRCRSCTLR15 Register
            308. 14.3.1.1.2.308 A53SS_APBADDR_ETM_CPU0_TRCSSCCR0 Register
            309. 14.3.1.1.2.309 A53SS_APBADDR_ETM_CPU0_TRCSSCSR0 Register
            310. 14.3.1.1.2.310 A53SS_APBADDR_ETM_CPU0_TRCOSLAR Register
            311. 14.3.1.1.2.311 A53SS_APBADDR_ETM_CPU0_TRCOSLSR Register
            312. 14.3.1.1.2.312 A53SS_APBADDR_ETM_CPU0_TRCPDCR Register
            313. 14.3.1.1.2.313 A53SS_APBADDR_ETM_CPU0_TRCPDSR Register
            314. 14.3.1.1.2.314 A53SS_APBADDR_ETM_CPU0_TRCACVR0_31_0 Register
            315. 14.3.1.1.2.315 A53SS_APBADDR_ETM_CPU0_TRCACVR0_63_32 Register
            316. 14.3.1.1.2.316 A53SS_APBADDR_ETM_CPU0_TRCACVR1_31_0 Register
            317. 14.3.1.1.2.317 A53SS_APBADDR_ETM_CPU0_TRCACVR1_63_32 Register
            318. 14.3.1.1.2.318 A53SS_APBADDR_ETM_CPU0_TRCACVR2_31_0 Register
            319. 14.3.1.1.2.319 A53SS_APBADDR_ETM_CPU0_TRCACVR2_63_32 Register
            320. 14.3.1.1.2.320 A53SS_APBADDR_ETM_CPU0_TRCACVR3_31_0 Register
            321. 14.3.1.1.2.321 A53SS_APBADDR_ETM_CPU0_TRCACVR3_63_32 Register
            322. 14.3.1.1.2.322 A53SS_APBADDR_ETM_CPU0_TRCACVR4_31_0 Register
            323. 14.3.1.1.2.323 A53SS_APBADDR_ETM_CPU0_TRCACVR4_63_32 Register
            324. 14.3.1.1.2.324 A53SS_APBADDR_ETM_CPU0_TRCACVR5_31_0 Register
            325. 14.3.1.1.2.325 A53SS_APBADDR_ETM_CPU0_TRCACVR5_63_32 Register
            326. 14.3.1.1.2.326 A53SS_APBADDR_ETM_CPU0_TRCACVR6_31_0 Register
            327. 14.3.1.1.2.327 A53SS_APBADDR_ETM_CPU0_TRCACVR6_63_32 Register
            328. 14.3.1.1.2.328 A53SS_APBADDR_ETM_CPU0_TRCACVR7_31_0 Register
            329. 14.3.1.1.2.329 A53SS_APBADDR_ETM_CPU0_TRCACVR7_63_32 Register
            330. 14.3.1.1.2.330 A53SS_APBADDR_ETM_CPU0_TRCACATR0 Register
            331. 14.3.1.1.2.331 A53SS_APBADDR_ETM_CPU0_TRCACATR1 Register
            332. 14.3.1.1.2.332 A53SS_APBADDR_ETM_CPU0_TRCACATR2 Register
            333. 14.3.1.1.2.333 A53SS_APBADDR_ETM_CPU0_TRCACATR3 Register
            334. 14.3.1.1.2.334 A53SS_APBADDR_ETM_CPU0_TRCACATR4 Register
            335. 14.3.1.1.2.335 A53SS_APBADDR_ETM_CPU0_TRCACATR5 Register
            336. 14.3.1.1.2.336 A53SS_APBADDR_ETM_CPU0_TRCACATR6 Register
            337. 14.3.1.1.2.337 A53SS_APBADDR_ETM_CPU0_TRCACATR7 Register
            338. 14.3.1.1.2.338 A53SS_APBADDR_ETM_CPU0_TRCCIDCVR0 Register
            339. 14.3.1.1.2.339 A53SS_APBADDR_ETM_CPU0_TRCVMIDCVR0 Register
            340. 14.3.1.1.2.340 A53SS_APBADDR_ETM_CPU0_TRCCIDCCTLR0 Register
            341. 14.3.1.1.2.341 A53SS_APBADDR_ETM_CPU0_TRCITATBIDR Register
            342. 14.3.1.1.2.342 A53SS_APBADDR_ETM_CPU0_TRCITIDATAR Register
            343. 14.3.1.1.2.343 A53SS_APBADDR_ETM_CPU0_TRCITIATBINR Register
            344. 14.3.1.1.2.344 A53SS_APBADDR_ETM_CPU0_TRCITIATBOUTR Register
            345. 14.3.1.1.2.345 A53SS_APBADDR_ETM_CPU0_TRCITCTRL Register
            346. 14.3.1.1.2.346 A53SS_APBADDR_ETM_CPU0_TRCCLAIMSET Register
            347. 14.3.1.1.2.347 A53SS_APBADDR_ETM_CPU0_TRCCLAIMCLR Register
            348. 14.3.1.1.2.348 A53SS_APBADDR_ETM_CPU0_TRCDEVAFF0 Register
            349. 14.3.1.1.2.349 A53SS_APBADDR_ETM_CPU0_TRCDEVAFF1 Register
            350. 14.3.1.1.2.350 A53SS_APBADDR_ETM_CPU0_TRCLAR Register
            351. 14.3.1.1.2.351 A53SS_APBADDR_ETM_CPU0_TRCLSR Register
            352. 14.3.1.1.2.352 A53SS_APBADDR_ETM_CPU0_TRCAUTHSTATUS Register
            353. 14.3.1.1.2.353 A53SS_APBADDR_ETM_CPU0_TRCDEVARCH Register
            354. 14.3.1.1.2.354 A53SS_APBADDR_ETM_CPU0_TRCDEVID Register
            355. 14.3.1.1.2.355 A53SS_APBADDR_ETM_CPU0_TRCDEVTYPE Register
            356. 14.3.1.1.2.356 A53SS_APBADDR_ETM_CPU0_TRCPIDR4 Register
            357. 14.3.1.1.2.357 A53SS_APBADDR_ETM_CPU0_TRCPIDR5 Register
            358. 14.3.1.1.2.358 A53SS_APBADDR_ETM_CPU0_TRCPIDR6 Register
            359. 14.3.1.1.2.359 A53SS_APBADDR_ETM_CPU0_TRCPIDR7 Register
            360. 14.3.1.1.2.360 A53SS_APBADDR_ETM_CPU0_TRCPIDR0 Register
            361. 14.3.1.1.2.361 A53SS_APBADDR_ETM_CPU0_TRCPIDR1 Register
            362. 14.3.1.1.2.362 A53SS_APBADDR_ETM_CPU0_TRCPIDR2 Register
            363. 14.3.1.1.2.363 A53SS_APBADDR_ETM_CPU0_TRCPIDR3 Register
            364. 14.3.1.1.2.364 A53SS_APBADDR_ETM_CPU0_TRCCIDR0 Register
            365. 14.3.1.1.2.365 A53SS_APBADDR_ETM_CPU0_TRCCIDR1 Register
            366. 14.3.1.1.2.366 A53SS_APBADDR_ETM_CPU0_TRCCIDR2 Register
            367. 14.3.1.1.2.367 A53SS_APBADDR_ETM_CPU0_TRCCIDR3 Register
            368. 14.3.1.1.2.368 A53SS_APBADDR_DBG_CPU1_EDESR Register
            369. 14.3.1.1.2.369 A53SS_APBADDR_DBG_CPU1_EDECR Register
            370. 14.3.1.1.2.370 A53SS_APBADDR_DBG_CPU1_EDWAR_31_0 Register
            371. 14.3.1.1.2.371 A53SS_APBADDR_DBG_CPU1_EDWAR_63_32 Register
            372. 14.3.1.1.2.372 A53SS_APBADDR_DBG_CPU1_DBGDTRRX_EL0 Register
            373. 14.3.1.1.2.373 A53SS_APBADDR_DBG_CPU1_EDITR Register
            374. 14.3.1.1.2.374 A53SS_APBADDR_DBG_CPU1_EDSCR Register
            375. 14.3.1.1.2.375 A53SS_APBADDR_DBG_CPU1_DBGDTRTX_EL0 Register
            376. 14.3.1.1.2.376 A53SS_APBADDR_DBG_CPU1_EDRCR Register
            377. 14.3.1.1.2.377 A53SS_APBADDR_DBG_CPU1_EDACR Register
            378. 14.3.1.1.2.378 A53SS_APBADDR_DBG_CPU1_EDECCR Register
            379. 14.3.1.1.2.379 A53SS_APBADDR_DBG_CPU1_EDPCSR_31_0 Register
            380. 14.3.1.1.2.380 A53SS_APBADDR_DBG_CPU1_EDCIDSR Register
            381. 14.3.1.1.2.381 A53SS_APBADDR_DBG_CPU1_EDVIDSR Register
            382. 14.3.1.1.2.382 A53SS_APBADDR_DBG_CPU1_EDPCSR_63_32 Register
            383. 14.3.1.1.2.383 A53SS_APBADDR_DBG_CPU1_OSLAR_EL1 Register
            384. 14.3.1.1.2.384 A53SS_APBADDR_DBG_CPU1_EDPRCR Register
            385. 14.3.1.1.2.385 A53SS_APBADDR_DBG_CPU1_EDPRSR Register
            386. 14.3.1.1.2.386 A53SS_APBADDR_DBG_CPU1_DBGBVR0_EL1_31_0 Register
            387. 14.3.1.1.2.387 A53SS_APBADDR_DBG_CPU1_DBGBVR0_EL1_63_32 Register
            388. 14.3.1.1.2.388 A53SS_APBADDR_DBG_CPU1_DBGBCR0_EL1 Register
            389. 14.3.1.1.2.389 A53SS_APBADDR_DBG_CPU1_DBGBVR1_EL1_31_0 Register
            390. 14.3.1.1.2.390 A53SS_APBADDR_DBG_CPU1_DBGBVR1_EL1_63_32 Register
            391. 14.3.1.1.2.391 A53SS_APBADDR_DBG_CPU1_DBGBCR1_EL1 Register
            392. 14.3.1.1.2.392 A53SS_APBADDR_DBG_CPU1_DBGBVR2_EL1_31_0 Register
            393. 14.3.1.1.2.393 A53SS_APBADDR_DBG_CPU1_DBGBVR2_EL1_63_32 Register
            394. 14.3.1.1.2.394 A53SS_APBADDR_DBG_CPU1_DBGBCR2_EL1 Register
            395. 14.3.1.1.2.395 A53SS_APBADDR_DBG_CPU1_DBGBVR3_EL1_31_0 Register
            396. 14.3.1.1.2.396 A53SS_APBADDR_DBG_CPU1_DBGBVR3_EL1_63_32 Register
            397. 14.3.1.1.2.397 A53SS_APBADDR_DBG_CPU1_DBGBCR3_EL1 Register
            398. 14.3.1.1.2.398 A53SS_APBADDR_DBG_CPU1_DBGBVR4_EL1_31_0 Register
            399. 14.3.1.1.2.399 A53SS_APBADDR_DBG_CPU1_DBGBVR4_EL1_63_32 Register
            400. 14.3.1.1.2.400 A53SS_APBADDR_DBG_CPU1_DBGBCR4_EL1 Register
            401. 14.3.1.1.2.401 A53SS_APBADDR_DBG_CPU1_DBGBVR5_EL1_31_0 Register
            402. 14.3.1.1.2.402 A53SS_APBADDR_DBG_CPU1_DBGBVR5_EL1_63_32 Register
            403. 14.3.1.1.2.403 A53SS_APBADDR_DBG_CPU1_DBGBCR5_EL1 Register
            404. 14.3.1.1.2.404 A53SS_APBADDR_DBG_CPU1_DBGWVR0_EL1_31_0 Register
            405. 14.3.1.1.2.405 A53SS_APBADDR_DBG_CPU1_DBGWVR0_EL1_63_32 Register
            406. 14.3.1.1.2.406 A53SS_APBADDR_DBG_CPU1_DBGWCR0_EL1 Register
            407. 14.3.1.1.2.407 A53SS_APBADDR_DBG_CPU1_DBGWVR1_EL1_31_0 Register
            408. 14.3.1.1.2.408 A53SS_APBADDR_DBG_CPU1_DBGWVR1_EL1_63_32 Register
            409. 14.3.1.1.2.409 A53SS_APBADDR_DBG_CPU1_DBGWCR1_EL1 Register
            410. 14.3.1.1.2.410 A53SS_APBADDR_DBG_CPU1_DBGWVR2_EL1_31_0 Register
            411. 14.3.1.1.2.411 A53SS_APBADDR_DBG_CPU1_DBGWVR2_EL1_63_32 Register
            412. 14.3.1.1.2.412 A53SS_APBADDR_DBG_CPU1_DBGWCR2_EL1 Register
            413. 14.3.1.1.2.413 A53SS_APBADDR_DBG_CPU1_DBGWVR3_EL1_31_0 Register
            414. 14.3.1.1.2.414 A53SS_APBADDR_DBG_CPU1_DBGWVR3_EL1_63_32 Register
            415. 14.3.1.1.2.415 A53SS_APBADDR_DBG_CPU1_DBGWCR3_EL1 Register
            416. 14.3.1.1.2.416 A53SS_APBADDR_DBG_CPU1_MIDR_EL1 Register
            417. 14.3.1.1.2.417 A53SS_APBADDR_DBG_CPU1_ID_AA64PFR0_EL1_31_0 Register
            418. 14.3.1.1.2.418 A53SS_APBADDR_DBG_CPU1_ID_AA64PFR0_EL1_63_32 Register
            419. 14.3.1.1.2.419 A53SS_APBADDR_DBG_CPU1_ID_AA64DFR0_EL1_31_0 Register
            420. 14.3.1.1.2.420 A53SS_APBADDR_DBG_CPU1_ID_AA64DFR0_EL1_63_32 Register
            421. 14.3.1.1.2.421 A53SS_APBADDR_DBG_CPU1_ID_AA64ISAR0_EL1_31_0 Register
            422. 14.3.1.1.2.422 A53SS_APBADDR_DBG_CPU1_ID_AA64ISAR0_EL1_63_32 Register
            423. 14.3.1.1.2.423 A53SS_APBADDR_DBG_CPU1_ID_AA64MMFR0_EL1_31_0 Register
            424. 14.3.1.1.2.424 A53SS_APBADDR_DBG_CPU1_ID_AA64MMFR0_EL1_63_32 Register
            425. 14.3.1.1.2.425 A53SS_APBADDR_DBG_CPU1_ID_AA64PFR1_EL1_31_0 Register
            426. 14.3.1.1.2.426 A53SS_APBADDR_DBG_CPU1_ID_AA64PFR1_EL1_63_32 Register
            427. 14.3.1.1.2.427 A53SS_APBADDR_DBG_CPU1_ID_AA64DFR1_EL1_31_0 Register
            428. 14.3.1.1.2.428 A53SS_APBADDR_DBG_CPU1_ID_AA64DFR1_EL1_63_32 Register
            429. 14.3.1.1.2.429 A53SS_APBADDR_DBG_CPU1_ID_AA64ISAR1_EL1_31_0 Register
            430. 14.3.1.1.2.430 A53SS_APBADDR_DBG_CPU1_ID_AA64ISAR1_EL1_63_32 Register
            431. 14.3.1.1.2.431 A53SS_APBADDR_DBG_CPU1_ID_AA64MMFR1_EL1_31_0 Register
            432. 14.3.1.1.2.432 A53SS_APBADDR_DBG_CPU1_ID_AA64MMFR1_EL1_63_32 Register
            433. 14.3.1.1.2.433 A53SS_APBADDR_DBG_CPU1_EDITCTRL Register
            434. 14.3.1.1.2.434 A53SS_APBADDR_DBG_CPU1_DBGCLAIMSET_EL1 Register
            435. 14.3.1.1.2.435 A53SS_APBADDR_DBG_CPU1_DBGCLAIMCLR_EL1 Register
            436. 14.3.1.1.2.436 A53SS_APBADDR_DBG_CPU1_EDDEVAFF0 Register
            437. 14.3.1.1.2.437 A53SS_APBADDR_DBG_CPU1_EDDEVAFF1 Register
            438. 14.3.1.1.2.438 A53SS_APBADDR_DBG_CPU1_EDLAR Register
            439. 14.3.1.1.2.439 A53SS_APBADDR_DBG_CPU1_EDLSR Register
            440. 14.3.1.1.2.440 A53SS_APBADDR_DBG_CPU1_DBGAUTHSTATUS_EL1 Register
            441. 14.3.1.1.2.441 A53SS_APBADDR_DBG_CPU1_EDDEVARCH Register
            442. 14.3.1.1.2.442 A53SS_APBADDR_DBG_CPU1_EDDEVID2 Register
            443. 14.3.1.1.2.443 A53SS_APBADDR_DBG_CPU1_EDDEVID1 Register
            444. 14.3.1.1.2.444 A53SS_APBADDR_DBG_CPU1_EDDEVID Register
            445. 14.3.1.1.2.445 A53SS_APBADDR_DBG_CPU1_EDDEVTYPE Register
            446. 14.3.1.1.2.446 A53SS_APBADDR_DBG_CPU1_EDPIDR4 Register
            447. 14.3.1.1.2.447 A53SS_APBADDR_DBG_CPU1_EDPIDR0 Register
            448. 14.3.1.1.2.448 A53SS_APBADDR_DBG_CPU1_EDPIDR1 Register
            449. 14.3.1.1.2.449 A53SS_APBADDR_DBG_CPU1_EDPIDR2 Register
            450. 14.3.1.1.2.450 A53SS_APBADDR_DBG_CPU1_EDPIDR3 Register
            451. 14.3.1.1.2.451 A53SS_APBADDR_DBG_CPU1_EDCIDR0 Register
            452. 14.3.1.1.2.452 A53SS_APBADDR_DBG_CPU1_EDCIDR1 Register
            453. 14.3.1.1.2.453 A53SS_APBADDR_DBG_CPU1_EDCIDR2 Register
            454. 14.3.1.1.2.454 A53SS_APBADDR_DBG_CPU1_EDCIDR3 Register
            455. 14.3.1.1.2.455 A53SS_APBADDR_PMU_CPU1_PMEVCNTR0_EL0 Register
            456. 14.3.1.1.2.456 A53SS_APBADDR_PMU_CPU1_PMEVCNTR1_EL0 Register
            457. 14.3.1.1.2.457 A53SS_APBADDR_PMU_CPU1_PMEVCNTR2_EL0 Register
            458. 14.3.1.1.2.458 A53SS_APBADDR_PMU_CPU1_PMEVCNTR3_EL0 Register
            459. 14.3.1.1.2.459 A53SS_APBADDR_PMU_CPU1_PMEVCNTR4_EL0 Register
            460. 14.3.1.1.2.460 A53SS_APBADDR_PMU_CPU1_PMEVCNTR5_EL0 Register
            461. 14.3.1.1.2.461 A53SS_APBADDR_PMU_CPU1_PMCCNTR_EL0_31_0 Register
            462. 14.3.1.1.2.462 A53SS_APBADDR_PMU_CPU1_PMCCNTR_EL0_63_32 Register
            463. 14.3.1.1.2.463 A53SS_APBADDR_PMU_CPU1_PMEVTYPER0_EL0 Register
            464. 14.3.1.1.2.464 A53SS_APBADDR_PMU_CPU1_PMEVTYPER1_EL0 Register
            465. 14.3.1.1.2.465 A53SS_APBADDR_PMU_CPU1_PMEVTYPER2_EL0 Register
            466. 14.3.1.1.2.466 A53SS_APBADDR_PMU_CPU1_PMEVTYPER3_EL0 Register
            467. 14.3.1.1.2.467 A53SS_APBADDR_PMU_CPU1_PMEVTYPER4_EL0 Register
            468. 14.3.1.1.2.468 A53SS_APBADDR_PMU_CPU1_PMEVTYPER5_EL0 Register
            469. 14.3.1.1.2.469 A53SS_APBADDR_PMU_CPU1_PMCCFILTR_EL0 Register
            470. 14.3.1.1.2.470 A53SS_APBADDR_PMU_CPU1_PMCNTENSET_EL0 Register
            471. 14.3.1.1.2.471 A53SS_APBADDR_PMU_CPU1_PMCNTENCLR_EL0 Register
            472. 14.3.1.1.2.472 A53SS_APBADDR_PMU_CPU1_PMINTENSET_EL1 Register
            473. 14.3.1.1.2.473 A53SS_APBADDR_PMU_CPU1_PMINTENCLR_EL1 Register
            474. 14.3.1.1.2.474 A53SS_APBADDR_PMU_CPU1_PMOVSCLR_EL0 Register
            475. 14.3.1.1.2.475 A53SS_APBADDR_PMU_CPU1_PMSWINC_EL0 Register
            476. 14.3.1.1.2.476 A53SS_APBADDR_PMU_CPU1_PMOVSSET_EL0 Register
            477. 14.3.1.1.2.477 A53SS_APBADDR_PMU_CPU1_PMCFGR Register
            478. 14.3.1.1.2.478 A53SS_APBADDR_PMU_CPU1_PMCR_EL0 Register
            479. 14.3.1.1.2.479 A53SS_APBADDR_PMU_CPU1_PMCEID0_EL0 Register
            480. 14.3.1.1.2.480 A53SS_APBADDR_PMU_CPU1_PMCEID1_EL0 Register
            481. 14.3.1.1.2.481 A53SS_APBADDR_PMU_CPU1_PMITCTRL Register
            482. 14.3.1.1.2.482 A53SS_APBADDR_PMU_CPU1_PMDEVAFF0 Register
            483. 14.3.1.1.2.483 A53SS_APBADDR_PMU_CPU1_PMDEVAFF1 Register
            484. 14.3.1.1.2.484 A53SS_APBADDR_PMU_CPU1_PMLAR Register
            485. 14.3.1.1.2.485 A53SS_APBADDR_PMU_CPU1_PMLSR Register
            486. 14.3.1.1.2.486 A53SS_APBADDR_PMU_CPU1_PMAUTHSTATUS Register
            487. 14.3.1.1.2.487 A53SS_APBADDR_PMU_CPU1_PMDEVARCH Register
            488. 14.3.1.1.2.488 A53SS_APBADDR_PMU_CPU1_PMDEVTYPE Register
            489. 14.3.1.1.2.489 A53SS_APBADDR_PMU_CPU1_PMPIDR4 Register
            490. 14.3.1.1.2.490 A53SS_APBADDR_PMU_CPU1_PMPIDR5 Register
            491. 14.3.1.1.2.491 A53SS_APBADDR_PMU_CPU1_PMPIDR6 Register
            492. 14.3.1.1.2.492 A53SS_APBADDR_PMU_CPU1_PMPIDR7 Register
            493. 14.3.1.1.2.493 A53SS_APBADDR_PMU_CPU1_PMPIDR0 Register
            494. 14.3.1.1.2.494 A53SS_APBADDR_PMU_CPU1_PMPIDR1 Register
            495. 14.3.1.1.2.495 A53SS_APBADDR_PMU_CPU1_PMPIDR2 Register
            496. 14.3.1.1.2.496 A53SS_APBADDR_PMU_CPU1_PMPIDR3 Register
            497. 14.3.1.1.2.497 A53SS_APBADDR_PMU_CPU1_PMCIDR0 Register
            498. 14.3.1.1.2.498 A53SS_APBADDR_PMU_CPU1_PMCIDR1 Register
            499. 14.3.1.1.2.499 A53SS_APBADDR_PMU_CPU1_PMCIDR2 Register
            500. 14.3.1.1.2.500 A53SS_APBADDR_PMU_CPU1_PMCIDR3 Register
            501. 14.3.1.1.2.501 A53SS_APBADDR_ETM_CPU1_TRCPRGCTLR Register
            502. 14.3.1.1.2.502 A53SS_APBADDR_ETM_CPU1_TRCSTATR Register
            503. 14.3.1.1.2.503 A53SS_APBADDR_ETM_CPU1_TRCCONFIGR Register
            504. 14.3.1.1.2.504 A53SS_APBADDR_ETM_CPU1_TRCAUXCTLR Register
            505. 14.3.1.1.2.505 A53SS_APBADDR_ETM_CPU1_TRCEVENTCTL0R Register
            506. 14.3.1.1.2.506 A53SS_APBADDR_ETM_CPU1_TRCEVENTCTL1R Register
            507. 14.3.1.1.2.507 A53SS_APBADDR_ETM_CPU1_TRCSTALLCTLR Register
            508. 14.3.1.1.2.508 A53SS_APBADDR_ETM_CPU1_TRCTSCTLR Register
            509. 14.3.1.1.2.509 A53SS_APBADDR_ETM_CPU1_TRCSYNCPR Register
            510. 14.3.1.1.2.510 A53SS_APBADDR_ETM_CPU1_TRCCCCTLR Register
            511. 14.3.1.1.2.511 A53SS_APBADDR_ETM_CPU1_TRCBBCTLR Register
            512. 14.3.1.1.2.512 A53SS_APBADDR_ETM_CPU1_TRCTRACEIDR Register
            513. 14.3.1.1.2.513 A53SS_APBADDR_ETM_CPU1_TRCVICTLR Register
            514. 14.3.1.1.2.514 A53SS_APBADDR_ETM_CPU1_TRCVIIECTLR Register
            515. 14.3.1.1.2.515 A53SS_APBADDR_ETM_CPU1_TRCVISSCTLR Register
            516. 14.3.1.1.2.516 A53SS_APBADDR_ETM_CPU1_TRCSEQEVR0 Register
            517. 14.3.1.1.2.517 A53SS_APBADDR_ETM_CPU1_TRCSEQEVR1 Register
            518. 14.3.1.1.2.518 A53SS_APBADDR_ETM_CPU1_TRCSEQEVR2 Register
            519. 14.3.1.1.2.519 A53SS_APBADDR_ETM_CPU1_TRCSEQRSTEVR Register
            520. 14.3.1.1.2.520 A53SS_APBADDR_ETM_CPU1_TRCSEQSTR Register
            521. 14.3.1.1.2.521 A53SS_APBADDR_ETM_CPU1_TRCEXTINSELR Register
            522. 14.3.1.1.2.522 A53SS_APBADDR_ETM_CPU1_TRCCNTRLDVR0 Register
            523. 14.3.1.1.2.523 A53SS_APBADDR_ETM_CPU1_TRCCNTRLDVR1 Register
            524. 14.3.1.1.2.524 A53SS_APBADDR_ETM_CPU1_TRCCNTCTLR0 Register
            525. 14.3.1.1.2.525 A53SS_APBADDR_ETM_CPU1_TRCCNTCTLR1 Register
            526. 14.3.1.1.2.526 A53SS_APBADDR_ETM_CPU1_TRCCNTVR0 Register
            527. 14.3.1.1.2.527 A53SS_APBADDR_ETM_CPU1_TRCCNTVR1 Register
            528. 14.3.1.1.2.528 A53SS_APBADDR_ETM_CPU1_TRCIDR8 Register
            529. 14.3.1.1.2.529 A53SS_APBADDR_ETM_CPU1_TRCIDR9 Register
            530. 14.3.1.1.2.530 A53SS_APBADDR_ETM_CPU1_TRCIDR10 Register
            531. 14.3.1.1.2.531 A53SS_APBADDR_ETM_CPU1_TRCIDR11 Register
            532. 14.3.1.1.2.532 A53SS_APBADDR_ETM_CPU1_TRCIDR12 Register
            533. 14.3.1.1.2.533 A53SS_APBADDR_ETM_CPU1_TRCIDR13 Register
            534. 14.3.1.1.2.534 A53SS_APBADDR_ETM_CPU1_TRCIMSPEC0 Register
            535. 14.3.1.1.2.535 A53SS_APBADDR_ETM_CPU1_TRCIDR0 Register
            536. 14.3.1.1.2.536 A53SS_APBADDR_ETM_CPU1_TRCIDR1 Register
            537. 14.3.1.1.2.537 A53SS_APBADDR_ETM_CPU1_TRCIDR2 Register
            538. 14.3.1.1.2.538 A53SS_APBADDR_ETM_CPU1_TRCIDR3 Register
            539. 14.3.1.1.2.539 A53SS_APBADDR_ETM_CPU1_TRCIDR4 Register
            540. 14.3.1.1.2.540 A53SS_APBADDR_ETM_CPU1_TRCIDR5 Register
            541. 14.3.1.1.2.541 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR2 Register
            542. 14.3.1.1.2.542 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR3 Register
            543. 14.3.1.1.2.543 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR4 Register
            544. 14.3.1.1.2.544 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR5 Register
            545. 14.3.1.1.2.545 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR6 Register
            546. 14.3.1.1.2.546 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR7 Register
            547. 14.3.1.1.2.547 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR8 Register
            548. 14.3.1.1.2.548 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR9 Register
            549. 14.3.1.1.2.549 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR10 Register
            550. 14.3.1.1.2.550 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR11 Register
            551. 14.3.1.1.2.551 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR12 Register
            552. 14.3.1.1.2.552 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR13 Register
            553. 14.3.1.1.2.553 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR14 Register
            554. 14.3.1.1.2.554 A53SS_APBADDR_ETM_CPU1_TRCRSCTLR15 Register
            555. 14.3.1.1.2.555 A53SS_APBADDR_ETM_CPU1_TRCSSCCR0 Register
            556. 14.3.1.1.2.556 A53SS_APBADDR_ETM_CPU1_TRCSSCSR0 Register
            557. 14.3.1.1.2.557 A53SS_APBADDR_ETM_CPU1_TRCOSLAR Register
            558. 14.3.1.1.2.558 A53SS_APBADDR_ETM_CPU1_TRCOSLSR Register
            559. 14.3.1.1.2.559 A53SS_APBADDR_ETM_CPU1_TRCPDCR Register
            560. 14.3.1.1.2.560 A53SS_APBADDR_ETM_CPU1_TRCPDSR Register
            561. 14.3.1.1.2.561 A53SS_APBADDR_ETM_CPU1_TRCACVR0_31_0 Register
            562. 14.3.1.1.2.562 A53SS_APBADDR_ETM_CPU1_TRCACVR0_63_32 Register
            563. 14.3.1.1.2.563 A53SS_APBADDR_ETM_CPU1_TRCACVR1_31_0 Register
            564. 14.3.1.1.2.564 A53SS_APBADDR_ETM_CPU1_TRCACVR1_63_32 Register
            565. 14.3.1.1.2.565 A53SS_APBADDR_ETM_CPU1_TRCACVR2_31_0 Register
            566. 14.3.1.1.2.566 A53SS_APBADDR_ETM_CPU1_TRCACVR2_63_32 Register
            567. 14.3.1.1.2.567 A53SS_APBADDR_ETM_CPU1_TRCACVR3_31_0 Register
            568. 14.3.1.1.2.568 A53SS_APBADDR_ETM_CPU1_TRCACVR3_63_32 Register
            569. 14.3.1.1.2.569 A53SS_APBADDR_ETM_CPU1_TRCACVR4_31_0 Register
            570. 14.3.1.1.2.570 A53SS_APBADDR_ETM_CPU1_TRCACVR4_63_32 Register
            571. 14.3.1.1.2.571 A53SS_APBADDR_ETM_CPU1_TRCACVR5_31_0 Register
            572. 14.3.1.1.2.572 A53SS_APBADDR_ETM_CPU1_TRCACVR5_63_32 Register
            573. 14.3.1.1.2.573 A53SS_APBADDR_ETM_CPU1_TRCACVR6_31_0 Register
            574. 14.3.1.1.2.574 A53SS_APBADDR_ETM_CPU1_TRCACVR6_63_32 Register
            575. 14.3.1.1.2.575 A53SS_APBADDR_ETM_CPU1_TRCACVR7_31_0 Register
            576. 14.3.1.1.2.576 A53SS_APBADDR_ETM_CPU1_TRCACVR7_63_32 Register
            577. 14.3.1.1.2.577 A53SS_APBADDR_ETM_CPU1_TRCACATR0 Register
            578. 14.3.1.1.2.578 A53SS_APBADDR_ETM_CPU1_TRCACATR1 Register
            579. 14.3.1.1.2.579 A53SS_APBADDR_ETM_CPU1_TRCACATR2 Register
            580. 14.3.1.1.2.580 A53SS_APBADDR_ETM_CPU1_TRCACATR3 Register
            581. 14.3.1.1.2.581 A53SS_APBADDR_ETM_CPU1_TRCACATR4 Register
            582. 14.3.1.1.2.582 A53SS_APBADDR_ETM_CPU1_TRCACATR5 Register
            583. 14.3.1.1.2.583 A53SS_APBADDR_ETM_CPU1_TRCACATR6 Register
            584. 14.3.1.1.2.584 A53SS_APBADDR_ETM_CPU1_TRCACATR7 Register
            585. 14.3.1.1.2.585 A53SS_APBADDR_ETM_CPU1_TRCCIDCVR0 Register
            586. 14.3.1.1.2.586 A53SS_APBADDR_ETM_CPU1_TRCVMIDCVR0 Register
            587. 14.3.1.1.2.587 A53SS_APBADDR_ETM_CPU1_TRCCIDCCTLR0 Register
            588. 14.3.1.1.2.588 A53SS_APBADDR_ETM_CPU1_TRCITATBIDR Register
            589. 14.3.1.1.2.589 A53SS_APBADDR_ETM_CPU1_TRCITIDATAR Register
            590. 14.3.1.1.2.590 A53SS_APBADDR_ETM_CPU1_TRCITIATBINR Register
            591. 14.3.1.1.2.591 A53SS_APBADDR_ETM_CPU1_TRCITIATBOUTR Register
            592. 14.3.1.1.2.592 A53SS_APBADDR_ETM_CPU1_TRCITCTRL Register
            593. 14.3.1.1.2.593 A53SS_APBADDR_ETM_CPU1_TRCCLAIMSET Register
            594. 14.3.1.1.2.594 A53SS_APBADDR_ETM_CPU1_TRCCLAIMCLR Register
            595. 14.3.1.1.2.595 A53SS_APBADDR_ETM_CPU1_TRCDEVAFF0 Register
            596. 14.3.1.1.2.596 A53SS_APBADDR_ETM_CPU1_TRCDEVAFF1 Register
            597. 14.3.1.1.2.597 A53SS_APBADDR_ETM_CPU1_TRCLAR Register
            598. 14.3.1.1.2.598 A53SS_APBADDR_ETM_CPU1_TRCLSR Register
            599. 14.3.1.1.2.599 A53SS_APBADDR_ETM_CPU1_TRCAUTHSTATUS Register
            600. 14.3.1.1.2.600 A53SS_APBADDR_ETM_CPU1_TRCDEVARCH Register
            601. 14.3.1.1.2.601 A53SS_APBADDR_ETM_CPU1_TRCDEVID Register
            602. 14.3.1.1.2.602 A53SS_APBADDR_ETM_CPU1_TRCDEVTYPE Register
            603. 14.3.1.1.2.603 A53SS_APBADDR_ETM_CPU1_TRCPIDR4 Register
            604. 14.3.1.1.2.604 A53SS_APBADDR_ETM_CPU1_TRCPIDR5 Register
            605. 14.3.1.1.2.605 A53SS_APBADDR_ETM_CPU1_TRCPIDR6 Register
            606. 14.3.1.1.2.606 A53SS_APBADDR_ETM_CPU1_TRCPIDR7 Register
            607. 14.3.1.1.2.607 A53SS_APBADDR_ETM_CPU1_TRCPIDR0 Register
            608. 14.3.1.1.2.608 A53SS_APBADDR_ETM_CPU1_TRCPIDR1 Register
            609. 14.3.1.1.2.609 A53SS_APBADDR_ETM_CPU1_TRCPIDR2 Register
            610. 14.3.1.1.2.610 A53SS_APBADDR_ETM_CPU1_TRCPIDR3 Register
            611. 14.3.1.1.2.611 A53SS_APBADDR_ETM_CPU1_TRCCIDR0 Register
            612. 14.3.1.1.2.612 A53SS_APBADDR_ETM_CPU1_TRCCIDR1 Register
            613. 14.3.1.1.2.613 A53SS_APBADDR_ETM_CPU1_TRCCIDR2 Register
            614. 14.3.1.1.2.614 A53SS_APBADDR_ETM_CPU1_TRCCIDR3 Register
            615. 14.3.1.1.2.615 A53SS_APBADDR_CTI_CPU1_CTICONTROL Register
            616. 14.3.1.1.2.616 A53SS_APBADDR_CTI_CPU1_CTIINTACK Register
            617. 14.3.1.1.2.617 A53SS_APBADDR_CTI_CPU1_CTIAPPSET Register
            618. 14.3.1.1.2.618 A53SS_APBADDR_CTI_CPU1_CTIAPPCLEAR Register
            619. 14.3.1.1.2.619 A53SS_APBADDR_CTI_CPU1_CTIAPPPULSE Register
            620. 14.3.1.1.2.620 A53SS_APBADDR_CTI_CPU1_CTIINEN0 Register
            621. 14.3.1.1.2.621 A53SS_APBADDR_CTI_CPU1_CTIINEN1 Register
            622. 14.3.1.1.2.622 A53SS_APBADDR_CTI_CPU1_CTIINEN2 Register
            623. 14.3.1.1.2.623 A53SS_APBADDR_CTI_CPU1_CTIINEN3 Register
            624. 14.3.1.1.2.624 A53SS_APBADDR_CTI_CPU1_CTIINEN4 Register
            625. 14.3.1.1.2.625 A53SS_APBADDR_CTI_CPU1_CTIINEN5 Register
            626. 14.3.1.1.2.626 A53SS_APBADDR_CTI_CPU1_CTIINEN6 Register
            627. 14.3.1.1.2.627 A53SS_APBADDR_CTI_CPU1_CTIINEN7 Register
            628. 14.3.1.1.2.628 A53SS_APBADDR_CTI_CPU1_CTIOUTEN0 Register
            629. 14.3.1.1.2.629 A53SS_APBADDR_CTI_CPU1_CTIOUTEN1 Register
            630. 14.3.1.1.2.630 A53SS_APBADDR_CTI_CPU1_CTIOUTEN2 Register
            631. 14.3.1.1.2.631 A53SS_APBADDR_CTI_CPU1_CTIOUTEN3 Register
            632. 14.3.1.1.2.632 A53SS_APBADDR_CTI_CPU1_CTIOUTEN4 Register
            633. 14.3.1.1.2.633 A53SS_APBADDR_CTI_CPU1_CTIOUTEN5 Register
            634. 14.3.1.1.2.634 A53SS_APBADDR_CTI_CPU1_CTIOUTEN6 Register
            635. 14.3.1.1.2.635 A53SS_APBADDR_CTI_CPU1_CTIOUTEN7 Register
            636. 14.3.1.1.2.636 A53SS_APBADDR_CTI_CPU1_CTITRIGINSTATUS Register
            637. 14.3.1.1.2.637 A53SS_APBADDR_CTI_CPU1_CTITRIGOUTSTATUS Register
            638. 14.3.1.1.2.638 A53SS_APBADDR_CTI_CPU1_CTICHINSTATUS Register
            639. 14.3.1.1.2.639 A53SS_APBADDR_CTI_CPU1_CTICHOUTSTATUS Register
            640. 14.3.1.1.2.640 A53SS_APBADDR_CTI_CPU1_CTIGATE Register
            641. 14.3.1.1.2.641 A53SS_APBADDR_CTI_CPU1_ASICCTL Register
            642. 14.3.1.1.2.642 A53SS_APBADDR_CTI_CPU1_CTIITCTRL Register
            643. 14.3.1.1.2.643 A53SS_APBADDR_CTI_CPU1_CTICLAIMSET Register
            644. 14.3.1.1.2.644 A53SS_APBADDR_CTI_CPU1_CTICLAIMCLR Register
            645. 14.3.1.1.2.645 A53SS_APBADDR_CTI_CPU1_CTIDEVAFF0 Register
            646. 14.3.1.1.2.646 A53SS_APBADDR_CTI_CPU1_CTIDEVAFF1 Register
            647. 14.3.1.1.2.647 A53SS_APBADDR_CTI_CPU1_CTILAR Register
            648. 14.3.1.1.2.648 A53SS_APBADDR_CTI_CPU1_CTILSR Register
            649. 14.3.1.1.2.649 A53SS_APBADDR_CTI_CPU1_CTIAUTHSTATUS Register
            650. 14.3.1.1.2.650 A53SS_APBADDR_CTI_CPU1_CTIDEVARCH Register
            651. 14.3.1.1.2.651 A53SS_APBADDR_CTI_CPU1_CTIDEVID2 Register
            652. 14.3.1.1.2.652 A53SS_APBADDR_CTI_CPU1_CTIDEVID1 Register
            653. 14.3.1.1.2.653 A53SS_APBADDR_CTI_CPU1_CTIDEVID Register
            654. 14.3.1.1.2.654 A53SS_APBADDR_CTI_CPU1_CTIDEVTYPE Register
            655. 14.3.1.1.2.655 A53SS_APBADDR_CTI_CPU1_CTIPIDR4 Register
            656. 14.3.1.1.2.656 A53SS_APBADDR_CTI_CPU1_CTIPIDR5 Register
            657. 14.3.1.1.2.657 A53SS_APBADDR_CTI_CPU1_CTIPIDR6 Register
            658. 14.3.1.1.2.658 A53SS_APBADDR_CTI_CPU1_CTIPIDR7 Register
            659. 14.3.1.1.2.659 A53SS_APBADDR_CTI_CPU1_CTIPIDR0 Register
            660. 14.3.1.1.2.660 A53SS_APBADDR_CTI_CPU1_CTIPIDR1 Register
            661. 14.3.1.1.2.661 A53SS_APBADDR_CTI_CPU1_CTIPIDR2 Register
            662. 14.3.1.1.2.662 A53SS_APBADDR_CTI_CPU1_CTIPIDR3 Register
            663. 14.3.1.1.2.663 A53SS_APBADDR_CTI_CPU1_CTICIDR0 Register
            664. 14.3.1.1.2.664 A53SS_APBADDR_CTI_CPU1_CTICIDR1 Register
            665. 14.3.1.1.2.665 A53SS_APBADDR_CTI_CPU1_CTICIDR2 Register
            666. 14.3.1.1.2.666 A53SS_APBADDR_CTI_CPU1_CTICIDR3 Register
      2. 14.3.2 M4FSS Registers
        1. 14.3.2.1 M4FSS_RAT_0 Registers
          1. 14.3.2.1.1  M4FSS_RAT_0 Summary Table
          2. 14.3.2.1.2  RAT_PID Register
          3. 14.3.2.1.3  RAT_CONFIG Register
          4. 14.3.2.1.4  RAT_REGION_CTRL_j Register
          5. 14.3.2.1.5  RAT_REGION_BASE_j Register
          6. 14.3.2.1.6  RAT_REGION_TRANS_L_j Register
          7. 14.3.2.1.7  RAT_REGION_TRANS_U_j Register
          8. 14.3.2.1.8  RAT_DESTINATION_ID Register
          9. 14.3.2.1.9  RAT_EXCEPTION_LOGGING_CONTROL Register
          10. 14.3.2.1.10 RAT_EXCEPTION_LOGGING_HEADER0 Register
          11. 14.3.2.1.11 RAT_EXCEPTION_LOGGING_HEADER1 Register
          12. 14.3.2.1.12 RAT_EXCEPTION_LOGGING_DATA0 Register
          13. 14.3.2.1.13 RAT_EXCEPTION_LOGGING_DATA1 Register
          14. 14.3.2.1.14 RAT_EXCEPTION_LOGGING_DATA2 Register
          15. 14.3.2.1.15 RAT_EXCEPTION_LOGGING_DATA3 Register
          16. 14.3.2.1.16 RAT_EXCEPTION_PEND_SET Register
          17. 14.3.2.1.17 RAT_EXCEPTION_PEND_CLEAR Register
          18. 14.3.2.1.18 RAT_EXCEPTION_ENABLE_SET Register
          19. 14.3.2.1.19 RAT_EXCEPTION_ENABLE_CLEAR Register
          20. 14.3.2.1.20 RAT_EOI_REG Register
        2. 14.3.2.2 M4FSS_IRAM_0 Registers
          1. 14.3.2.2.1 M4FSS_IRAM_0 Summary Table
          2. 14.3.2.2.2 M4FSS_IRAM_0_BLAZAR_IRAM_RAM_REG_j Register
        3. 14.3.2.3 M4FSS_DRAM_0
          1. 14.3.2.3.1 M4FSS_DRAM_0 Summaries
            1.         6058
          2. 14.3.2.3.2 M4FSS_DRAM_0 Registers
            1. 14.3.2.3.2.1 M4FSS_DRAM_0_IDRAM_SLV_RAM_RAM_REG_j Register
        4. 14.3.2.4 M4FSS_ECC_AGGR_0
          1. 14.3.2.4.1 M4FSS_ECC_AGGR_0 Summaries
            1.         6063
          2. 14.3.2.4.2 M4FSS_ECC_AGGR_0 Registers
            1. 14.3.2.4.2.1  ECC_AGGR_REV Register
            2. 14.3.2.4.2.2  ECC_AGGR_VECTOR Register
            3. 14.3.2.4.2.3  ECC_AGGR_STAT Register
            4. 14.3.2.4.2.4  ECC_AGGR_RESERVED_SVBUS_j Register
            5. 14.3.2.4.2.5  ECC_AGGR_SEC_EOI_REG Register
            6. 14.3.2.4.2.6  ECC_AGGR_SEC_STATUS_REG0 Register
            7. 14.3.2.4.2.7  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            8. 14.3.2.4.2.8  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            9. 14.3.2.4.2.9  ECC_AGGR_DED_EOI_REG Register
            10. 14.3.2.4.2.10 ECC_AGGR_DED_STATUS_REG0 Register
            11. 14.3.2.4.2.11 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            12. 14.3.2.4.2.12 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            13. 14.3.2.4.2.13 ECC_AGGR_AGGR_ENABLE_SET Register
            14. 14.3.2.4.2.14 ECC_AGGR_AGGR_ENABLE_CLR Register
            15. 14.3.2.4.2.15 ECC_AGGR_AGGR_STATUS_SET Register
            16. 14.3.2.4.2.16 ECC_AGGR_AGGR_STATUS_CLR Register
      3. 14.3.3 R5FSS Registers
        1. 14.3.3.1 R5FSS_COMMON0
          1. 14.3.3.1.1 R5FSS_COMMON0 Summaries
            1.         6084
            2.         6085
            3.         6086
          2. 14.3.3.1.2 R5FSS_COMMON0 Registers
            1. 14.3.3.1.2.1  ECC_AGGR_REV Register
            2. 14.3.3.1.2.2  ECC_AGGR_VECTOR Register
            3. 14.3.3.1.2.3  ECC_AGGR_STAT Register
            4. 14.3.3.1.2.4  ECC_AGGR_RESERVED_SVBUS_j Register
            5. 14.3.3.1.2.5  ECC_AGGR_SEC_EOI_REG Register
            6. 14.3.3.1.2.6  ECC_AGGR_SEC_STATUS_REG0 Register
            7. 14.3.3.1.2.7  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            8. 14.3.3.1.2.8  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            9. 14.3.3.1.2.9  ECC_AGGR_DED_EOI_REG Register
            10. 14.3.3.1.2.10 ECC_AGGR_DED_STATUS_REG0 Register
            11. 14.3.3.1.2.11 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            12. 14.3.3.1.2.12 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            13. 14.3.3.1.2.13 ECC_AGGR_AGGR_ENABLE_SET Register
            14. 14.3.3.1.2.14 ECC_AGGR_AGGR_ENABLE_CLR Register
            15. 14.3.3.1.2.15 ECC_AGGR_AGGR_STATUS_SET Register
            16. 14.3.3.1.2.16 ECC_AGGR_AGGR_STATUS_CLR Register
            17. 14.3.3.1.2.17 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_DISABLE_CR Register
            18. 14.3.3.1.2.18 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_CPU0_EVNT_BUS_SB_ERR_CNT_STATUS Register
            19. 14.3.3.1.2.19 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_CPU1_EVNT_BUS_SB_ERR_CNT_STATUS Register
            20. 14.3.3.1.2.20 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_CPU0_EVNT_BUS_MB_ERR_CNT_STATUS Register
            21. 14.3.3.1.2.21 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_CPU1_EVNT_BUS_MB_ERR_CNT_STATUS Register
            22. 14.3.3.1.2.22 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_EVNT_BUS_ESM_STATUS Register
            23. 14.3.3.1.2.23 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_EVNT_BUS_ESM_SET Register
            24. 14.3.3.1.2.24 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_EVNT_BUS_ESM_CLR Register
            25. 14.3.3.1.2.25 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_EVNT_BUS_MASK_ESM_SET Register
            26. 14.3.3.1.2.26 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_EVNT_BUS_MASK_ESM_CLR Register
            27. 14.3.3.1.2.27 R5FSS_COMMON0_EVNT_BUS_VBUSP_MMRS_PULSAR_EVT_BUS_REVID Register
            28. 14.3.3.1.2.28 ECC_AGGR_REV Register
            29. 14.3.3.1.2.29 ECC_AGGR_VECTOR Register
            30. 14.3.3.1.2.30 ECC_AGGR_STAT Register
            31. 14.3.3.1.2.31 ECC_AGGR_RESERVED_SVBUS_j Register
            32. 14.3.3.1.2.32 ECC_AGGR_SEC_EOI_REG Register
            33. 14.3.3.1.2.33 ECC_AGGR_SEC_STATUS_REG0 Register
            34. 14.3.3.1.2.34 ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            35. 14.3.3.1.2.35 ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            36. 14.3.3.1.2.36 ECC_AGGR_DED_EOI_REG Register
            37. 14.3.3.1.2.37 ECC_AGGR_DED_STATUS_REG0 Register
            38. 14.3.3.1.2.38 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            39. 14.3.3.1.2.39 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            40. 14.3.3.1.2.40 ECC_AGGR_AGGR_ENABLE_SET Register
            41. 14.3.3.1.2.41 ECC_AGGR_AGGR_ENABLE_CLR Register
            42. 14.3.3.1.2.42 ECC_AGGR_AGGR_STATUS_SET Register
            43. 14.3.3.1.2.43 ECC_AGGR_AGGR_STATUS_CLR Register
      4. 14.3.4 R5FSS_VIM Registers
        1. 14.3.4.1 R5FSS_VIM Registers
      5. 14.3.5 R5FSS_RAT
        1. 14.3.5.1 R5FSS_RAT Registers
      6. 14.3.6 PRUSS Registers
        1. 14.3.6.1 PRU_ICSSG Registers
          1. 14.3.6.1.1  PRU_ICSSG PRU_CTRL, RTU_PRU_CTRL, and TX_PRU_CTRL Registers
          2. 14.3.6.1.2  PRU_ICSSG PRU_DEBUG, RTU_PRU_DEBUG, and TX_PRU_DEBUG Registers
          3. 14.3.6.1.3  PRU_ICSSG_ECC_AGGR Registers
          4. 14.3.6.1.4  PRU_ICSSG_DDRAM Registers
          5. 14.3.6.1.5  PRU_ICSSG_CFG Registers
          6. 14.3.6.1.6  PRU_ECAP_ECAP0 Registers
          7. 14.3.6.1.7  PRU_ICSS_INTC_INTC Registers
          8. 14.3.6.1.8  PRU_UART Registers
            1.         6145
          9. 14.3.6.1.9  ICSS_G_PR1_ICSS_UART_UART_SLV_RBR Register
          10. 14.3.6.1.10 ICSS_G_PR1_ICSS_UART_UART_SLV_IER Register
          11. 14.3.6.1.11 ICSS_G_PR1_ICSS_UART_UART_SLV_IIR Register
          12. 14.3.6.1.12 ICSS_G_PR1_ICSS_UART_UART_SLV_LCR Register
          13. 14.3.6.1.13 ICSS_G_PR1_ICSS_UART_UART_SLV_MCR Register
          14. 14.3.6.1.14 ICSS_G_PR1_ICSS_UART_UART_SLV_LSR Register
          15. 14.3.6.1.15 ICSS_G_PR1_ICSS_UART_UART_SLV_MSR Register
          16. 14.3.6.1.16 ICSS_G_PR1_ICSS_UART_UART_SLV_SCR Register
          17. 14.3.6.1.17 ICSS_G_PR1_ICSS_UART_UART_SLV_DLL Register
          18. 14.3.6.1.18 ICSS_G_PR1_ICSS_UART_UART_SLV_DLH Register
          19. 14.3.6.1.19 ICSS_G_PR1_ICSS_UART_UART_SLV_REVID1 Register
          20. 14.3.6.1.20 ICSS_G_PR1_ICSS_UART_UART_SLV_PWREMU_MGMT Register
          21. 14.3.6.1.21 ICSS_G_PR1_ICSS_UART_UART_SLV_MDR Register
          22. 14.3.6.1.22 ICSS_G_PR1_ICSS_UART_UART_SLV_THR Register
          23. 14.3.6.1.23 ICSS_G_PR1_ICSS_UART_UART_SLV_FCR Register
          24. 14.3.6.1.24 ICSS_G_PR1_ICSS_UART_UART_SLV_REVID2 Register
          25. 14.3.6.1.25 PRU_IEP_IEP Registers
          26. 14.3.6.1.26 PRU_MDIO_MDIO Registers
          27. 14.3.6.1.27 PRU_MII_RT_MII_RT Registers
          28. 14.3.6.1.28 PRU_MII_G_RT_MII_G_RT Registers
          29. 14.3.6.1.29 PRU_ICSSG_PA_STAT Registers
          30. 14.3.6.1.30 PRU_ICSSG_PA_STAT_QSTAT Registers
          31. 14.3.6.1.31 PRU_ICSSG_PA_STAT_CSTAT Registers
          32. 14.3.6.1.32 PRU_PROT_PROTECT Registers
          33. 14.3.6.1.33 PRU_RAT_SLICE_RAT_SLICE Registers
          34. 14.3.6.1.34 PRU_TASKS_MGR_TASKS_MGR_PRU_RTU_TX Registers
          35. 14.3.6.1.35 PRU_ICSSG_RAM Registers
    4. 14.4  Interprocessor Communication Registers
      1. 14.4.1 MAILBOX_MAILBOX_CLUSTER_0
        1. 14.4.1.1 MAILBOX_MAILBOX_CLUSTER_0 Summaries
          1.        6176
        2. 14.4.1.2 MAILBOX_MAILBOX_CLUSTER_0 Registers
          1. 14.4.1.2.1  MAILBOX_REVISION Register
          2. 14.4.1.2.2  MAILBOX_SYSCONFIG Register
          3. 14.4.1.2.3  MAILBOX_MESSAGE_j Register
          4. 14.4.1.2.4  MAILBOX_FIFO_STATUS_j Register
          5. 14.4.1.2.5  MAILBOX_MSG_STATUS_j Register
          6. 14.4.1.2.6  MAILBOX_IRQ_EOI Register
          7. 14.4.1.2.7  MAILBOX_USER_IRQ_STATUS_RAW_j Register
          8. 14.4.1.2.8  MAILBOX_USER_IRQ_STATUS_CLR_j Register
          9. 14.4.1.2.9  MAILBOX_USER_IRQ_ENABLE_SET_j Register
          10. 14.4.1.2.10 MAILBOX_USER_IRQ_ENABLE_CLR_j Register
      2. 14.4.2 MAILBOX_MAILBOX_CLUSTER_1
        1. 14.4.2.1 MAILBOX_MAILBOX_CLUSTER_1 Summaries
          1.        6190
        2. 14.4.2.2 MAILBOX_MAILBOX_CLUSTER_1 Registers
          1. 14.4.2.2.1  MAILBOX_REVISION Register
          2. 14.4.2.2.2  MAILBOX_SYSCONFIG Register
          3. 14.4.2.2.3  MAILBOX_MESSAGE_j Register
          4. 14.4.2.2.4  MAILBOX_FIFO_STATUS_j Register
          5. 14.4.2.2.5  MAILBOX_MSG_STATUS_j Register
          6. 14.4.2.2.6  MAILBOX_IRQ_EOI Register
          7. 14.4.2.2.7  MAILBOX_USER_IRQ_STATUS_RAW_j Register
          8. 14.4.2.2.8  MAILBOX_USER_IRQ_STATUS_CLR_j Register
          9. 14.4.2.2.9  MAILBOX_USER_IRQ_ENABLE_SET_j Register
          10. 14.4.2.2.10 MAILBOX_USER_IRQ_ENABLE_CLR_j Register
      3. 14.4.3 MAILBOX_MAILBOX_CLUSTER_2
        1. 14.4.3.1 MAILBOX_MAILBOX_CLUSTER_2 Summaries
          1.        6204
        2. 14.4.3.2 MAILBOX_MAILBOX_CLUSTER_2 Registers
          1. 14.4.3.2.1  MAILBOX_REVISION Register
          2. 14.4.3.2.2  MAILBOX_SYSCONFIG Register
          3. 14.4.3.2.3  MAILBOX_MESSAGE_j Register
          4. 14.4.3.2.4  MAILBOX_FIFO_STATUS_j Register
          5. 14.4.3.2.5  MAILBOX_MSG_STATUS_j Register
          6. 14.4.3.2.6  MAILBOX_IRQ_EOI Register
          7. 14.4.3.2.7  MAILBOX_USER_IRQ_STATUS_RAW_j Register
          8. 14.4.3.2.8  MAILBOX_USER_IRQ_STATUS_CLR_j Register
          9. 14.4.3.2.9  MAILBOX_USER_IRQ_ENABLE_SET_j Register
          10. 14.4.3.2.10 MAILBOX_USER_IRQ_ENABLE_CLR_j Register
      4. 14.4.4 MAILBOX_MAILBOX_CLUSTER_3
        1. 14.4.4.1 MAILBOX_MAILBOX_CLUSTER_3 Summaries
          1.        6218
        2. 14.4.4.2 MAILBOX_MAILBOX_CLUSTER_3 Registers
          1. 14.4.4.2.1  MAILBOX_REVISION Register
          2. 14.4.4.2.2  MAILBOX_SYSCONFIG Register
          3. 14.4.4.2.3  MAILBOX_MESSAGE_j Register
          4. 14.4.4.2.4  MAILBOX_FIFO_STATUS_j Register
          5. 14.4.4.2.5  MAILBOX_MSG_STATUS_j Register
          6. 14.4.4.2.6  MAILBOX_IRQ_EOI Register
          7. 14.4.4.2.7  MAILBOX_USER_IRQ_STATUS_RAW_j Register
          8. 14.4.4.2.8  MAILBOX_USER_IRQ_STATUS_CLR_j Register
          9. 14.4.4.2.9  MAILBOX_USER_IRQ_ENABLE_SET_j Register
          10. 14.4.4.2.10 MAILBOX_USER_IRQ_ENABLE_CLR_j Register
      5. 14.4.5 MAILBOX_MAILBOX_CLUSTER_4
        1. 14.4.5.1 MAILBOX_MAILBOX_CLUSTER_4 Summaries
          1.        6232
        2. 14.4.5.2 MAILBOX_MAILBOX_CLUSTER_4 Registers
          1. 14.4.5.2.1  MAILBOX_REVISION Register
          2. 14.4.5.2.2  MAILBOX_SYSCONFIG Register
          3. 14.4.5.2.3  MAILBOX_MESSAGE_j Register
          4. 14.4.5.2.4  MAILBOX_FIFO_STATUS_j Register
          5. 14.4.5.2.5  MAILBOX_MSG_STATUS_j Register
          6. 14.4.5.2.6  MAILBOX_IRQ_EOI Register
          7. 14.4.5.2.7  MAILBOX_USER_IRQ_STATUS_RAW_j Register
          8. 14.4.5.2.8  MAILBOX_USER_IRQ_STATUS_CLR_j Register
          9. 14.4.5.2.9  MAILBOX_USER_IRQ_ENABLE_SET_j Register
          10. 14.4.5.2.10 MAILBOX_USER_IRQ_ENABLE_CLR_j Register
      6. 14.4.6 MAILBOX_MAILBOX_CLUSTER_5
        1. 14.4.6.1 MAILBOX_MAILBOX_CLUSTER_5 Summaries
          1.        6246
        2. 14.4.6.2 MAILBOX_MAILBOX_CLUSTER_5 Registers
          1. 14.4.6.2.1  MAILBOX_REVISION Register
          2. 14.4.6.2.2  MAILBOX_SYSCONFIG Register
          3. 14.4.6.2.3  MAILBOX_MESSAGE_j Register
          4. 14.4.6.2.4  MAILBOX_FIFO_STATUS_j Register
          5. 14.4.6.2.5  MAILBOX_MSG_STATUS_j Register
          6. 14.4.6.2.6  MAILBOX_IRQ_EOI Register
          7. 14.4.6.2.7  MAILBOX_USER_IRQ_STATUS_RAW_j Register
          8. 14.4.6.2.8  MAILBOX_USER_IRQ_STATUS_CLR_j Register
          9. 14.4.6.2.9  MAILBOX_USER_IRQ_ENABLE_SET_j Register
          10. 14.4.6.2.10 MAILBOX_USER_IRQ_ENABLE_CLR_j Register
      7. 14.4.7 MAILBOX_MAILBOX_CLUSTER_6
        1. 14.4.7.1 MAILBOX_MAILBOX_CLUSTER_6 Summaries
          1.        6260
        2. 14.4.7.2 MAILBOX_MAILBOX_CLUSTER_6 Registers
          1. 14.4.7.2.1  MAILBOX_REVISION Register
          2. 14.4.7.2.2  MAILBOX_SYSCONFIG Register
          3. 14.4.7.2.3  MAILBOX_MESSAGE_j Register
          4. 14.4.7.2.4  MAILBOX_FIFO_STATUS_j Register
          5. 14.4.7.2.5  MAILBOX_MSG_STATUS_j Register
          6. 14.4.7.2.6  MAILBOX_IRQ_EOI Register
          7. 14.4.7.2.7  MAILBOX_USER_IRQ_STATUS_RAW_j Register
          8. 14.4.7.2.8  MAILBOX_USER_IRQ_STATUS_CLR_j Register
          9. 14.4.7.2.9  MAILBOX_USER_IRQ_ENABLE_SET_j Register
          10. 14.4.7.2.10 MAILBOX_USER_IRQ_ENABLE_CLR_j Register
      8. 14.4.8 MAILBOX_MAILBOX_CLUSTER_7
        1. 14.4.8.1 MAILBOX_MAILBOX_CLUSTER_7 Summaries
          1.        6274
        2. 14.4.8.2 MAILBOX_MAILBOX_CLUSTER_7 Registers
          1. 14.4.8.2.1  MAILBOX_REVISION Register
          2. 14.4.8.2.2  MAILBOX_SYSCONFIG Register
          3. 14.4.8.2.3  MAILBOX_MESSAGE_j Register
          4. 14.4.8.2.4  MAILBOX_FIFO_STATUS_j Register
          5. 14.4.8.2.5  MAILBOX_MSG_STATUS_j Register
          6. 14.4.8.2.6  MAILBOX_IRQ_EOI Register
          7. 14.4.8.2.7  MAILBOX_USER_IRQ_STATUS_RAW_j Register
          8. 14.4.8.2.8  MAILBOX_USER_IRQ_STATUS_CLR_j Register
          9. 14.4.8.2.9  MAILBOX_USER_IRQ_ENABLE_SET_j Register
          10. 14.4.8.2.10 MAILBOX_USER_IRQ_ENABLE_CLR_j Register
      9. 14.4.9 SPINLOCK
        1. 14.4.9.1 SPINLOCK Summaries
          1.        6288
        2. 14.4.9.2 SPINLOCK Registers
          1. 14.4.9.2.1 SPINLOCK_REVISION Register
          2. 14.4.9.2.2 SPINLOCK_SYSCONFIG Register
          3. 14.4.9.2.3 SPINLOCK_SYSTATUS Register
          4. 14.4.9.2.4 SPINLOCK_LOCK_REG_j Register
    5. 14.5  Memory Controller Registers
      1. 14.5.1 ddr16ss
        1. 14.5.1.1 ddr16ss Summaries
          1.        6297
          2.        6298
        2. 14.5.1.2 ddr16ss Registers
          1. 14.5.1.2.1    EMIF_SSCFG_SS_ID_REV_REG Register
          2. 14.5.1.2.2    EMIF_SSCFG_SS_CTL_REG Register
          3. 14.5.1.2.3    EMIF_SSCFG_V2A_CTL_REG Register
          4. 14.5.1.2.4    EMIF_SSCFG_V2A_R1_MAT_REG Register
          5. 14.5.1.2.5    EMIF_SSCFG_V2A_R2_MAT_REG Register
          6. 14.5.1.2.6    EMIF_SSCFG_V2A_R3_MAT_REG Register
          7. 14.5.1.2.7    EMIF_SSCFG_V2A_DEF_PRI_MAP_REG Register
          8. 14.5.1.2.8    EMIF_SSCFG_V2A_R1_PRI_MAP_REG Register
          9. 14.5.1.2.9    EMIF_SSCFG_V2A_R2_PRI_MAP_REG Register
          10. 14.5.1.2.10   EMIF_SSCFG_V2A_R3_PRI_MAP_REG Register
          11. 14.5.1.2.11   EMIF_SSCFG_V2A_AERR_LOG1_REG Register
          12. 14.5.1.2.12   EMIF_SSCFG_V2A_AERR_LOG2_REG Register
          13. 14.5.1.2.13   EMIF_SSCFG_V2A_BUS_TO Register
          14. 14.5.1.2.14   EMIF_SSCFG_V2A_INT_RAW_REG Register
          15. 14.5.1.2.15   EMIF_SSCFG_V2A_INT_STAT_REG Register
          16. 14.5.1.2.16   EMIF_SSCFG_V2A_INT_SET_REG Register
          17. 14.5.1.2.17   EMIF_SSCFG_V2A_INT_CLR_REG Register
          18. 14.5.1.2.18   EMIF_SSCFG_V2A_EOI_REG Register
          19. 14.5.1.2.19   EMIF_SSCFG_PERF_CNT_SEL_REG Register
          20. 14.5.1.2.20   EMIF_SSCFG_PERF_CNT1_REG Register
          21. 14.5.1.2.21   EMIF_SSCFG_PERF_CNT2_REG Register
          22. 14.5.1.2.22   EMIF_SSCFG_PERF_CNT3_REG Register
          23. 14.5.1.2.23   EMIF_SSCFG_PERF_CNT4_REG Register
          24. 14.5.1.2.24   EMIF_SSCFG_ECC_CTRL_REG Register
          25. 14.5.1.2.25   EMIF_SSCFG_ECC_RID_INDX_REG Register
          26. 14.5.1.2.26   EMIF_SSCFG_ECC_RID_VAL_REG Register
          27. 14.5.1.2.27   EMIF_SSCFG_ECC_R0_STR_ADDR_REG Register
          28. 14.5.1.2.28   EMIF_SSCFG_ECC_R0_END_ADDR_REG Register
          29. 14.5.1.2.29   EMIF_SSCFG_ECC_R1_STR_ADDR_REG Register
          30. 14.5.1.2.30   EMIF_SSCFG_ECC_R1_END_ADDR_REG Register
          31. 14.5.1.2.31   EMIF_SSCFG_ECC_R2_STR_ADDR_REG Register
          32. 14.5.1.2.32   EMIF_SSCFG_ECC_R2_END_ADDR_REG Register
          33. 14.5.1.2.33   EMIF_SSCFG_ECC_1B_ERR_CNT_REG Register
          34. 14.5.1.2.34   EMIF_SSCFG_ECC_1B_ERR_THRSH_REG Register
          35. 14.5.1.2.35   EMIF_SSCFG_ECC_1B_ERR_ADR_LOG_REG Register
          36. 14.5.1.2.36   EMIF_SSCFG_ECC_1B_ERR_MSK_LOG_REG Register
          37. 14.5.1.2.37   EMIF_SSCFG_ECC_2B_ERR_ADR_LOG_REG Register
          38. 14.5.1.2.38   EMIF_SSCFG_ECC_2B_ERR_MSK_LOG_REG Register
          39. 14.5.1.2.39   EMIF_SSCFG_PHY_TEST_CTRL1_REG Register
          40. 14.5.1.2.40   EMIF_SSCFG_PHY_TEST_CTRL2_REG Register
          41. 14.5.1.2.41   EMIF_SSCFG_PHY_TEST_CTRL3_REG Register
          42. 14.5.1.2.42   EMIF_SSCFG_PHY_TEST_CTRL4_REG Register
          43. 14.5.1.2.43   EMIF_SSCFG_PHY_TEST_CTRL5_REG Register
          44. 14.5.1.2.44   EMIF_SSCFG_PHY_TEST_CTRL6_REG Register
          45. 14.5.1.2.45   EMIF_SSCFG_PHY_TEST_CTRL7_REG Register
          46. 14.5.1.2.46   EMIF_SSCFG_PHY_TEST_CTRL8_REG Register
          47. 14.5.1.2.47   EMIF_SSCFG_PHY_TEST_CTRL9_REG Register
          48. 14.5.1.2.48   EMIF_SSCFG_PHY_TEST_CTRL10_REG Register
          49. 14.5.1.2.49   EMIF_SSCFG_PHY_TEST_STAT1_REG Register
          50. 14.5.1.2.50   EMIF_SSCFG_PHY_TEST_STAT2_REG Register
          51. 14.5.1.2.51   EMIF_CTLCFG_DENALI_CTL_0 Register
          52. 14.5.1.2.52   EMIF_CTLCFG_DENALI_CTL_1 Register
          53. 14.5.1.2.53   EMIF_CTLCFG_DENALI_CTL_2 Register
          54. 14.5.1.2.54   EMIF_CTLCFG_DENALI_CTL_3 Register
          55. 14.5.1.2.55   EMIF_CTLCFG_DENALI_CTL_4 Register
          56. 14.5.1.2.56   EMIF_CTLCFG_DENALI_CTL_5 Register
          57. 14.5.1.2.57   EMIF_CTLCFG_DENALI_CTL_6 Register
          58. 14.5.1.2.58   EMIF_CTLCFG_DENALI_CTL_7 Register
          59. 14.5.1.2.59   EMIF_CTLCFG_DENALI_CTL_8 Register
          60. 14.5.1.2.60   EMIF_CTLCFG_DENALI_CTL_9 Register
          61. 14.5.1.2.61   EMIF_CTLCFG_DENALI_CTL_10 Register
          62. 14.5.1.2.62   EMIF_CTLCFG_DENALI_CTL_11 Register
          63. 14.5.1.2.63   EMIF_CTLCFG_DENALI_CTL_12 Register
          64. 14.5.1.2.64   EMIF_CTLCFG_DENALI_CTL_13 Register
          65. 14.5.1.2.65   EMIF_CTLCFG_DENALI_CTL_14 Register
          66. 14.5.1.2.66   EMIF_CTLCFG_DENALI_CTL_15 Register
          67. 14.5.1.2.67   EMIF_CTLCFG_DENALI_CTL_16 Register
          68. 14.5.1.2.68   EMIF_CTLCFG_DENALI_CTL_17 Register
          69. 14.5.1.2.69   EMIF_CTLCFG_DENALI_CTL_18 Register
          70. 14.5.1.2.70   EMIF_CTLCFG_DENALI_CTL_19 Register
          71. 14.5.1.2.71   EMIF_CTLCFG_DENALI_CTL_20 Register
          72. 14.5.1.2.72   EMIF_CTLCFG_DENALI_CTL_21 Register
          73. 14.5.1.2.73   EMIF_CTLCFG_DENALI_CTL_22 Register
          74. 14.5.1.2.74   EMIF_CTLCFG_DENALI_CTL_23 Register
          75. 14.5.1.2.75   EMIF_CTLCFG_DENALI_CTL_24 Register
          76. 14.5.1.2.76   EMIF_CTLCFG_DENALI_CTL_25 Register
          77. 14.5.1.2.77   EMIF_CTLCFG_DENALI_CTL_26 Register
          78. 14.5.1.2.78   EMIF_CTLCFG_DENALI_CTL_27 Register
          79. 14.5.1.2.79   EMIF_CTLCFG_DENALI_CTL_28 Register
          80. 14.5.1.2.80   EMIF_CTLCFG_DENALI_CTL_29 Register
          81. 14.5.1.2.81   EMIF_CTLCFG_DENALI_CTL_30 Register
          82. 14.5.1.2.82   EMIF_CTLCFG_DENALI_CTL_31 Register
          83. 14.5.1.2.83   EMIF_CTLCFG_DENALI_CTL_32 Register
          84. 14.5.1.2.84   EMIF_CTLCFG_DENALI_CTL_33 Register
          85. 14.5.1.2.85   EMIF_CTLCFG_DENALI_CTL_34 Register
          86. 14.5.1.2.86   EMIF_CTLCFG_DENALI_CTL_35 Register
          87. 14.5.1.2.87   EMIF_CTLCFG_DENALI_CTL_36 Register
          88. 14.5.1.2.88   EMIF_CTLCFG_DENALI_CTL_37 Register
          89. 14.5.1.2.89   EMIF_CTLCFG_DENALI_CTL_38 Register
          90. 14.5.1.2.90   EMIF_CTLCFG_DENALI_CTL_39 Register
          91. 14.5.1.2.91   EMIF_CTLCFG_DENALI_CTL_40 Register
          92. 14.5.1.2.92   EMIF_CTLCFG_DENALI_CTL_41 Register
          93. 14.5.1.2.93   EMIF_CTLCFG_DENALI_CTL_42 Register
          94. 14.5.1.2.94   EMIF_CTLCFG_DENALI_CTL_43 Register
          95. 14.5.1.2.95   EMIF_CTLCFG_DENALI_CTL_44 Register
          96. 14.5.1.2.96   EMIF_CTLCFG_DENALI_CTL_45 Register
          97. 14.5.1.2.97   EMIF_CTLCFG_DENALI_CTL_46 Register
          98. 14.5.1.2.98   EMIF_CTLCFG_DENALI_CTL_47 Register
          99. 14.5.1.2.99   EMIF_CTLCFG_DENALI_CTL_48 Register
          100. 14.5.1.2.100  EMIF_CTLCFG_DENALI_CTL_49 Register
          101. 14.5.1.2.101  EMIF_CTLCFG_DENALI_CTL_50 Register
          102. 14.5.1.2.102  EMIF_CTLCFG_DENALI_CTL_51 Register
          103. 14.5.1.2.103  EMIF_CTLCFG_DENALI_CTL_52 Register
          104. 14.5.1.2.104  EMIF_CTLCFG_DENALI_CTL_53 Register
          105. 14.5.1.2.105  EMIF_CTLCFG_DENALI_CTL_54 Register
          106. 14.5.1.2.106  EMIF_CTLCFG_DENALI_CTL_55 Register
          107. 14.5.1.2.107  EMIF_CTLCFG_DENALI_CTL_56 Register
          108. 14.5.1.2.108  EMIF_CTLCFG_DENALI_CTL_57 Register
          109. 14.5.1.2.109  EMIF_CTLCFG_DENALI_CTL_58 Register
          110. 14.5.1.2.110  EMIF_CTLCFG_DENALI_CTL_59 Register
          111. 14.5.1.2.111  EMIF_CTLCFG_DENALI_CTL_60 Register
          112. 14.5.1.2.112  EMIF_CTLCFG_DENALI_CTL_61 Register
          113. 14.5.1.2.113  EMIF_CTLCFG_DENALI_CTL_62 Register
          114. 14.5.1.2.114  EMIF_CTLCFG_DENALI_CTL_63 Register
          115. 14.5.1.2.115  EMIF_CTLCFG_DENALI_CTL_64 Register
          116. 14.5.1.2.116  EMIF_CTLCFG_DENALI_CTL_65 Register
          117. 14.5.1.2.117  EMIF_CTLCFG_DENALI_CTL_66 Register
          118. 14.5.1.2.118  EMIF_CTLCFG_DENALI_CTL_67 Register
          119. 14.5.1.2.119  EMIF_CTLCFG_DENALI_CTL_68 Register
          120. 14.5.1.2.120  EMIF_CTLCFG_DENALI_CTL_69 Register
          121. 14.5.1.2.121  EMIF_CTLCFG_DENALI_CTL_70 Register
          122. 14.5.1.2.122  EMIF_CTLCFG_DENALI_CTL_71 Register
          123. 14.5.1.2.123  EMIF_CTLCFG_DENALI_CTL_72 Register
          124. 14.5.1.2.124  EMIF_CTLCFG_DENALI_CTL_73 Register
          125. 14.5.1.2.125  EMIF_CTLCFG_DENALI_CTL_74 Register
          126. 14.5.1.2.126  EMIF_CTLCFG_DENALI_CTL_75 Register
          127. 14.5.1.2.127  EMIF_CTLCFG_DENALI_CTL_76 Register
          128. 14.5.1.2.128  EMIF_CTLCFG_DENALI_CTL_77 Register
          129. 14.5.1.2.129  EMIF_CTLCFG_DENALI_CTL_78 Register
          130. 14.5.1.2.130  EMIF_CTLCFG_DENALI_CTL_79 Register
          131. 14.5.1.2.131  EMIF_CTLCFG_DENALI_CTL_80 Register
          132. 14.5.1.2.132  EMIF_CTLCFG_DENALI_CTL_81 Register
          133. 14.5.1.2.133  EMIF_CTLCFG_DENALI_CTL_82 Register
          134. 14.5.1.2.134  EMIF_CTLCFG_DENALI_CTL_83 Register
          135. 14.5.1.2.135  EMIF_CTLCFG_DENALI_CTL_84 Register
          136. 14.5.1.2.136  EMIF_CTLCFG_DENALI_CTL_85 Register
          137. 14.5.1.2.137  EMIF_CTLCFG_DENALI_CTL_86 Register
          138. 14.5.1.2.138  EMIF_CTLCFG_DENALI_CTL_87 Register
          139. 14.5.1.2.139  EMIF_CTLCFG_DENALI_CTL_88 Register
          140. 14.5.1.2.140  EMIF_CTLCFG_DENALI_CTL_89 Register
          141. 14.5.1.2.141  EMIF_CTLCFG_DENALI_CTL_90 Register
          142. 14.5.1.2.142  EMIF_CTLCFG_DENALI_CTL_91 Register
          143. 14.5.1.2.143  EMIF_CTLCFG_DENALI_CTL_92 Register
          144. 14.5.1.2.144  EMIF_CTLCFG_DENALI_CTL_93 Register
          145. 14.5.1.2.145  EMIF_CTLCFG_DENALI_CTL_94 Register
          146. 14.5.1.2.146  EMIF_CTLCFG_DENALI_CTL_95 Register
          147. 14.5.1.2.147  EMIF_CTLCFG_DENALI_CTL_96 Register
          148. 14.5.1.2.148  EMIF_CTLCFG_DENALI_CTL_97 Register
          149. 14.5.1.2.149  EMIF_CTLCFG_DENALI_CTL_98 Register
          150. 14.5.1.2.150  EMIF_CTLCFG_DENALI_CTL_99 Register
          151. 14.5.1.2.151  EMIF_CTLCFG_DENALI_CTL_100 Register
          152. 14.5.1.2.152  EMIF_CTLCFG_DENALI_CTL_101 Register
          153. 14.5.1.2.153  EMIF_CTLCFG_DENALI_CTL_102 Register
          154. 14.5.1.2.154  EMIF_CTLCFG_DENALI_CTL_103 Register
          155. 14.5.1.2.155  EMIF_CTLCFG_DENALI_CTL_104 Register
          156. 14.5.1.2.156  EMIF_CTLCFG_DENALI_CTL_105 Register
          157. 14.5.1.2.157  EMIF_CTLCFG_DENALI_CTL_106 Register
          158. 14.5.1.2.158  EMIF_CTLCFG_DENALI_CTL_107 Register
          159. 14.5.1.2.159  EMIF_CTLCFG_DENALI_CTL_108 Register
          160. 14.5.1.2.160  EMIF_CTLCFG_DENALI_CTL_109 Register
          161. 14.5.1.2.161  EMIF_CTLCFG_DENALI_CTL_110 Register
          162. 14.5.1.2.162  EMIF_CTLCFG_DENALI_CTL_111 Register
          163. 14.5.1.2.163  EMIF_CTLCFG_DENALI_CTL_112 Register
          164. 14.5.1.2.164  EMIF_CTLCFG_DENALI_CTL_113 Register
          165. 14.5.1.2.165  EMIF_CTLCFG_DENALI_CTL_114 Register
          166. 14.5.1.2.166  EMIF_CTLCFG_DENALI_CTL_115 Register
          167. 14.5.1.2.167  EMIF_CTLCFG_DENALI_CTL_116 Register
          168. 14.5.1.2.168  EMIF_CTLCFG_DENALI_CTL_117 Register
          169. 14.5.1.2.169  EMIF_CTLCFG_DENALI_CTL_118 Register
          170. 14.5.1.2.170  EMIF_CTLCFG_DENALI_CTL_119 Register
          171. 14.5.1.2.171  EMIF_CTLCFG_DENALI_CTL_120 Register
          172. 14.5.1.2.172  EMIF_CTLCFG_DENALI_CTL_121 Register
          173. 14.5.1.2.173  EMIF_CTLCFG_DENALI_CTL_122 Register
          174. 14.5.1.2.174  EMIF_CTLCFG_DENALI_CTL_123 Register
          175. 14.5.1.2.175  EMIF_CTLCFG_DENALI_CTL_124 Register
          176. 14.5.1.2.176  EMIF_CTLCFG_DENALI_CTL_125 Register
          177. 14.5.1.2.177  EMIF_CTLCFG_DENALI_CTL_126 Register
          178. 14.5.1.2.178  EMIF_CTLCFG_DENALI_CTL_127 Register
          179. 14.5.1.2.179  EMIF_CTLCFG_DENALI_CTL_128 Register
          180. 14.5.1.2.180  EMIF_CTLCFG_DENALI_CTL_129 Register
          181. 14.5.1.2.181  EMIF_CTLCFG_DENALI_CTL_130 Register
          182. 14.5.1.2.182  EMIF_CTLCFG_DENALI_CTL_131 Register
          183. 14.5.1.2.183  EMIF_CTLCFG_DENALI_CTL_132 Register
          184. 14.5.1.2.184  EMIF_CTLCFG_DENALI_CTL_133 Register
          185. 14.5.1.2.185  EMIF_CTLCFG_DENALI_CTL_134 Register
          186. 14.5.1.2.186  EMIF_CTLCFG_DENALI_CTL_135 Register
          187. 14.5.1.2.187  EMIF_CTLCFG_DENALI_CTL_136 Register
          188. 14.5.1.2.188  EMIF_CTLCFG_DENALI_CTL_137 Register
          189. 14.5.1.2.189  EMIF_CTLCFG_DENALI_CTL_138 Register
          190. 14.5.1.2.190  EMIF_CTLCFG_DENALI_CTL_139 Register
          191. 14.5.1.2.191  EMIF_CTLCFG_DENALI_CTL_140 Register
          192. 14.5.1.2.192  EMIF_CTLCFG_DENALI_CTL_141 Register
          193. 14.5.1.2.193  EMIF_CTLCFG_DENALI_CTL_142 Register
          194. 14.5.1.2.194  EMIF_CTLCFG_DENALI_CTL_143 Register
          195. 14.5.1.2.195  EMIF_CTLCFG_DENALI_CTL_144 Register
          196. 14.5.1.2.196  EMIF_CTLCFG_DENALI_CTL_145 Register
          197. 14.5.1.2.197  EMIF_CTLCFG_DENALI_CTL_146 Register
          198. 14.5.1.2.198  EMIF_CTLCFG_DENALI_CTL_147 Register
          199. 14.5.1.2.199  EMIF_CTLCFG_DENALI_CTL_148 Register
          200. 14.5.1.2.200  EMIF_CTLCFG_DENALI_CTL_149 Register
          201. 14.5.1.2.201  EMIF_CTLCFG_DENALI_CTL_150 Register
          202. 14.5.1.2.202  EMIF_CTLCFG_DENALI_CTL_151 Register
          203. 14.5.1.2.203  EMIF_CTLCFG_DENALI_CTL_152 Register
          204. 14.5.1.2.204  EMIF_CTLCFG_DENALI_CTL_153 Register
          205. 14.5.1.2.205  EMIF_CTLCFG_DENALI_CTL_154 Register
          206. 14.5.1.2.206  EMIF_CTLCFG_DENALI_CTL_155 Register
          207. 14.5.1.2.207  EMIF_CTLCFG_DENALI_CTL_156 Register
          208. 14.5.1.2.208  EMIF_CTLCFG_DENALI_CTL_157 Register
          209. 14.5.1.2.209  EMIF_CTLCFG_DENALI_CTL_158 Register
          210. 14.5.1.2.210  EMIF_CTLCFG_DENALI_CTL_159 Register
          211. 14.5.1.2.211  EMIF_CTLCFG_DENALI_CTL_160 Register
          212. 14.5.1.2.212  EMIF_CTLCFG_DENALI_CTL_161 Register
          213. 14.5.1.2.213  EMIF_CTLCFG_DENALI_CTL_162 Register
          214. 14.5.1.2.214  EMIF_CTLCFG_DENALI_CTL_163 Register
          215. 14.5.1.2.215  EMIF_CTLCFG_DENALI_CTL_164 Register
          216. 14.5.1.2.216  EMIF_CTLCFG_DENALI_CTL_165 Register
          217. 14.5.1.2.217  EMIF_CTLCFG_DENALI_CTL_166 Register
          218. 14.5.1.2.218  EMIF_CTLCFG_DENALI_CTL_167 Register
          219. 14.5.1.2.219  EMIF_CTLCFG_DENALI_CTL_168 Register
          220. 14.5.1.2.220  EMIF_CTLCFG_DENALI_CTL_169 Register
          221. 14.5.1.2.221  EMIF_CTLCFG_DENALI_CTL_170 Register
          222. 14.5.1.2.222  EMIF_CTLCFG_DENALI_CTL_171 Register
          223. 14.5.1.2.223  EMIF_CTLCFG_DENALI_CTL_172 Register
          224. 14.5.1.2.224  EMIF_CTLCFG_DENALI_CTL_173 Register
          225. 14.5.1.2.225  EMIF_CTLCFG_DENALI_CTL_174 Register
          226. 14.5.1.2.226  EMIF_CTLCFG_DENALI_CTL_175 Register
          227. 14.5.1.2.227  EMIF_CTLCFG_DENALI_CTL_176 Register
          228. 14.5.1.2.228  EMIF_CTLCFG_DENALI_CTL_177 Register
          229. 14.5.1.2.229  EMIF_CTLCFG_DENALI_CTL_178 Register
          230. 14.5.1.2.230  EMIF_CTLCFG_DENALI_CTL_179 Register
          231. 14.5.1.2.231  EMIF_CTLCFG_DENALI_CTL_180 Register
          232. 14.5.1.2.232  EMIF_CTLCFG_DENALI_CTL_181 Register
          233. 14.5.1.2.233  EMIF_CTLCFG_DENALI_CTL_182 Register
          234. 14.5.1.2.234  EMIF_CTLCFG_DENALI_CTL_183 Register
          235. 14.5.1.2.235  EMIF_CTLCFG_DENALI_CTL_184 Register
          236. 14.5.1.2.236  EMIF_CTLCFG_DENALI_CTL_185 Register
          237. 14.5.1.2.237  EMIF_CTLCFG_DENALI_CTL_186 Register
          238. 14.5.1.2.238  EMIF_CTLCFG_DENALI_CTL_187 Register
          239. 14.5.1.2.239  EMIF_CTLCFG_DENALI_CTL_188 Register
          240. 14.5.1.2.240  EMIF_CTLCFG_DENALI_CTL_189 Register
          241. 14.5.1.2.241  EMIF_CTLCFG_DENALI_CTL_190 Register
          242. 14.5.1.2.242  EMIF_CTLCFG_DENALI_CTL_191 Register
          243. 14.5.1.2.243  EMIF_CTLCFG_DENALI_CTL_192 Register
          244. 14.5.1.2.244  EMIF_CTLCFG_DENALI_CTL_193 Register
          245. 14.5.1.2.245  EMIF_CTLCFG_DENALI_CTL_194 Register
          246. 14.5.1.2.246  EMIF_CTLCFG_DENALI_CTL_195 Register
          247. 14.5.1.2.247  EMIF_CTLCFG_DENALI_CTL_196 Register
          248. 14.5.1.2.248  EMIF_CTLCFG_DENALI_CTL_197 Register
          249. 14.5.1.2.249  EMIF_CTLCFG_DENALI_CTL_198 Register
          250. 14.5.1.2.250  EMIF_CTLCFG_DENALI_CTL_199 Register
          251. 14.5.1.2.251  EMIF_CTLCFG_DENALI_CTL_200 Register
          252. 14.5.1.2.252  EMIF_CTLCFG_DENALI_CTL_201 Register
          253. 14.5.1.2.253  EMIF_CTLCFG_DENALI_CTL_202 Register
          254. 14.5.1.2.254  EMIF_CTLCFG_DENALI_CTL_203 Register
          255. 14.5.1.2.255  EMIF_CTLCFG_DENALI_CTL_204 Register
          256. 14.5.1.2.256  EMIF_CTLCFG_DENALI_CTL_205 Register
          257. 14.5.1.2.257  EMIF_CTLCFG_DENALI_CTL_206 Register
          258. 14.5.1.2.258  EMIF_CTLCFG_DENALI_CTL_207 Register
          259. 14.5.1.2.259  EMIF_CTLCFG_DENALI_CTL_208 Register
          260. 14.5.1.2.260  EMIF_CTLCFG_DENALI_CTL_209 Register
          261. 14.5.1.2.261  EMIF_CTLCFG_DENALI_CTL_210 Register
          262. 14.5.1.2.262  EMIF_CTLCFG_DENALI_CTL_211 Register
          263. 14.5.1.2.263  EMIF_CTLCFG_DENALI_CTL_212 Register
          264. 14.5.1.2.264  EMIF_CTLCFG_DENALI_CTL_213 Register
          265. 14.5.1.2.265  EMIF_CTLCFG_DENALI_CTL_214 Register
          266. 14.5.1.2.266  EMIF_CTLCFG_DENALI_CTL_215 Register
          267. 14.5.1.2.267  EMIF_CTLCFG_DENALI_CTL_216 Register
          268. 14.5.1.2.268  EMIF_CTLCFG_DENALI_CTL_217 Register
          269. 14.5.1.2.269  EMIF_CTLCFG_DENALI_CTL_218 Register
          270. 14.5.1.2.270  EMIF_CTLCFG_DENALI_CTL_219 Register
          271. 14.5.1.2.271  EMIF_CTLCFG_DENALI_CTL_220 Register
          272. 14.5.1.2.272  EMIF_CTLCFG_DENALI_CTL_221 Register
          273. 14.5.1.2.273  EMIF_CTLCFG_DENALI_CTL_222 Register
          274. 14.5.1.2.274  EMIF_CTLCFG_DENALI_CTL_223 Register
          275. 14.5.1.2.275  EMIF_CTLCFG_DENALI_CTL_224 Register
          276. 14.5.1.2.276  EMIF_CTLCFG_DENALI_CTL_225 Register
          277. 14.5.1.2.277  EMIF_CTLCFG_DENALI_CTL_226 Register
          278. 14.5.1.2.278  EMIF_CTLCFG_DENALI_CTL_227 Register
          279. 14.5.1.2.279  EMIF_CTLCFG_DENALI_CTL_228 Register
          280. 14.5.1.2.280  EMIF_CTLCFG_DENALI_CTL_229 Register
          281. 14.5.1.2.281  EMIF_CTLCFG_DENALI_CTL_230 Register
          282. 14.5.1.2.282  EMIF_CTLCFG_DENALI_CTL_231 Register
          283. 14.5.1.2.283  EMIF_CTLCFG_DENALI_CTL_232 Register
          284. 14.5.1.2.284  EMIF_CTLCFG_DENALI_CTL_233 Register
          285. 14.5.1.2.285  EMIF_CTLCFG_DENALI_CTL_234 Register
          286. 14.5.1.2.286  EMIF_CTLCFG_DENALI_CTL_235 Register
          287. 14.5.1.2.287  EMIF_CTLCFG_DENALI_CTL_236 Register
          288. 14.5.1.2.288  EMIF_CTLCFG_DENALI_CTL_237 Register
          289. 14.5.1.2.289  EMIF_CTLCFG_DENALI_CTL_238 Register
          290. 14.5.1.2.290  EMIF_CTLCFG_DENALI_CTL_239 Register
          291. 14.5.1.2.291  EMIF_CTLCFG_DENALI_CTL_240 Register
          292. 14.5.1.2.292  EMIF_CTLCFG_DENALI_CTL_241 Register
          293. 14.5.1.2.293  EMIF_CTLCFG_DENALI_CTL_242 Register
          294. 14.5.1.2.294  EMIF_CTLCFG_DENALI_CTL_243 Register
          295. 14.5.1.2.295  EMIF_CTLCFG_DENALI_CTL_244 Register
          296. 14.5.1.2.296  EMIF_CTLCFG_DENALI_CTL_245 Register
          297. 14.5.1.2.297  EMIF_CTLCFG_DENALI_CTL_246 Register
          298. 14.5.1.2.298  EMIF_CTLCFG_DENALI_CTL_247 Register
          299. 14.5.1.2.299  EMIF_CTLCFG_DENALI_CTL_248 Register
          300. 14.5.1.2.300  EMIF_CTLCFG_DENALI_CTL_249 Register
          301. 14.5.1.2.301  EMIF_CTLCFG_DENALI_CTL_250 Register
          302. 14.5.1.2.302  EMIF_CTLCFG_DENALI_CTL_251 Register
          303. 14.5.1.2.303  EMIF_CTLCFG_DENALI_CTL_252 Register
          304. 14.5.1.2.304  EMIF_CTLCFG_DENALI_CTL_253 Register
          305. 14.5.1.2.305  EMIF_CTLCFG_DENALI_CTL_254 Register
          306. 14.5.1.2.306  EMIF_CTLCFG_DENALI_CTL_255 Register
          307. 14.5.1.2.307  EMIF_CTLCFG_DENALI_CTL_256 Register
          308. 14.5.1.2.308  EMIF_CTLCFG_DENALI_CTL_257 Register
          309. 14.5.1.2.309  EMIF_CTLCFG_DENALI_CTL_258 Register
          310. 14.5.1.2.310  EMIF_CTLCFG_DENALI_CTL_259 Register
          311. 14.5.1.2.311  EMIF_CTLCFG_DENALI_CTL_260 Register
          312. 14.5.1.2.312  EMIF_CTLCFG_DENALI_CTL_261 Register
          313. 14.5.1.2.313  EMIF_CTLCFG_DENALI_CTL_262 Register
          314. 14.5.1.2.314  EMIF_CTLCFG_DENALI_CTL_263 Register
          315. 14.5.1.2.315  EMIF_CTLCFG_DENALI_CTL_264 Register
          316. 14.5.1.2.316  EMIF_CTLCFG_DENALI_CTL_265 Register
          317. 14.5.1.2.317  EMIF_CTLCFG_DENALI_CTL_266 Register
          318. 14.5.1.2.318  EMIF_CTLCFG_DENALI_CTL_267 Register
          319. 14.5.1.2.319  EMIF_CTLCFG_DENALI_CTL_268 Register
          320. 14.5.1.2.320  EMIF_CTLCFG_DENALI_CTL_269 Register
          321. 14.5.1.2.321  EMIF_CTLCFG_DENALI_CTL_270 Register
          322. 14.5.1.2.322  EMIF_CTLCFG_DENALI_CTL_271 Register
          323. 14.5.1.2.323  EMIF_CTLCFG_DENALI_CTL_272 Register
          324. 14.5.1.2.324  EMIF_CTLCFG_DENALI_CTL_273 Register
          325. 14.5.1.2.325  EMIF_CTLCFG_DENALI_CTL_274 Register
          326. 14.5.1.2.326  EMIF_CTLCFG_DENALI_CTL_275 Register
          327. 14.5.1.2.327  EMIF_CTLCFG_DENALI_CTL_276 Register
          328. 14.5.1.2.328  EMIF_CTLCFG_DENALI_CTL_277 Register
          329. 14.5.1.2.329  EMIF_CTLCFG_DENALI_CTL_278 Register
          330. 14.5.1.2.330  EMIF_CTLCFG_DENALI_CTL_279 Register
          331. 14.5.1.2.331  EMIF_CTLCFG_DENALI_CTL_280 Register
          332. 14.5.1.2.332  EMIF_CTLCFG_DENALI_CTL_281 Register
          333. 14.5.1.2.333  EMIF_CTLCFG_DENALI_CTL_282 Register
          334. 14.5.1.2.334  EMIF_CTLCFG_DENALI_CTL_283 Register
          335. 14.5.1.2.335  EMIF_CTLCFG_DENALI_CTL_284 Register
          336. 14.5.1.2.336  EMIF_CTLCFG_DENALI_CTL_285 Register
          337. 14.5.1.2.337  EMIF_CTLCFG_DENALI_CTL_286 Register
          338. 14.5.1.2.338  EMIF_CTLCFG_DENALI_CTL_287 Register
          339. 14.5.1.2.339  EMIF_CTLCFG_DENALI_CTL_288 Register
          340. 14.5.1.2.340  EMIF_CTLCFG_DENALI_CTL_289 Register
          341. 14.5.1.2.341  EMIF_CTLCFG_DENALI_CTL_290 Register
          342. 14.5.1.2.342  EMIF_CTLCFG_DENALI_CTL_291 Register
          343. 14.5.1.2.343  EMIF_CTLCFG_DENALI_CTL_292 Register
          344. 14.5.1.2.344  EMIF_CTLCFG_DENALI_CTL_293 Register
          345. 14.5.1.2.345  EMIF_CTLCFG_DENALI_CTL_294 Register
          346. 14.5.1.2.346  EMIF_CTLCFG_DENALI_CTL_295 Register
          347. 14.5.1.2.347  EMIF_CTLCFG_DENALI_CTL_296 Register
          348. 14.5.1.2.348  EMIF_CTLCFG_DENALI_CTL_297 Register
          349. 14.5.1.2.349  EMIF_CTLCFG_DENALI_CTL_298 Register
          350. 14.5.1.2.350  EMIF_CTLCFG_DENALI_CTL_299 Register
          351. 14.5.1.2.351  EMIF_CTLCFG_DENALI_CTL_300 Register
          352. 14.5.1.2.352  EMIF_CTLCFG_DENALI_CTL_301 Register
          353. 14.5.1.2.353  EMIF_CTLCFG_DENALI_CTL_302 Register
          354. 14.5.1.2.354  EMIF_CTLCFG_DENALI_CTL_303 Register
          355. 14.5.1.2.355  EMIF_CTLCFG_DENALI_CTL_304 Register
          356. 14.5.1.2.356  EMIF_CTLCFG_DENALI_CTL_305 Register
          357. 14.5.1.2.357  EMIF_CTLCFG_DENALI_CTL_306 Register
          358. 14.5.1.2.358  EMIF_CTLCFG_DENALI_CTL_307 Register
          359. 14.5.1.2.359  EMIF_CTLCFG_DENALI_CTL_308 Register
          360. 14.5.1.2.360  EMIF_CTLCFG_DENALI_CTL_309 Register
          361. 14.5.1.2.361  EMIF_CTLCFG_DENALI_CTL_310 Register
          362. 14.5.1.2.362  EMIF_CTLCFG_DENALI_CTL_311 Register
          363. 14.5.1.2.363  EMIF_CTLCFG_DENALI_CTL_312 Register
          364. 14.5.1.2.364  EMIF_CTLCFG_DENALI_CTL_313 Register
          365. 14.5.1.2.365  EMIF_CTLCFG_DENALI_CTL_314 Register
          366. 14.5.1.2.366  EMIF_CTLCFG_DENALI_CTL_315 Register
          367. 14.5.1.2.367  EMIF_CTLCFG_DENALI_CTL_316 Register
          368. 14.5.1.2.368  EMIF_CTLCFG_DENALI_CTL_317 Register
          369. 14.5.1.2.369  EMIF_CTLCFG_DENALI_CTL_318 Register
          370. 14.5.1.2.370  EMIF_CTLCFG_DENALI_CTL_319 Register
          371. 14.5.1.2.371  EMIF_CTLCFG_DENALI_CTL_320 Register
          372. 14.5.1.2.372  EMIF_CTLCFG_DENALI_CTL_321 Register
          373. 14.5.1.2.373  EMIF_CTLCFG_DENALI_CTL_322 Register
          374. 14.5.1.2.374  EMIF_CTLCFG_DENALI_CTL_323 Register
          375. 14.5.1.2.375  EMIF_CTLCFG_DENALI_CTL_324 Register
          376. 14.5.1.2.376  EMIF_CTLCFG_DENALI_CTL_325 Register
          377. 14.5.1.2.377  EMIF_CTLCFG_DENALI_CTL_326 Register
          378. 14.5.1.2.378  EMIF_CTLCFG_DENALI_CTL_327 Register
          379. 14.5.1.2.379  EMIF_CTLCFG_DENALI_CTL_328 Register
          380. 14.5.1.2.380  EMIF_CTLCFG_DENALI_CTL_329 Register
          381. 14.5.1.2.381  EMIF_CTLCFG_DENALI_CTL_330 Register
          382. 14.5.1.2.382  EMIF_CTLCFG_DENALI_CTL_331 Register
          383. 14.5.1.2.383  EMIF_CTLCFG_DENALI_CTL_332 Register
          384. 14.5.1.2.384  EMIF_CTLCFG_DENALI_CTL_333 Register
          385. 14.5.1.2.385  EMIF_CTLCFG_DENALI_CTL_334 Register
          386. 14.5.1.2.386  EMIF_CTLCFG_DENALI_CTL_335 Register
          387. 14.5.1.2.387  EMIF_CTLCFG_DENALI_CTL_336 Register
          388. 14.5.1.2.388  EMIF_CTLCFG_DENALI_CTL_337 Register
          389. 14.5.1.2.389  EMIF_CTLCFG_DENALI_CTL_338 Register
          390. 14.5.1.2.390  EMIF_CTLCFG_DENALI_CTL_339 Register
          391. 14.5.1.2.391  EMIF_CTLCFG_DENALI_CTL_340 Register
          392. 14.5.1.2.392  EMIF_CTLCFG_DENALI_CTL_341 Register
          393. 14.5.1.2.393  EMIF_CTLCFG_DENALI_CTL_342 Register
          394. 14.5.1.2.394  EMIF_CTLCFG_DENALI_CTL_343 Register
          395. 14.5.1.2.395  EMIF_CTLCFG_DENALI_CTL_344 Register
          396. 14.5.1.2.396  EMIF_CTLCFG_DENALI_CTL_345 Register
          397. 14.5.1.2.397  EMIF_CTLCFG_DENALI_CTL_346 Register
          398. 14.5.1.2.398  EMIF_CTLCFG_DENALI_CTL_347 Register
          399. 14.5.1.2.399  EMIF_CTLCFG_DENALI_CTL_348 Register
          400. 14.5.1.2.400  EMIF_CTLCFG_DENALI_CTL_349 Register
          401. 14.5.1.2.401  EMIF_CTLCFG_DENALI_CTL_350 Register
          402. 14.5.1.2.402  EMIF_CTLCFG_DENALI_CTL_351 Register
          403. 14.5.1.2.403  EMIF_CTLCFG_DENALI_CTL_352 Register
          404. 14.5.1.2.404  EMIF_CTLCFG_DENALI_CTL_353 Register
          405. 14.5.1.2.405  EMIF_CTLCFG_DENALI_CTL_354 Register
          406. 14.5.1.2.406  EMIF_CTLCFG_DENALI_CTL_355 Register
          407. 14.5.1.2.407  EMIF_CTLCFG_DENALI_CTL_356 Register
          408. 14.5.1.2.408  EMIF_CTLCFG_DENALI_CTL_357 Register
          409. 14.5.1.2.409  EMIF_CTLCFG_DENALI_CTL_358 Register
          410. 14.5.1.2.410  EMIF_CTLCFG_DENALI_CTL_359 Register
          411. 14.5.1.2.411  EMIF_CTLCFG_DENALI_CTL_360 Register
          412. 14.5.1.2.412  EMIF_CTLCFG_DENALI_CTL_361 Register
          413. 14.5.1.2.413  EMIF_CTLCFG_DENALI_CTL_362 Register
          414. 14.5.1.2.414  EMIF_CTLCFG_DENALI_CTL_363 Register
          415. 14.5.1.2.415  EMIF_CTLCFG_DENALI_CTL_364 Register
          416. 14.5.1.2.416  EMIF_CTLCFG_DENALI_CTL_365 Register
          417. 14.5.1.2.417  EMIF_CTLCFG_DENALI_CTL_366 Register
          418. 14.5.1.2.418  EMIF_CTLCFG_DENALI_CTL_367 Register
          419. 14.5.1.2.419  EMIF_CTLCFG_DENALI_CTL_368 Register
          420. 14.5.1.2.420  EMIF_CTLCFG_DENALI_CTL_369 Register
          421. 14.5.1.2.421  EMIF_CTLCFG_DENALI_CTL_370 Register
          422. 14.5.1.2.422  EMIF_CTLCFG_DENALI_CTL_371 Register
          423. 14.5.1.2.423  EMIF_CTLCFG_DENALI_CTL_372 Register
          424. 14.5.1.2.424  EMIF_CTLCFG_DENALI_CTL_373 Register
          425. 14.5.1.2.425  EMIF_CTLCFG_DENALI_CTL_374 Register
          426. 14.5.1.2.426  EMIF_CTLCFG_DENALI_CTL_375 Register
          427. 14.5.1.2.427  EMIF_CTLCFG_DENALI_CTL_376 Register
          428. 14.5.1.2.428  EMIF_CTLCFG_DENALI_CTL_377 Register
          429. 14.5.1.2.429  EMIF_CTLCFG_DENALI_CTL_378 Register
          430. 14.5.1.2.430  EMIF_CTLCFG_DENALI_CTL_379 Register
          431. 14.5.1.2.431  EMIF_CTLCFG_DENALI_CTL_380 Register
          432. 14.5.1.2.432  EMIF_CTLCFG_DENALI_CTL_381 Register
          433. 14.5.1.2.433  EMIF_CTLCFG_DENALI_CTL_382 Register
          434. 14.5.1.2.434  EMIF_CTLCFG_DENALI_CTL_383 Register
          435. 14.5.1.2.435  EMIF_CTLCFG_DENALI_CTL_384 Register
          436. 14.5.1.2.436  EMIF_CTLCFG_DENALI_CTL_385 Register
          437. 14.5.1.2.437  EMIF_CTLCFG_DENALI_CTL_386 Register
          438. 14.5.1.2.438  EMIF_CTLCFG_DENALI_CTL_387 Register
          439. 14.5.1.2.439  EMIF_CTLCFG_DENALI_CTL_388 Register
          440. 14.5.1.2.440  EMIF_CTLCFG_DENALI_CTL_389 Register
          441. 14.5.1.2.441  EMIF_CTLCFG_DENALI_CTL_390 Register
          442. 14.5.1.2.442  EMIF_CTLCFG_DENALI_CTL_391 Register
          443. 14.5.1.2.443  EMIF_CTLCFG_DENALI_CTL_392 Register
          444. 14.5.1.2.444  EMIF_CTLCFG_DENALI_CTL_393 Register
          445. 14.5.1.2.445  EMIF_CTLCFG_DENALI_CTL_394 Register
          446. 14.5.1.2.446  EMIF_CTLCFG_DENALI_CTL_395 Register
          447. 14.5.1.2.447  EMIF_CTLCFG_DENALI_CTL_396 Register
          448. 14.5.1.2.448  EMIF_CTLCFG_DENALI_CTL_397 Register
          449. 14.5.1.2.449  EMIF_CTLCFG_DENALI_CTL_398 Register
          450. 14.5.1.2.450  EMIF_CTLCFG_DENALI_CTL_399 Register
          451. 14.5.1.2.451  EMIF_CTLCFG_DENALI_CTL_400 Register
          452. 14.5.1.2.452  EMIF_CTLCFG_DENALI_CTL_401 Register
          453. 14.5.1.2.453  EMIF_CTLCFG_DENALI_CTL_402 Register
          454. 14.5.1.2.454  EMIF_CTLCFG_DENALI_CTL_403 Register
          455. 14.5.1.2.455  EMIF_CTLCFG_DENALI_CTL_404 Register
          456. 14.5.1.2.456  EMIF_CTLCFG_DENALI_CTL_405 Register
          457. 14.5.1.2.457  EMIF_CTLCFG_DENALI_CTL_406 Register
          458. 14.5.1.2.458  EMIF_CTLCFG_DENALI_CTL_407 Register
          459. 14.5.1.2.459  EMIF_CTLCFG_DENALI_CTL_408 Register
          460. 14.5.1.2.460  EMIF_CTLCFG_DENALI_CTL_409 Register
          461. 14.5.1.2.461  EMIF_CTLCFG_DENALI_CTL_410 Register
          462. 14.5.1.2.462  EMIF_CTLCFG_DENALI_CTL_411 Register
          463. 14.5.1.2.463  EMIF_CTLCFG_DENALI_CTL_412 Register
          464. 14.5.1.2.464  EMIF_CTLCFG_DENALI_CTL_413 Register
          465. 14.5.1.2.465  EMIF_CTLCFG_DENALI_CTL_414 Register
          466. 14.5.1.2.466  EMIF_CTLCFG_DENALI_CTL_415 Register
          467. 14.5.1.2.467  EMIF_CTLCFG_DENALI_CTL_416 Register
          468. 14.5.1.2.468  EMIF_CTLCFG_DENALI_CTL_417 Register
          469. 14.5.1.2.469  EMIF_CTLCFG_DENALI_CTL_418 Register
          470. 14.5.1.2.470  EMIF_CTLCFG_DENALI_CTL_419 Register
          471. 14.5.1.2.471  EMIF_CTLCFG_DENALI_CTL_420 Register
          472. 14.5.1.2.472  EMIF_CTLCFG_DENALI_CTL_421 Register
          473. 14.5.1.2.473  EMIF_CTLCFG_DENALI_CTL_422 Register
          474. 14.5.1.2.474  EMIF_CTLCFG_DENALI_PI_0 Register
          475. 14.5.1.2.475  EMIF_CTLCFG_DENALI_PI_1 Register
          476. 14.5.1.2.476  EMIF_CTLCFG_DENALI_PI_2 Register
          477. 14.5.1.2.477  EMIF_CTLCFG_DENALI_PI_3 Register
          478. 14.5.1.2.478  EMIF_CTLCFG_DENALI_PI_4 Register
          479. 14.5.1.2.479  EMIF_CTLCFG_DENALI_PI_5 Register
          480. 14.5.1.2.480  EMIF_CTLCFG_DENALI_PI_6 Register
          481. 14.5.1.2.481  EMIF_CTLCFG_DENALI_PI_7 Register
          482. 14.5.1.2.482  EMIF_CTLCFG_DENALI_PI_8 Register
          483. 14.5.1.2.483  EMIF_CTLCFG_DENALI_PI_9 Register
          484. 14.5.1.2.484  EMIF_CTLCFG_DENALI_PI_10 Register
          485. 14.5.1.2.485  EMIF_CTLCFG_DENALI_PI_11 Register
          486. 14.5.1.2.486  EMIF_CTLCFG_DENALI_PI_12 Register
          487. 14.5.1.2.487  EMIF_CTLCFG_DENALI_PI_13 Register
          488. 14.5.1.2.488  EMIF_CTLCFG_DENALI_PI_14 Register
          489. 14.5.1.2.489  EMIF_CTLCFG_DENALI_PI_15 Register
          490. 14.5.1.2.490  EMIF_CTLCFG_DENALI_PI_16 Register
          491. 14.5.1.2.491  EMIF_CTLCFG_DENALI_PI_17 Register
          492. 14.5.1.2.492  EMIF_CTLCFG_DENALI_PI_18 Register
          493. 14.5.1.2.493  EMIF_CTLCFG_DENALI_PI_19 Register
          494. 14.5.1.2.494  EMIF_CTLCFG_DENALI_PI_20 Register
          495. 14.5.1.2.495  EMIF_CTLCFG_DENALI_PI_21 Register
          496. 14.5.1.2.496  EMIF_CTLCFG_DENALI_PI_22 Register
          497. 14.5.1.2.497  EMIF_CTLCFG_DENALI_PI_23 Register
          498. 14.5.1.2.498  EMIF_CTLCFG_DENALI_PI_24 Register
          499. 14.5.1.2.499  EMIF_CTLCFG_DENALI_PI_25 Register
          500. 14.5.1.2.500  EMIF_CTLCFG_DENALI_PI_26 Register
          501. 14.5.1.2.501  EMIF_CTLCFG_DENALI_PI_27 Register
          502. 14.5.1.2.502  EMIF_CTLCFG_DENALI_PI_28 Register
          503. 14.5.1.2.503  EMIF_CTLCFG_DENALI_PI_29 Register
          504. 14.5.1.2.504  EMIF_CTLCFG_DENALI_PI_30 Register
          505. 14.5.1.2.505  EMIF_CTLCFG_DENALI_PI_31 Register
          506. 14.5.1.2.506  EMIF_CTLCFG_DENALI_PI_32 Register
          507. 14.5.1.2.507  EMIF_CTLCFG_DENALI_PI_33 Register
          508. 14.5.1.2.508  EMIF_CTLCFG_DENALI_PI_34 Register
          509. 14.5.1.2.509  EMIF_CTLCFG_DENALI_PI_35 Register
          510. 14.5.1.2.510  EMIF_CTLCFG_DENALI_PI_36 Register
          511. 14.5.1.2.511  EMIF_CTLCFG_DENALI_PI_37 Register
          512. 14.5.1.2.512  EMIF_CTLCFG_DENALI_PI_38 Register
          513. 14.5.1.2.513  EMIF_CTLCFG_DENALI_PI_39 Register
          514. 14.5.1.2.514  EMIF_CTLCFG_DENALI_PI_40 Register
          515. 14.5.1.2.515  EMIF_CTLCFG_DENALI_PI_41 Register
          516. 14.5.1.2.516  EMIF_CTLCFG_DENALI_PI_42 Register
          517. 14.5.1.2.517  EMIF_CTLCFG_DENALI_PI_43 Register
          518. 14.5.1.2.518  EMIF_CTLCFG_DENALI_PI_44 Register
          519. 14.5.1.2.519  EMIF_CTLCFG_DENALI_PI_45 Register
          520. 14.5.1.2.520  EMIF_CTLCFG_DENALI_PI_46 Register
          521. 14.5.1.2.521  EMIF_CTLCFG_DENALI_PI_47 Register
          522. 14.5.1.2.522  EMIF_CTLCFG_DENALI_PI_48 Register
          523. 14.5.1.2.523  EMIF_CTLCFG_DENALI_PI_49 Register
          524. 14.5.1.2.524  EMIF_CTLCFG_DENALI_PI_50 Register
          525. 14.5.1.2.525  EMIF_CTLCFG_DENALI_PI_51 Register
          526. 14.5.1.2.526  EMIF_CTLCFG_DENALI_PI_52 Register
          527. 14.5.1.2.527  EMIF_CTLCFG_DENALI_PI_53 Register
          528. 14.5.1.2.528  EMIF_CTLCFG_DENALI_PI_54 Register
          529. 14.5.1.2.529  EMIF_CTLCFG_DENALI_PI_55 Register
          530. 14.5.1.2.530  EMIF_CTLCFG_DENALI_PI_56 Register
          531. 14.5.1.2.531  EMIF_CTLCFG_DENALI_PI_57 Register
          532. 14.5.1.2.532  EMIF_CTLCFG_DENALI_PI_58 Register
          533. 14.5.1.2.533  EMIF_CTLCFG_DENALI_PI_59 Register
          534. 14.5.1.2.534  EMIF_CTLCFG_DENALI_PI_60 Register
          535. 14.5.1.2.535  EMIF_CTLCFG_DENALI_PI_61 Register
          536. 14.5.1.2.536  EMIF_CTLCFG_DENALI_PI_62 Register
          537. 14.5.1.2.537  EMIF_CTLCFG_DENALI_PI_63 Register
          538. 14.5.1.2.538  EMIF_CTLCFG_DENALI_PI_64 Register
          539. 14.5.1.2.539  EMIF_CTLCFG_DENALI_PI_65 Register
          540. 14.5.1.2.540  EMIF_CTLCFG_DENALI_PI_66 Register
          541. 14.5.1.2.541  EMIF_CTLCFG_DENALI_PI_67 Register
          542. 14.5.1.2.542  EMIF_CTLCFG_DENALI_PI_68 Register
          543. 14.5.1.2.543  EMIF_CTLCFG_DENALI_PI_69 Register
          544. 14.5.1.2.544  EMIF_CTLCFG_DENALI_PI_70 Register
          545. 14.5.1.2.545  EMIF_CTLCFG_DENALI_PI_71 Register
          546. 14.5.1.2.546  EMIF_CTLCFG_DENALI_PI_72 Register
          547. 14.5.1.2.547  EMIF_CTLCFG_DENALI_PI_73 Register
          548. 14.5.1.2.548  EMIF_CTLCFG_DENALI_PI_74 Register
          549. 14.5.1.2.549  EMIF_CTLCFG_DENALI_PI_75 Register
          550. 14.5.1.2.550  EMIF_CTLCFG_DENALI_PI_76 Register
          551. 14.5.1.2.551  EMIF_CTLCFG_DENALI_PI_77 Register
          552. 14.5.1.2.552  EMIF_CTLCFG_DENALI_PI_78 Register
          553. 14.5.1.2.553  EMIF_CTLCFG_DENALI_PI_79 Register
          554. 14.5.1.2.554  EMIF_CTLCFG_DENALI_PI_80 Register
          555. 14.5.1.2.555  EMIF_CTLCFG_DENALI_PI_81 Register
          556. 14.5.1.2.556  EMIF_CTLCFG_DENALI_PI_82 Register
          557. 14.5.1.2.557  EMIF_CTLCFG_DENALI_PI_83 Register
          558. 14.5.1.2.558  EMIF_CTLCFG_DENALI_PI_84 Register
          559. 14.5.1.2.559  EMIF_CTLCFG_DENALI_PI_85 Register
          560. 14.5.1.2.560  EMIF_CTLCFG_DENALI_PI_86 Register
          561. 14.5.1.2.561  EMIF_CTLCFG_DENALI_PI_87 Register
          562. 14.5.1.2.562  EMIF_CTLCFG_DENALI_PI_88 Register
          563. 14.5.1.2.563  EMIF_CTLCFG_DENALI_PI_89 Register
          564. 14.5.1.2.564  EMIF_CTLCFG_DENALI_PI_90 Register
          565. 14.5.1.2.565  EMIF_CTLCFG_DENALI_PI_91 Register
          566. 14.5.1.2.566  EMIF_CTLCFG_DENALI_PI_92 Register
          567. 14.5.1.2.567  EMIF_CTLCFG_DENALI_PI_93 Register
          568. 14.5.1.2.568  EMIF_CTLCFG_DENALI_PI_94 Register
          569. 14.5.1.2.569  EMIF_CTLCFG_DENALI_PI_95 Register
          570. 14.5.1.2.570  EMIF_CTLCFG_DENALI_PI_96 Register
          571. 14.5.1.2.571  EMIF_CTLCFG_DENALI_PI_97 Register
          572. 14.5.1.2.572  EMIF_CTLCFG_DENALI_PI_98 Register
          573. 14.5.1.2.573  EMIF_CTLCFG_DENALI_PI_99 Register
          574. 14.5.1.2.574  EMIF_CTLCFG_DENALI_PI_100 Register
          575. 14.5.1.2.575  EMIF_CTLCFG_DENALI_PI_101 Register
          576. 14.5.1.2.576  EMIF_CTLCFG_DENALI_PI_102 Register
          577. 14.5.1.2.577  EMIF_CTLCFG_DENALI_PI_103 Register
          578. 14.5.1.2.578  EMIF_CTLCFG_DENALI_PI_104 Register
          579. 14.5.1.2.579  EMIF_CTLCFG_DENALI_PI_105 Register
          580. 14.5.1.2.580  EMIF_CTLCFG_DENALI_PI_106 Register
          581. 14.5.1.2.581  EMIF_CTLCFG_DENALI_PI_107 Register
          582. 14.5.1.2.582  EMIF_CTLCFG_DENALI_PI_108 Register
          583. 14.5.1.2.583  EMIF_CTLCFG_DENALI_PI_109 Register
          584. 14.5.1.2.584  EMIF_CTLCFG_DENALI_PI_110 Register
          585. 14.5.1.2.585  EMIF_CTLCFG_DENALI_PI_111 Register
          586. 14.5.1.2.586  EMIF_CTLCFG_DENALI_PI_112 Register
          587. 14.5.1.2.587  EMIF_CTLCFG_DENALI_PI_113 Register
          588. 14.5.1.2.588  EMIF_CTLCFG_DENALI_PI_114 Register
          589. 14.5.1.2.589  EMIF_CTLCFG_DENALI_PI_115 Register
          590. 14.5.1.2.590  EMIF_CTLCFG_DENALI_PI_116 Register
          591. 14.5.1.2.591  EMIF_CTLCFG_DENALI_PI_117 Register
          592. 14.5.1.2.592  EMIF_CTLCFG_DENALI_PI_118 Register
          593. 14.5.1.2.593  EMIF_CTLCFG_DENALI_PI_119 Register
          594. 14.5.1.2.594  EMIF_CTLCFG_DENALI_PI_120 Register
          595. 14.5.1.2.595  EMIF_CTLCFG_DENALI_PI_121 Register
          596. 14.5.1.2.596  EMIF_CTLCFG_DENALI_PI_122 Register
          597. 14.5.1.2.597  EMIF_CTLCFG_DENALI_PI_123 Register
          598. 14.5.1.2.598  EMIF_CTLCFG_DENALI_PI_124 Register
          599. 14.5.1.2.599  EMIF_CTLCFG_DENALI_PI_125 Register
          600. 14.5.1.2.600  EMIF_CTLCFG_DENALI_PI_126 Register
          601. 14.5.1.2.601  EMIF_CTLCFG_DENALI_PI_127 Register
          602. 14.5.1.2.602  EMIF_CTLCFG_DENALI_PI_128 Register
          603. 14.5.1.2.603  EMIF_CTLCFG_DENALI_PI_129 Register
          604. 14.5.1.2.604  EMIF_CTLCFG_DENALI_PI_130 Register
          605. 14.5.1.2.605  EMIF_CTLCFG_DENALI_PI_131 Register
          606. 14.5.1.2.606  EMIF_CTLCFG_DENALI_PI_132 Register
          607. 14.5.1.2.607  EMIF_CTLCFG_DENALI_PI_133 Register
          608. 14.5.1.2.608  EMIF_CTLCFG_DENALI_PI_134 Register
          609. 14.5.1.2.609  EMIF_CTLCFG_DENALI_PI_135 Register
          610. 14.5.1.2.610  EMIF_CTLCFG_DENALI_PI_136 Register
          611. 14.5.1.2.611  EMIF_CTLCFG_DENALI_PI_137 Register
          612. 14.5.1.2.612  EMIF_CTLCFG_DENALI_PI_138 Register
          613. 14.5.1.2.613  EMIF_CTLCFG_DENALI_PI_139 Register
          614. 14.5.1.2.614  EMIF_CTLCFG_DENALI_PI_140 Register
          615. 14.5.1.2.615  EMIF_CTLCFG_DENALI_PI_141 Register
          616. 14.5.1.2.616  EMIF_CTLCFG_DENALI_PI_142 Register
          617. 14.5.1.2.617  EMIF_CTLCFG_DENALI_PI_143 Register
          618. 14.5.1.2.618  EMIF_CTLCFG_DENALI_PI_144 Register
          619. 14.5.1.2.619  EMIF_CTLCFG_DENALI_PI_145 Register
          620. 14.5.1.2.620  EMIF_CTLCFG_DENALI_PI_146 Register
          621. 14.5.1.2.621  EMIF_CTLCFG_DENALI_PI_147 Register
          622. 14.5.1.2.622  EMIF_CTLCFG_DENALI_PI_148 Register
          623. 14.5.1.2.623  EMIF_CTLCFG_DENALI_PI_149 Register
          624. 14.5.1.2.624  EMIF_CTLCFG_DENALI_PI_150 Register
          625. 14.5.1.2.625  EMIF_CTLCFG_DENALI_PI_151 Register
          626. 14.5.1.2.626  EMIF_CTLCFG_DENALI_PI_152 Register
          627. 14.5.1.2.627  EMIF_CTLCFG_DENALI_PI_153 Register
          628. 14.5.1.2.628  EMIF_CTLCFG_DENALI_PI_154 Register
          629. 14.5.1.2.629  EMIF_CTLCFG_DENALI_PI_155 Register
          630. 14.5.1.2.630  EMIF_CTLCFG_DENALI_PI_156 Register
          631. 14.5.1.2.631  EMIF_CTLCFG_DENALI_PI_157 Register
          632. 14.5.1.2.632  EMIF_CTLCFG_DENALI_PI_158 Register
          633. 14.5.1.2.633  EMIF_CTLCFG_DENALI_PI_159 Register
          634. 14.5.1.2.634  EMIF_CTLCFG_DENALI_PI_160 Register
          635. 14.5.1.2.635  EMIF_CTLCFG_DENALI_PI_161 Register
          636. 14.5.1.2.636  EMIF_CTLCFG_DENALI_PI_162 Register
          637. 14.5.1.2.637  EMIF_CTLCFG_DENALI_PI_163 Register
          638. 14.5.1.2.638  EMIF_CTLCFG_DENALI_PI_164 Register
          639. 14.5.1.2.639  EMIF_CTLCFG_DENALI_PI_165 Register
          640. 14.5.1.2.640  EMIF_CTLCFG_DENALI_PI_166 Register
          641. 14.5.1.2.641  EMIF_CTLCFG_DENALI_PI_167 Register
          642. 14.5.1.2.642  EMIF_CTLCFG_DENALI_PI_168 Register
          643. 14.5.1.2.643  EMIF_CTLCFG_DENALI_PI_169 Register
          644. 14.5.1.2.644  EMIF_CTLCFG_DENALI_PI_170 Register
          645. 14.5.1.2.645  EMIF_CTLCFG_DENALI_PI_171 Register
          646. 14.5.1.2.646  EMIF_CTLCFG_DENALI_PI_172 Register
          647. 14.5.1.2.647  EMIF_CTLCFG_DENALI_PI_173 Register
          648. 14.5.1.2.648  EMIF_CTLCFG_DENALI_PI_174 Register
          649. 14.5.1.2.649  EMIF_CTLCFG_DENALI_PI_175 Register
          650. 14.5.1.2.650  EMIF_CTLCFG_DENALI_PI_176 Register
          651. 14.5.1.2.651  EMIF_CTLCFG_DENALI_PI_177 Register
          652. 14.5.1.2.652  EMIF_CTLCFG_DENALI_PI_178 Register
          653. 14.5.1.2.653  EMIF_CTLCFG_DENALI_PI_179 Register
          654. 14.5.1.2.654  EMIF_CTLCFG_DENALI_PI_180 Register
          655. 14.5.1.2.655  EMIF_CTLCFG_DENALI_PI_181 Register
          656. 14.5.1.2.656  EMIF_CTLCFG_DENALI_PI_182 Register
          657. 14.5.1.2.657  EMIF_CTLCFG_DENALI_PI_183 Register
          658. 14.5.1.2.658  EMIF_CTLCFG_DENALI_PI_184 Register
          659. 14.5.1.2.659  EMIF_CTLCFG_DENALI_PI_185 Register
          660. 14.5.1.2.660  EMIF_CTLCFG_DENALI_PI_186 Register
          661. 14.5.1.2.661  EMIF_CTLCFG_DENALI_PI_187 Register
          662. 14.5.1.2.662  EMIF_CTLCFG_DENALI_PI_188 Register
          663. 14.5.1.2.663  EMIF_CTLCFG_DENALI_PI_189 Register
          664. 14.5.1.2.664  EMIF_CTLCFG_DENALI_PI_190 Register
          665. 14.5.1.2.665  EMIF_CTLCFG_DENALI_PI_191 Register
          666. 14.5.1.2.666  EMIF_CTLCFG_DENALI_PI_192 Register
          667. 14.5.1.2.667  EMIF_CTLCFG_DENALI_PI_193 Register
          668. 14.5.1.2.668  EMIF_CTLCFG_DENALI_PI_194 Register
          669. 14.5.1.2.669  EMIF_CTLCFG_DENALI_PI_195 Register
          670. 14.5.1.2.670  EMIF_CTLCFG_DENALI_PI_196 Register
          671. 14.5.1.2.671  EMIF_CTLCFG_DENALI_PI_197 Register
          672. 14.5.1.2.672  EMIF_CTLCFG_DENALI_PI_198 Register
          673. 14.5.1.2.673  EMIF_CTLCFG_DENALI_PI_199 Register
          674. 14.5.1.2.674  EMIF_CTLCFG_DENALI_PI_200 Register
          675. 14.5.1.2.675  EMIF_CTLCFG_DENALI_PI_201 Register
          676. 14.5.1.2.676  EMIF_CTLCFG_DENALI_PI_202 Register
          677. 14.5.1.2.677  EMIF_CTLCFG_DENALI_PI_203 Register
          678. 14.5.1.2.678  EMIF_CTLCFG_DENALI_PI_204 Register
          679. 14.5.1.2.679  EMIF_CTLCFG_DENALI_PI_205 Register
          680. 14.5.1.2.680  EMIF_CTLCFG_DENALI_PI_206 Register
          681. 14.5.1.2.681  EMIF_CTLCFG_DENALI_PI_207 Register
          682. 14.5.1.2.682  EMIF_CTLCFG_DENALI_PI_208 Register
          683. 14.5.1.2.683  EMIF_CTLCFG_DENALI_PI_209 Register
          684. 14.5.1.2.684  EMIF_CTLCFG_DENALI_PI_210 Register
          685. 14.5.1.2.685  EMIF_CTLCFG_DENALI_PI_211 Register
          686. 14.5.1.2.686  EMIF_CTLCFG_DENALI_PI_212 Register
          687. 14.5.1.2.687  EMIF_CTLCFG_DENALI_PI_213 Register
          688. 14.5.1.2.688  EMIF_CTLCFG_DENALI_PI_214 Register
          689. 14.5.1.2.689  EMIF_CTLCFG_DENALI_PI_215 Register
          690. 14.5.1.2.690  EMIF_CTLCFG_DENALI_PI_216 Register
          691. 14.5.1.2.691  EMIF_CTLCFG_DENALI_PI_217 Register
          692. 14.5.1.2.692  EMIF_CTLCFG_DENALI_PI_218 Register
          693. 14.5.1.2.693  EMIF_CTLCFG_DENALI_PI_219 Register
          694. 14.5.1.2.694  EMIF_CTLCFG_DENALI_PI_220 Register
          695. 14.5.1.2.695  EMIF_CTLCFG_DENALI_PI_221 Register
          696. 14.5.1.2.696  EMIF_CTLCFG_DENALI_PI_222 Register
          697. 14.5.1.2.697  EMIF_CTLCFG_DENALI_PI_223 Register
          698. 14.5.1.2.698  EMIF_CTLCFG_DENALI_PI_224 Register
          699. 14.5.1.2.699  EMIF_CTLCFG_DENALI_PI_225 Register
          700. 14.5.1.2.700  EMIF_CTLCFG_DENALI_PI_226 Register
          701. 14.5.1.2.701  EMIF_CTLCFG_DENALI_PI_227 Register
          702. 14.5.1.2.702  EMIF_CTLCFG_DENALI_PI_228 Register
          703. 14.5.1.2.703  EMIF_CTLCFG_DENALI_PI_229 Register
          704. 14.5.1.2.704  EMIF_CTLCFG_DENALI_PI_230 Register
          705. 14.5.1.2.705  EMIF_CTLCFG_DENALI_PI_231 Register
          706. 14.5.1.2.706  EMIF_CTLCFG_DENALI_PI_232 Register
          707. 14.5.1.2.707  EMIF_CTLCFG_DENALI_PI_233 Register
          708. 14.5.1.2.708  EMIF_CTLCFG_DENALI_PI_234 Register
          709. 14.5.1.2.709  EMIF_CTLCFG_DENALI_PI_235 Register
          710. 14.5.1.2.710  EMIF_CTLCFG_DENALI_PI_236 Register
          711. 14.5.1.2.711  EMIF_CTLCFG_DENALI_PI_237 Register
          712. 14.5.1.2.712  EMIF_CTLCFG_DENALI_PI_238 Register
          713. 14.5.1.2.713  EMIF_CTLCFG_DENALI_PI_239 Register
          714. 14.5.1.2.714  EMIF_CTLCFG_DENALI_PI_240 Register
          715. 14.5.1.2.715  EMIF_CTLCFG_DENALI_PI_241 Register
          716. 14.5.1.2.716  EMIF_CTLCFG_DENALI_PI_242 Register
          717. 14.5.1.2.717  EMIF_CTLCFG_DENALI_PI_243 Register
          718. 14.5.1.2.718  EMIF_CTLCFG_DENALI_PI_244 Register
          719. 14.5.1.2.719  EMIF_CTLCFG_DENALI_PI_245 Register
          720. 14.5.1.2.720  EMIF_CTLCFG_DENALI_PI_246 Register
          721. 14.5.1.2.721  EMIF_CTLCFG_DENALI_PI_247 Register
          722. 14.5.1.2.722  EMIF_CTLCFG_DENALI_PI_248 Register
          723. 14.5.1.2.723  EMIF_CTLCFG_DENALI_PI_249 Register
          724. 14.5.1.2.724  EMIF_CTLCFG_DENALI_PI_250 Register
          725. 14.5.1.2.725  EMIF_CTLCFG_DENALI_PI_251 Register
          726. 14.5.1.2.726  EMIF_CTLCFG_DENALI_PI_252 Register
          727. 14.5.1.2.727  EMIF_CTLCFG_DENALI_PI_253 Register
          728. 14.5.1.2.728  EMIF_CTLCFG_DENALI_PI_254 Register
          729. 14.5.1.2.729  EMIF_CTLCFG_DENALI_PI_255 Register
          730. 14.5.1.2.730  EMIF_CTLCFG_DENALI_PI_256 Register
          731. 14.5.1.2.731  EMIF_CTLCFG_DENALI_PI_257 Register
          732. 14.5.1.2.732  EMIF_CTLCFG_DENALI_PI_258 Register
          733. 14.5.1.2.733  EMIF_CTLCFG_DENALI_PI_259 Register
          734. 14.5.1.2.734  EMIF_CTLCFG_DENALI_PI_260 Register
          735. 14.5.1.2.735  EMIF_CTLCFG_DENALI_PI_261 Register
          736. 14.5.1.2.736  EMIF_CTLCFG_DENALI_PI_262 Register
          737. 14.5.1.2.737  EMIF_CTLCFG_DENALI_PI_263 Register
          738. 14.5.1.2.738  EMIF_CTLCFG_DENALI_PI_264 Register
          739. 14.5.1.2.739  EMIF_CTLCFG_DENALI_PI_265 Register
          740. 14.5.1.2.740  EMIF_CTLCFG_DENALI_PI_266 Register
          741. 14.5.1.2.741  EMIF_CTLCFG_DENALI_PI_267 Register
          742. 14.5.1.2.742  EMIF_CTLCFG_DENALI_PI_268 Register
          743. 14.5.1.2.743  EMIF_CTLCFG_DENALI_PI_269 Register
          744. 14.5.1.2.744  EMIF_CTLCFG_DENALI_PI_270 Register
          745. 14.5.1.2.745  EMIF_CTLCFG_DENALI_PI_271 Register
          746. 14.5.1.2.746  EMIF_CTLCFG_DENALI_PI_272 Register
          747. 14.5.1.2.747  EMIF_CTLCFG_DENALI_PI_273 Register
          748. 14.5.1.2.748  EMIF_CTLCFG_DENALI_PI_274 Register
          749. 14.5.1.2.749  EMIF_CTLCFG_DENALI_PI_275 Register
          750. 14.5.1.2.750  EMIF_CTLCFG_DENALI_PI_276 Register
          751. 14.5.1.2.751  EMIF_CTLCFG_DENALI_PI_277 Register
          752. 14.5.1.2.752  EMIF_CTLCFG_DENALI_PI_278 Register
          753. 14.5.1.2.753  EMIF_CTLCFG_DENALI_PI_279 Register
          754. 14.5.1.2.754  EMIF_CTLCFG_DENALI_PI_280 Register
          755. 14.5.1.2.755  EMIF_CTLCFG_DENALI_PI_281 Register
          756. 14.5.1.2.756  EMIF_CTLCFG_DENALI_PI_282 Register
          757. 14.5.1.2.757  EMIF_CTLCFG_DENALI_PI_283 Register
          758. 14.5.1.2.758  EMIF_CTLCFG_DENALI_PI_284 Register
          759. 14.5.1.2.759  EMIF_CTLCFG_DENALI_PI_285 Register
          760. 14.5.1.2.760  EMIF_CTLCFG_DENALI_PI_286 Register
          761. 14.5.1.2.761  EMIF_CTLCFG_DENALI_PI_287 Register
          762. 14.5.1.2.762  EMIF_CTLCFG_DENALI_PI_288 Register
          763. 14.5.1.2.763  EMIF_CTLCFG_DENALI_PI_289 Register
          764. 14.5.1.2.764  EMIF_CTLCFG_DENALI_PI_290 Register
          765. 14.5.1.2.765  EMIF_CTLCFG_DENALI_PI_291 Register
          766. 14.5.1.2.766  EMIF_CTLCFG_DENALI_PI_292 Register
          767. 14.5.1.2.767  EMIF_CTLCFG_DENALI_PI_293 Register
          768. 14.5.1.2.768  EMIF_CTLCFG_DENALI_PI_294 Register
          769. 14.5.1.2.769  EMIF_CTLCFG_DENALI_PI_295 Register
          770. 14.5.1.2.770  EMIF_CTLCFG_DENALI_PI_296 Register
          771. 14.5.1.2.771  EMIF_CTLCFG_DENALI_PI_297 Register
          772. 14.5.1.2.772  EMIF_CTLCFG_DENALI_PI_298 Register
          773. 14.5.1.2.773  EMIF_CTLCFG_DENALI_PI_299 Register
          774. 14.5.1.2.774  EMIF_CTLCFG_DENALI_PI_300 Register
          775. 14.5.1.2.775  EMIF_CTLCFG_DENALI_PI_301 Register
          776. 14.5.1.2.776  EMIF_CTLCFG_DENALI_PI_302 Register
          777. 14.5.1.2.777  EMIF_CTLCFG_DENALI_PI_303 Register
          778. 14.5.1.2.778  EMIF_CTLCFG_DENALI_PI_304 Register
          779. 14.5.1.2.779  EMIF_CTLCFG_DENALI_PI_305 Register
          780. 14.5.1.2.780  EMIF_CTLCFG_DENALI_PI_306 Register
          781. 14.5.1.2.781  EMIF_CTLCFG_DENALI_PI_307 Register
          782. 14.5.1.2.782  EMIF_CTLCFG_DENALI_PI_308 Register
          783. 14.5.1.2.783  EMIF_CTLCFG_DENALI_PI_309 Register
          784. 14.5.1.2.784  EMIF_CTLCFG_DENALI_PI_310 Register
          785. 14.5.1.2.785  EMIF_CTLCFG_DENALI_PI_311 Register
          786. 14.5.1.2.786  EMIF_CTLCFG_DENALI_PI_312 Register
          787. 14.5.1.2.787  EMIF_CTLCFG_DENALI_PI_313 Register
          788. 14.5.1.2.788  EMIF_CTLCFG_DENALI_PI_314 Register
          789. 14.5.1.2.789  EMIF_CTLCFG_DENALI_PI_315 Register
          790. 14.5.1.2.790  EMIF_CTLCFG_DENALI_PI_316 Register
          791. 14.5.1.2.791  EMIF_CTLCFG_DENALI_PI_317 Register
          792. 14.5.1.2.792  EMIF_CTLCFG_DENALI_PI_318 Register
          793. 14.5.1.2.793  EMIF_CTLCFG_DENALI_PI_319 Register
          794. 14.5.1.2.794  EMIF_CTLCFG_DENALI_PI_320 Register
          795. 14.5.1.2.795  EMIF_CTLCFG_DENALI_PI_321 Register
          796. 14.5.1.2.796  EMIF_CTLCFG_DENALI_PI_322 Register
          797. 14.5.1.2.797  EMIF_CTLCFG_DENALI_PI_323 Register
          798. 14.5.1.2.798  EMIF_CTLCFG_DENALI_PI_324 Register
          799. 14.5.1.2.799  EMIF_CTLCFG_DENALI_PI_325 Register
          800. 14.5.1.2.800  EMIF_CTLCFG_DENALI_PI_326 Register
          801. 14.5.1.2.801  EMIF_CTLCFG_DENALI_PI_327 Register
          802. 14.5.1.2.802  EMIF_CTLCFG_DENALI_PI_328 Register
          803. 14.5.1.2.803  EMIF_CTLCFG_DENALI_PI_329 Register
          804. 14.5.1.2.804  EMIF_CTLCFG_DENALI_PI_330 Register
          805. 14.5.1.2.805  EMIF_CTLCFG_DENALI_PI_331 Register
          806. 14.5.1.2.806  EMIF_CTLCFG_DENALI_PI_332 Register
          807. 14.5.1.2.807  EMIF_CTLCFG_DENALI_PI_333 Register
          808. 14.5.1.2.808  EMIF_CTLCFG_DENALI_PI_334 Register
          809. 14.5.1.2.809  EMIF_CTLCFG_DENALI_PI_335 Register
          810. 14.5.1.2.810  EMIF_CTLCFG_DENALI_PI_336 Register
          811. 14.5.1.2.811  EMIF_CTLCFG_DENALI_PI_337 Register
          812. 14.5.1.2.812  EMIF_CTLCFG_DENALI_PI_338 Register
          813. 14.5.1.2.813  EMIF_CTLCFG_DENALI_PI_339 Register
          814. 14.5.1.2.814  EMIF_CTLCFG_DENALI_PI_340 Register
          815. 14.5.1.2.815  EMIF_CTLCFG_DENALI_PI_341 Register
          816. 14.5.1.2.816  EMIF_CTLCFG_DENALI_PI_342 Register
          817. 14.5.1.2.817  EMIF_CTLCFG_DENALI_PI_343 Register
          818. 14.5.1.2.818  EMIF_CTLCFG_DENALI_PI_344 Register
          819. 14.5.1.2.819  EMIF_CTLCFG_DENALI_PHY_0 Register
          820. 14.5.1.2.820  EMIF_CTLCFG_DENALI_PHY_1 Register
          821. 14.5.1.2.821  EMIF_CTLCFG_DENALI_PHY_2 Register
          822. 14.5.1.2.822  EMIF_CTLCFG_DENALI_PHY_3 Register
          823. 14.5.1.2.823  EMIF_CTLCFG_DENALI_PHY_4 Register
          824. 14.5.1.2.824  EMIF_CTLCFG_DENALI_PHY_5 Register
          825. 14.5.1.2.825  EMIF_CTLCFG_DENALI_PHY_6 Register
          826. 14.5.1.2.826  EMIF_CTLCFG_DENALI_PHY_7 Register
          827. 14.5.1.2.827  EMIF_CTLCFG_DENALI_PHY_8 Register
          828. 14.5.1.2.828  EMIF_CTLCFG_DENALI_PHY_9 Register
          829. 14.5.1.2.829  EMIF_CTLCFG_DENALI_PHY_10 Register
          830. 14.5.1.2.830  EMIF_CTLCFG_DENALI_PHY_11 Register
          831. 14.5.1.2.831  EMIF_CTLCFG_DENALI_PHY_12 Register
          832. 14.5.1.2.832  EMIF_CTLCFG_DENALI_PHY_13 Register
          833. 14.5.1.2.833  EMIF_CTLCFG_DENALI_PHY_14 Register
          834. 14.5.1.2.834  EMIF_CTLCFG_DENALI_PHY_15 Register
          835. 14.5.1.2.835  EMIF_CTLCFG_DENALI_PHY_16 Register
          836. 14.5.1.2.836  EMIF_CTLCFG_DENALI_PHY_17 Register
          837. 14.5.1.2.837  EMIF_CTLCFG_DENALI_PHY_18 Register
          838. 14.5.1.2.838  EMIF_CTLCFG_DENALI_PHY_19 Register
          839. 14.5.1.2.839  EMIF_CTLCFG_DENALI_PHY_20 Register
          840. 14.5.1.2.840  EMIF_CTLCFG_DENALI_PHY_21 Register
          841. 14.5.1.2.841  EMIF_CTLCFG_DENALI_PHY_22 Register
          842. 14.5.1.2.842  EMIF_CTLCFG_DENALI_PHY_23 Register
          843. 14.5.1.2.843  EMIF_CTLCFG_DENALI_PHY_24 Register
          844. 14.5.1.2.844  EMIF_CTLCFG_DENALI_PHY_25 Register
          845. 14.5.1.2.845  EMIF_CTLCFG_DENALI_PHY_26 Register
          846. 14.5.1.2.846  EMIF_CTLCFG_DENALI_PHY_27 Register
          847. 14.5.1.2.847  EMIF_CTLCFG_DENALI_PHY_28 Register
          848. 14.5.1.2.848  EMIF_CTLCFG_DENALI_PHY_29 Register
          849. 14.5.1.2.849  EMIF_CTLCFG_DENALI_PHY_30 Register
          850. 14.5.1.2.850  EMIF_CTLCFG_DENALI_PHY_31 Register
          851. 14.5.1.2.851  EMIF_CTLCFG_DENALI_PHY_32 Register
          852. 14.5.1.2.852  EMIF_CTLCFG_DENALI_PHY_33 Register
          853. 14.5.1.2.853  EMIF_CTLCFG_DENALI_PHY_34 Register
          854. 14.5.1.2.854  EMIF_CTLCFG_DENALI_PHY_35 Register
          855. 14.5.1.2.855  EMIF_CTLCFG_DENALI_PHY_36 Register
          856. 14.5.1.2.856  EMIF_CTLCFG_DENALI_PHY_37 Register
          857. 14.5.1.2.857  EMIF_CTLCFG_DENALI_PHY_38 Register
          858. 14.5.1.2.858  EMIF_CTLCFG_DENALI_PHY_39 Register
          859. 14.5.1.2.859  EMIF_CTLCFG_DENALI_PHY_40 Register
          860. 14.5.1.2.860  EMIF_CTLCFG_DENALI_PHY_41 Register
          861. 14.5.1.2.861  EMIF_CTLCFG_DENALI_PHY_42 Register
          862. 14.5.1.2.862  EMIF_CTLCFG_DENALI_PHY_43 Register
          863. 14.5.1.2.863  EMIF_CTLCFG_DENALI_PHY_44 Register
          864. 14.5.1.2.864  EMIF_CTLCFG_DENALI_PHY_45 Register
          865. 14.5.1.2.865  EMIF_CTLCFG_DENALI_PHY_46 Register
          866. 14.5.1.2.866  EMIF_CTLCFG_DENALI_PHY_47 Register
          867. 14.5.1.2.867  EMIF_CTLCFG_DENALI_PHY_48 Register
          868. 14.5.1.2.868  EMIF_CTLCFG_DENALI_PHY_49 Register
          869. 14.5.1.2.869  EMIF_CTLCFG_DENALI_PHY_50 Register
          870. 14.5.1.2.870  EMIF_CTLCFG_DENALI_PHY_51 Register
          871. 14.5.1.2.871  EMIF_CTLCFG_DENALI_PHY_52 Register
          872. 14.5.1.2.872  EMIF_CTLCFG_DENALI_PHY_53 Register
          873. 14.5.1.2.873  EMIF_CTLCFG_DENALI_PHY_54 Register
          874. 14.5.1.2.874  EMIF_CTLCFG_DENALI_PHY_55 Register
          875. 14.5.1.2.875  EMIF_CTLCFG_DENALI_PHY_56 Register
          876. 14.5.1.2.876  EMIF_CTLCFG_DENALI_PHY_57 Register
          877. 14.5.1.2.877  EMIF_CTLCFG_DENALI_PHY_58 Register
          878. 14.5.1.2.878  EMIF_CTLCFG_DENALI_PHY_59 Register
          879. 14.5.1.2.879  EMIF_CTLCFG_DENALI_PHY_60 Register
          880. 14.5.1.2.880  EMIF_CTLCFG_DENALI_PHY_61 Register
          881. 14.5.1.2.881  EMIF_CTLCFG_DENALI_PHY_62 Register
          882. 14.5.1.2.882  EMIF_CTLCFG_DENALI_PHY_63 Register
          883. 14.5.1.2.883  EMIF_CTLCFG_DENALI_PHY_64 Register
          884. 14.5.1.2.884  EMIF_CTLCFG_DENALI_PHY_65 Register
          885. 14.5.1.2.885  EMIF_CTLCFG_DENALI_PHY_66 Register
          886. 14.5.1.2.886  EMIF_CTLCFG_DENALI_PHY_67 Register
          887. 14.5.1.2.887  EMIF_CTLCFG_DENALI_PHY_68 Register
          888. 14.5.1.2.888  EMIF_CTLCFG_DENALI_PHY_69 Register
          889. 14.5.1.2.889  EMIF_CTLCFG_DENALI_PHY_70 Register
          890. 14.5.1.2.890  EMIF_CTLCFG_DENALI_PHY_71 Register
          891. 14.5.1.2.891  EMIF_CTLCFG_DENALI_PHY_72 Register
          892. 14.5.1.2.892  EMIF_CTLCFG_DENALI_PHY_73 Register
          893. 14.5.1.2.893  EMIF_CTLCFG_DENALI_PHY_74 Register
          894. 14.5.1.2.894  EMIF_CTLCFG_DENALI_PHY_75 Register
          895. 14.5.1.2.895  EMIF_CTLCFG_DENALI_PHY_76 Register
          896. 14.5.1.2.896  EMIF_CTLCFG_DENALI_PHY_77 Register
          897. 14.5.1.2.897  EMIF_CTLCFG_DENALI_PHY_78 Register
          898. 14.5.1.2.898  EMIF_CTLCFG_DENALI_PHY_79 Register
          899. 14.5.1.2.899  EMIF_CTLCFG_DENALI_PHY_80 Register
          900. 14.5.1.2.900  EMIF_CTLCFG_DENALI_PHY_81 Register
          901. 14.5.1.2.901  EMIF_CTLCFG_DENALI_PHY_82 Register
          902. 14.5.1.2.902  EMIF_CTLCFG_DENALI_PHY_83 Register
          903. 14.5.1.2.903  EMIF_CTLCFG_DENALI_PHY_84 Register
          904. 14.5.1.2.904  EMIF_CTLCFG_DENALI_PHY_85 Register
          905. 14.5.1.2.905  EMIF_CTLCFG_DENALI_PHY_86 Register
          906. 14.5.1.2.906  EMIF_CTLCFG_DENALI_PHY_87 Register
          907. 14.5.1.2.907  EMIF_CTLCFG_DENALI_PHY_88 Register
          908. 14.5.1.2.908  EMIF_CTLCFG_DENALI_PHY_89 Register
          909. 14.5.1.2.909  EMIF_CTLCFG_DENALI_PHY_90 Register
          910. 14.5.1.2.910  EMIF_CTLCFG_DENALI_PHY_91 Register
          911. 14.5.1.2.911  EMIF_CTLCFG_DENALI_PHY_92 Register
          912. 14.5.1.2.912  EMIF_CTLCFG_DENALI_PHY_93 Register
          913. 14.5.1.2.913  EMIF_CTLCFG_DENALI_PHY_94 Register
          914. 14.5.1.2.914  EMIF_CTLCFG_DENALI_PHY_95 Register
          915. 14.5.1.2.915  EMIF_CTLCFG_DENALI_PHY_96 Register
          916. 14.5.1.2.916  EMIF_CTLCFG_DENALI_PHY_97 Register
          917. 14.5.1.2.917  EMIF_CTLCFG_DENALI_PHY_98 Register
          918. 14.5.1.2.918  EMIF_CTLCFG_DENALI_PHY_99 Register
          919. 14.5.1.2.919  EMIF_CTLCFG_DENALI_PHY_100 Register
          920. 14.5.1.2.920  EMIF_CTLCFG_DENALI_PHY_101 Register
          921. 14.5.1.2.921  EMIF_CTLCFG_DENALI_PHY_102 Register
          922. 14.5.1.2.922  EMIF_CTLCFG_DENALI_PHY_103 Register
          923. 14.5.1.2.923  EMIF_CTLCFG_DENALI_PHY_104 Register
          924. 14.5.1.2.924  EMIF_CTLCFG_DENALI_PHY_105 Register
          925. 14.5.1.2.925  EMIF_CTLCFG_DENALI_PHY_106 Register
          926. 14.5.1.2.926  EMIF_CTLCFG_DENALI_PHY_107 Register
          927. 14.5.1.2.927  EMIF_CTLCFG_DENALI_PHY_108 Register
          928. 14.5.1.2.928  EMIF_CTLCFG_DENALI_PHY_109 Register
          929. 14.5.1.2.929  EMIF_CTLCFG_DENALI_PHY_110 Register
          930. 14.5.1.2.930  EMIF_CTLCFG_DENALI_PHY_111 Register
          931. 14.5.1.2.931  EMIF_CTLCFG_DENALI_PHY_112 Register
          932. 14.5.1.2.932  EMIF_CTLCFG_DENALI_PHY_113 Register
          933. 14.5.1.2.933  EMIF_CTLCFG_DENALI_PHY_114 Register
          934. 14.5.1.2.934  EMIF_CTLCFG_DENALI_PHY_115 Register
          935. 14.5.1.2.935  EMIF_CTLCFG_DENALI_PHY_116 Register
          936. 14.5.1.2.936  EMIF_CTLCFG_DENALI_PHY_117 Register
          937. 14.5.1.2.937  EMIF_CTLCFG_DENALI_PHY_118 Register
          938. 14.5.1.2.938  EMIF_CTLCFG_DENALI_PHY_119 Register
          939. 14.5.1.2.939  EMIF_CTLCFG_DENALI_PHY_120 Register
          940. 14.5.1.2.940  EMIF_CTLCFG_DENALI_PHY_121 Register
          941. 14.5.1.2.941  EMIF_CTLCFG_DENALI_PHY_122 Register
          942. 14.5.1.2.942  EMIF_CTLCFG_DENALI_PHY_123 Register
          943. 14.5.1.2.943  EMIF_CTLCFG_DENALI_PHY_124 Register
          944. 14.5.1.2.944  EMIF_CTLCFG_DENALI_PHY_125 Register
          945. 14.5.1.2.945  EMIF_CTLCFG_DENALI_PHY_256 Register
          946. 14.5.1.2.946  EMIF_CTLCFG_DENALI_PHY_257 Register
          947. 14.5.1.2.947  EMIF_CTLCFG_DENALI_PHY_258 Register
          948. 14.5.1.2.948  EMIF_CTLCFG_DENALI_PHY_259 Register
          949. 14.5.1.2.949  EMIF_CTLCFG_DENALI_PHY_260 Register
          950. 14.5.1.2.950  EMIF_CTLCFG_DENALI_PHY_261 Register
          951. 14.5.1.2.951  EMIF_CTLCFG_DENALI_PHY_262 Register
          952. 14.5.1.2.952  EMIF_CTLCFG_DENALI_PHY_263 Register
          953. 14.5.1.2.953  EMIF_CTLCFG_DENALI_PHY_264 Register
          954. 14.5.1.2.954  EMIF_CTLCFG_DENALI_PHY_265 Register
          955. 14.5.1.2.955  EMIF_CTLCFG_DENALI_PHY_266 Register
          956. 14.5.1.2.956  EMIF_CTLCFG_DENALI_PHY_267 Register
          957. 14.5.1.2.957  EMIF_CTLCFG_DENALI_PHY_268 Register
          958. 14.5.1.2.958  EMIF_CTLCFG_DENALI_PHY_269 Register
          959. 14.5.1.2.959  EMIF_CTLCFG_DENALI_PHY_270 Register
          960. 14.5.1.2.960  EMIF_CTLCFG_DENALI_PHY_271 Register
          961. 14.5.1.2.961  EMIF_CTLCFG_DENALI_PHY_272 Register
          962. 14.5.1.2.962  EMIF_CTLCFG_DENALI_PHY_273 Register
          963. 14.5.1.2.963  EMIF_CTLCFG_DENALI_PHY_274 Register
          964. 14.5.1.2.964  EMIF_CTLCFG_DENALI_PHY_275 Register
          965. 14.5.1.2.965  EMIF_CTLCFG_DENALI_PHY_276 Register
          966. 14.5.1.2.966  EMIF_CTLCFG_DENALI_PHY_277 Register
          967. 14.5.1.2.967  EMIF_CTLCFG_DENALI_PHY_278 Register
          968. 14.5.1.2.968  EMIF_CTLCFG_DENALI_PHY_279 Register
          969. 14.5.1.2.969  EMIF_CTLCFG_DENALI_PHY_280 Register
          970. 14.5.1.2.970  EMIF_CTLCFG_DENALI_PHY_281 Register
          971. 14.5.1.2.971  EMIF_CTLCFG_DENALI_PHY_282 Register
          972. 14.5.1.2.972  EMIF_CTLCFG_DENALI_PHY_283 Register
          973. 14.5.1.2.973  EMIF_CTLCFG_DENALI_PHY_284 Register
          974. 14.5.1.2.974  EMIF_CTLCFG_DENALI_PHY_285 Register
          975. 14.5.1.2.975  EMIF_CTLCFG_DENALI_PHY_286 Register
          976. 14.5.1.2.976  EMIF_CTLCFG_DENALI_PHY_287 Register
          977. 14.5.1.2.977  EMIF_CTLCFG_DENALI_PHY_288 Register
          978. 14.5.1.2.978  EMIF_CTLCFG_DENALI_PHY_289 Register
          979. 14.5.1.2.979  EMIF_CTLCFG_DENALI_PHY_290 Register
          980. 14.5.1.2.980  EMIF_CTLCFG_DENALI_PHY_291 Register
          981. 14.5.1.2.981  EMIF_CTLCFG_DENALI_PHY_292 Register
          982. 14.5.1.2.982  EMIF_CTLCFG_DENALI_PHY_293 Register
          983. 14.5.1.2.983  EMIF_CTLCFG_DENALI_PHY_294 Register
          984. 14.5.1.2.984  EMIF_CTLCFG_DENALI_PHY_295 Register
          985. 14.5.1.2.985  EMIF_CTLCFG_DENALI_PHY_296 Register
          986. 14.5.1.2.986  EMIF_CTLCFG_DENALI_PHY_297 Register
          987. 14.5.1.2.987  EMIF_CTLCFG_DENALI_PHY_298 Register
          988. 14.5.1.2.988  EMIF_CTLCFG_DENALI_PHY_299 Register
          989. 14.5.1.2.989  EMIF_CTLCFG_DENALI_PHY_300 Register
          990. 14.5.1.2.990  EMIF_CTLCFG_DENALI_PHY_301 Register
          991. 14.5.1.2.991  EMIF_CTLCFG_DENALI_PHY_302 Register
          992. 14.5.1.2.992  EMIF_CTLCFG_DENALI_PHY_303 Register
          993. 14.5.1.2.993  EMIF_CTLCFG_DENALI_PHY_304 Register
          994. 14.5.1.2.994  EMIF_CTLCFG_DENALI_PHY_305 Register
          995. 14.5.1.2.995  EMIF_CTLCFG_DENALI_PHY_306 Register
          996. 14.5.1.2.996  EMIF_CTLCFG_DENALI_PHY_307 Register
          997. 14.5.1.2.997  EMIF_CTLCFG_DENALI_PHY_308 Register
          998. 14.5.1.2.998  EMIF_CTLCFG_DENALI_PHY_309 Register
          999. 14.5.1.2.999  EMIF_CTLCFG_DENALI_PHY_310 Register
          1000. 14.5.1.2.1000 EMIF_CTLCFG_DENALI_PHY_311 Register
          1001. 14.5.1.2.1001 EMIF_CTLCFG_DENALI_PHY_312 Register
          1002. 14.5.1.2.1002 EMIF_CTLCFG_DENALI_PHY_313 Register
          1003. 14.5.1.2.1003 EMIF_CTLCFG_DENALI_PHY_314 Register
          1004. 14.5.1.2.1004 EMIF_CTLCFG_DENALI_PHY_315 Register
          1005. 14.5.1.2.1005 EMIF_CTLCFG_DENALI_PHY_316 Register
          1006. 14.5.1.2.1006 EMIF_CTLCFG_DENALI_PHY_317 Register
          1007. 14.5.1.2.1007 EMIF_CTLCFG_DENALI_PHY_318 Register
          1008. 14.5.1.2.1008 EMIF_CTLCFG_DENALI_PHY_319 Register
          1009. 14.5.1.2.1009 EMIF_CTLCFG_DENALI_PHY_320 Register
          1010. 14.5.1.2.1010 EMIF_CTLCFG_DENALI_PHY_321 Register
          1011. 14.5.1.2.1011 EMIF_CTLCFG_DENALI_PHY_322 Register
          1012. 14.5.1.2.1012 EMIF_CTLCFG_DENALI_PHY_323 Register
          1013. 14.5.1.2.1013 EMIF_CTLCFG_DENALI_PHY_324 Register
          1014. 14.5.1.2.1014 EMIF_CTLCFG_DENALI_PHY_325 Register
          1015. 14.5.1.2.1015 EMIF_CTLCFG_DENALI_PHY_326 Register
          1016. 14.5.1.2.1016 EMIF_CTLCFG_DENALI_PHY_327 Register
          1017. 14.5.1.2.1017 EMIF_CTLCFG_DENALI_PHY_328 Register
          1018. 14.5.1.2.1018 EMIF_CTLCFG_DENALI_PHY_329 Register
          1019. 14.5.1.2.1019 EMIF_CTLCFG_DENALI_PHY_330 Register
          1020. 14.5.1.2.1020 EMIF_CTLCFG_DENALI_PHY_331 Register
          1021. 14.5.1.2.1021 EMIF_CTLCFG_DENALI_PHY_332 Register
          1022. 14.5.1.2.1022 EMIF_CTLCFG_DENALI_PHY_333 Register
          1023. 14.5.1.2.1023 EMIF_CTLCFG_DENALI_PHY_334 Register
          1024. 14.5.1.2.1024 EMIF_CTLCFG_DENALI_PHY_335 Register
          1025. 14.5.1.2.1025 EMIF_CTLCFG_DENALI_PHY_336 Register
          1026. 14.5.1.2.1026 EMIF_CTLCFG_DENALI_PHY_337 Register
          1027. 14.5.1.2.1027 EMIF_CTLCFG_DENALI_PHY_338 Register
          1028. 14.5.1.2.1028 EMIF_CTLCFG_DENALI_PHY_339 Register
          1029. 14.5.1.2.1029 EMIF_CTLCFG_DENALI_PHY_340 Register
          1030. 14.5.1.2.1030 EMIF_CTLCFG_DENALI_PHY_341 Register
          1031. 14.5.1.2.1031 EMIF_CTLCFG_DENALI_PHY_342 Register
          1032. 14.5.1.2.1032 EMIF_CTLCFG_DENALI_PHY_343 Register
          1033. 14.5.1.2.1033 EMIF_CTLCFG_DENALI_PHY_344 Register
          1034. 14.5.1.2.1034 EMIF_CTLCFG_DENALI_PHY_345 Register
          1035. 14.5.1.2.1035 EMIF_CTLCFG_DENALI_PHY_346 Register
          1036. 14.5.1.2.1036 EMIF_CTLCFG_DENALI_PHY_347 Register
          1037. 14.5.1.2.1037 EMIF_CTLCFG_DENALI_PHY_348 Register
          1038. 14.5.1.2.1038 EMIF_CTLCFG_DENALI_PHY_349 Register
          1039. 14.5.1.2.1039 EMIF_CTLCFG_DENALI_PHY_350 Register
          1040. 14.5.1.2.1040 EMIF_CTLCFG_DENALI_PHY_351 Register
          1041. 14.5.1.2.1041 EMIF_CTLCFG_DENALI_PHY_352 Register
          1042. 14.5.1.2.1042 EMIF_CTLCFG_DENALI_PHY_353 Register
          1043. 14.5.1.2.1043 EMIF_CTLCFG_DENALI_PHY_354 Register
          1044. 14.5.1.2.1044 EMIF_CTLCFG_DENALI_PHY_355 Register
          1045. 14.5.1.2.1045 EMIF_CTLCFG_DENALI_PHY_356 Register
          1046. 14.5.1.2.1046 EMIF_CTLCFG_DENALI_PHY_357 Register
          1047. 14.5.1.2.1047 EMIF_CTLCFG_DENALI_PHY_358 Register
          1048. 14.5.1.2.1048 EMIF_CTLCFG_DENALI_PHY_359 Register
          1049. 14.5.1.2.1049 EMIF_CTLCFG_DENALI_PHY_360 Register
          1050. 14.5.1.2.1050 EMIF_CTLCFG_DENALI_PHY_361 Register
          1051. 14.5.1.2.1051 EMIF_CTLCFG_DENALI_PHY_362 Register
          1052. 14.5.1.2.1052 EMIF_CTLCFG_DENALI_PHY_363 Register
          1053. 14.5.1.2.1053 EMIF_CTLCFG_DENALI_PHY_364 Register
          1054. 14.5.1.2.1054 EMIF_CTLCFG_DENALI_PHY_365 Register
          1055. 14.5.1.2.1055 EMIF_CTLCFG_DENALI_PHY_366 Register
          1056. 14.5.1.2.1056 EMIF_CTLCFG_DENALI_PHY_367 Register
          1057. 14.5.1.2.1057 EMIF_CTLCFG_DENALI_PHY_368 Register
          1058. 14.5.1.2.1058 EMIF_CTLCFG_DENALI_PHY_369 Register
          1059. 14.5.1.2.1059 EMIF_CTLCFG_DENALI_PHY_370 Register
          1060. 14.5.1.2.1060 EMIF_CTLCFG_DENALI_PHY_371 Register
          1061. 14.5.1.2.1061 EMIF_CTLCFG_DENALI_PHY_372 Register
          1062. 14.5.1.2.1062 EMIF_CTLCFG_DENALI_PHY_373 Register
          1063. 14.5.1.2.1063 EMIF_CTLCFG_DENALI_PHY_374 Register
          1064. 14.5.1.2.1064 EMIF_CTLCFG_DENALI_PHY_375 Register
          1065. 14.5.1.2.1065 EMIF_CTLCFG_DENALI_PHY_376 Register
          1066. 14.5.1.2.1066 EMIF_CTLCFG_DENALI_PHY_377 Register
          1067. 14.5.1.2.1067 EMIF_CTLCFG_DENALI_PHY_378 Register
          1068. 14.5.1.2.1068 EMIF_CTLCFG_DENALI_PHY_379 Register
          1069. 14.5.1.2.1069 EMIF_CTLCFG_DENALI_PHY_380 Register
          1070. 14.5.1.2.1070 EMIF_CTLCFG_DENALI_PHY_381 Register
          1071. 14.5.1.2.1071 EMIF_CTLCFG_DENALI_PHY_512 Register
          1072. 14.5.1.2.1072 EMIF_CTLCFG_DENALI_PHY_513 Register
          1073. 14.5.1.2.1073 EMIF_CTLCFG_DENALI_PHY_514 Register
          1074. 14.5.1.2.1074 EMIF_CTLCFG_DENALI_PHY_515 Register
          1075. 14.5.1.2.1075 EMIF_CTLCFG_DENALI_PHY_516 Register
          1076. 14.5.1.2.1076 EMIF_CTLCFG_DENALI_PHY_517 Register
          1077. 14.5.1.2.1077 EMIF_CTLCFG_DENALI_PHY_518 Register
          1078. 14.5.1.2.1078 EMIF_CTLCFG_DENALI_PHY_519 Register
          1079. 14.5.1.2.1079 EMIF_CTLCFG_DENALI_PHY_520 Register
          1080. 14.5.1.2.1080 EMIF_CTLCFG_DENALI_PHY_521 Register
          1081. 14.5.1.2.1081 EMIF_CTLCFG_DENALI_PHY_522 Register
          1082. 14.5.1.2.1082 EMIF_CTLCFG_DENALI_PHY_523 Register
          1083. 14.5.1.2.1083 EMIF_CTLCFG_DENALI_PHY_524 Register
          1084. 14.5.1.2.1084 EMIF_CTLCFG_DENALI_PHY_525 Register
          1085. 14.5.1.2.1085 EMIF_CTLCFG_DENALI_PHY_526 Register
          1086. 14.5.1.2.1086 EMIF_CTLCFG_DENALI_PHY_527 Register
          1087. 14.5.1.2.1087 EMIF_CTLCFG_DENALI_PHY_528 Register
          1088. 14.5.1.2.1088 EMIF_CTLCFG_DENALI_PHY_529 Register
          1089. 14.5.1.2.1089 EMIF_CTLCFG_DENALI_PHY_530 Register
          1090. 14.5.1.2.1090 EMIF_CTLCFG_DENALI_PHY_531 Register
          1091. 14.5.1.2.1091 EMIF_CTLCFG_DENALI_PHY_532 Register
          1092. 14.5.1.2.1092 EMIF_CTLCFG_DENALI_PHY_533 Register
          1093. 14.5.1.2.1093 EMIF_CTLCFG_DENALI_PHY_534 Register
          1094. 14.5.1.2.1094 EMIF_CTLCFG_DENALI_PHY_535 Register
          1095. 14.5.1.2.1095 EMIF_CTLCFG_DENALI_PHY_536 Register
          1096. 14.5.1.2.1096 EMIF_CTLCFG_DENALI_PHY_537 Register
          1097. 14.5.1.2.1097 EMIF_CTLCFG_DENALI_PHY_538 Register
          1098. 14.5.1.2.1098 EMIF_CTLCFG_DENALI_PHY_539 Register
          1099. 14.5.1.2.1099 EMIF_CTLCFG_DENALI_PHY_540 Register
          1100. 14.5.1.2.1100 EMIF_CTLCFG_DENALI_PHY_541 Register
          1101. 14.5.1.2.1101 EMIF_CTLCFG_DENALI_PHY_542 Register
          1102. 14.5.1.2.1102 EMIF_CTLCFG_DENALI_PHY_543 Register
          1103. 14.5.1.2.1103 EMIF_CTLCFG_DENALI_PHY_544 Register
          1104. 14.5.1.2.1104 EMIF_CTLCFG_DENALI_PHY_545 Register
          1105. 14.5.1.2.1105 EMIF_CTLCFG_DENALI_PHY_546 Register
          1106. 14.5.1.2.1106 EMIF_CTLCFG_DENALI_PHY_547 Register
          1107. 14.5.1.2.1107 EMIF_CTLCFG_DENALI_PHY_548 Register
          1108. 14.5.1.2.1108 EMIF_CTLCFG_DENALI_PHY_549 Register
          1109. 14.5.1.2.1109 EMIF_CTLCFG_DENALI_PHY_550 Register
          1110. 14.5.1.2.1110 EMIF_CTLCFG_DENALI_PHY_551 Register
          1111. 14.5.1.2.1111 EMIF_CTLCFG_DENALI_PHY_552 Register
          1112. 14.5.1.2.1112 EMIF_CTLCFG_DENALI_PHY_553 Register
          1113. 14.5.1.2.1113 EMIF_CTLCFG_DENALI_PHY_554 Register
          1114. 14.5.1.2.1114 EMIF_CTLCFG_DENALI_PHY_768 Register
          1115. 14.5.1.2.1115 EMIF_CTLCFG_DENALI_PHY_769 Register
          1116. 14.5.1.2.1116 EMIF_CTLCFG_DENALI_PHY_770 Register
          1117. 14.5.1.2.1117 EMIF_CTLCFG_DENALI_PHY_771 Register
          1118. 14.5.1.2.1118 EMIF_CTLCFG_DENALI_PHY_772 Register
          1119. 14.5.1.2.1119 EMIF_CTLCFG_DENALI_PHY_773 Register
          1120. 14.5.1.2.1120 EMIF_CTLCFG_DENALI_PHY_774 Register
          1121. 14.5.1.2.1121 EMIF_CTLCFG_DENALI_PHY_775 Register
          1122. 14.5.1.2.1122 EMIF_CTLCFG_DENALI_PHY_776 Register
          1123. 14.5.1.2.1123 EMIF_CTLCFG_DENALI_PHY_777 Register
          1124. 14.5.1.2.1124 EMIF_CTLCFG_DENALI_PHY_778 Register
          1125. 14.5.1.2.1125 EMIF_CTLCFG_DENALI_PHY_779 Register
          1126. 14.5.1.2.1126 EMIF_CTLCFG_DENALI_PHY_780 Register
          1127. 14.5.1.2.1127 EMIF_CTLCFG_DENALI_PHY_781 Register
          1128. 14.5.1.2.1128 EMIF_CTLCFG_DENALI_PHY_782 Register
          1129. 14.5.1.2.1129 EMIF_CTLCFG_DENALI_PHY_783 Register
          1130. 14.5.1.2.1130 EMIF_CTLCFG_DENALI_PHY_784 Register
          1131. 14.5.1.2.1131 EMIF_CTLCFG_DENALI_PHY_785 Register
          1132. 14.5.1.2.1132 EMIF_CTLCFG_DENALI_PHY_786 Register
          1133. 14.5.1.2.1133 EMIF_CTLCFG_DENALI_PHY_787 Register
          1134. 14.5.1.2.1134 EMIF_CTLCFG_DENALI_PHY_788 Register
          1135. 14.5.1.2.1135 EMIF_CTLCFG_DENALI_PHY_789 Register
          1136. 14.5.1.2.1136 EMIF_CTLCFG_DENALI_PHY_790 Register
          1137. 14.5.1.2.1137 EMIF_CTLCFG_DENALI_PHY_791 Register
          1138. 14.5.1.2.1138 EMIF_CTLCFG_DENALI_PHY_792 Register
          1139. 14.5.1.2.1139 EMIF_CTLCFG_DENALI_PHY_793 Register
          1140. 14.5.1.2.1140 EMIF_CTLCFG_DENALI_PHY_794 Register
          1141. 14.5.1.2.1141 EMIF_CTLCFG_DENALI_PHY_795 Register
          1142. 14.5.1.2.1142 EMIF_CTLCFG_DENALI_PHY_796 Register
          1143. 14.5.1.2.1143 EMIF_CTLCFG_DENALI_PHY_797 Register
          1144. 14.5.1.2.1144 EMIF_CTLCFG_DENALI_PHY_798 Register
          1145. 14.5.1.2.1145 EMIF_CTLCFG_DENALI_PHY_799 Register
          1146. 14.5.1.2.1146 EMIF_CTLCFG_DENALI_PHY_800 Register
          1147. 14.5.1.2.1147 EMIF_CTLCFG_DENALI_PHY_801 Register
          1148. 14.5.1.2.1148 EMIF_CTLCFG_DENALI_PHY_802 Register
          1149. 14.5.1.2.1149 EMIF_CTLCFG_DENALI_PHY_803 Register
          1150. 14.5.1.2.1150 EMIF_CTLCFG_DENALI_PHY_804 Register
          1151. 14.5.1.2.1151 EMIF_CTLCFG_DENALI_PHY_805 Register
          1152. 14.5.1.2.1152 EMIF_CTLCFG_DENALI_PHY_806 Register
          1153. 14.5.1.2.1153 EMIF_CTLCFG_DENALI_PHY_807 Register
          1154. 14.5.1.2.1154 EMIF_CTLCFG_DENALI_PHY_808 Register
          1155. 14.5.1.2.1155 EMIF_CTLCFG_DENALI_PHY_809 Register
          1156. 14.5.1.2.1156 EMIF_CTLCFG_DENALI_PHY_810 Register
          1157. 14.5.1.2.1157 EMIF_CTLCFG_DENALI_PHY_1024 Register
          1158. 14.5.1.2.1158 EMIF_CTLCFG_DENALI_PHY_1025 Register
          1159. 14.5.1.2.1159 EMIF_CTLCFG_DENALI_PHY_1026 Register
          1160. 14.5.1.2.1160 EMIF_CTLCFG_DENALI_PHY_1027 Register
          1161. 14.5.1.2.1161 EMIF_CTLCFG_DENALI_PHY_1028 Register
          1162. 14.5.1.2.1162 EMIF_CTLCFG_DENALI_PHY_1029 Register
          1163. 14.5.1.2.1163 EMIF_CTLCFG_DENALI_PHY_1030 Register
          1164. 14.5.1.2.1164 EMIF_CTLCFG_DENALI_PHY_1031 Register
          1165. 14.5.1.2.1165 EMIF_CTLCFG_DENALI_PHY_1032 Register
          1166. 14.5.1.2.1166 EMIF_CTLCFG_DENALI_PHY_1033 Register
          1167. 14.5.1.2.1167 EMIF_CTLCFG_DENALI_PHY_1034 Register
          1168. 14.5.1.2.1168 EMIF_CTLCFG_DENALI_PHY_1035 Register
          1169. 14.5.1.2.1169 EMIF_CTLCFG_DENALI_PHY_1036 Register
          1170. 14.5.1.2.1170 EMIF_CTLCFG_DENALI_PHY_1037 Register
          1171. 14.5.1.2.1171 EMIF_CTLCFG_DENALI_PHY_1038 Register
          1172. 14.5.1.2.1172 EMIF_CTLCFG_DENALI_PHY_1039 Register
          1173. 14.5.1.2.1173 EMIF_CTLCFG_DENALI_PHY_1040 Register
          1174. 14.5.1.2.1174 EMIF_CTLCFG_DENALI_PHY_1041 Register
          1175. 14.5.1.2.1175 EMIF_CTLCFG_DENALI_PHY_1042 Register
          1176. 14.5.1.2.1176 EMIF_CTLCFG_DENALI_PHY_1043 Register
          1177. 14.5.1.2.1177 EMIF_CTLCFG_DENALI_PHY_1044 Register
          1178. 14.5.1.2.1178 EMIF_CTLCFG_DENALI_PHY_1045 Register
          1179. 14.5.1.2.1179 EMIF_CTLCFG_DENALI_PHY_1046 Register
          1180. 14.5.1.2.1180 EMIF_CTLCFG_DENALI_PHY_1047 Register
          1181. 14.5.1.2.1181 EMIF_CTLCFG_DENALI_PHY_1048 Register
          1182. 14.5.1.2.1182 EMIF_CTLCFG_DENALI_PHY_1049 Register
          1183. 14.5.1.2.1183 EMIF_CTLCFG_DENALI_PHY_1050 Register
          1184. 14.5.1.2.1184 EMIF_CTLCFG_DENALI_PHY_1051 Register
          1185. 14.5.1.2.1185 EMIF_CTLCFG_DENALI_PHY_1052 Register
          1186. 14.5.1.2.1186 EMIF_CTLCFG_DENALI_PHY_1053 Register
          1187. 14.5.1.2.1187 EMIF_CTLCFG_DENALI_PHY_1054 Register
          1188. 14.5.1.2.1188 EMIF_CTLCFG_DENALI_PHY_1055 Register
          1189. 14.5.1.2.1189 EMIF_CTLCFG_DENALI_PHY_1056 Register
          1190. 14.5.1.2.1190 EMIF_CTLCFG_DENALI_PHY_1057 Register
          1191. 14.5.1.2.1191 EMIF_CTLCFG_DENALI_PHY_1058 Register
          1192. 14.5.1.2.1192 EMIF_CTLCFG_DENALI_PHY_1059 Register
          1193. 14.5.1.2.1193 EMIF_CTLCFG_DENALI_PHY_1060 Register
          1194. 14.5.1.2.1194 EMIF_CTLCFG_DENALI_PHY_1061 Register
          1195. 14.5.1.2.1195 EMIF_CTLCFG_DENALI_PHY_1062 Register
          1196. 14.5.1.2.1196 EMIF_CTLCFG_DENALI_PHY_1063 Register
          1197. 14.5.1.2.1197 EMIF_CTLCFG_DENALI_PHY_1064 Register
          1198. 14.5.1.2.1198 EMIF_CTLCFG_DENALI_PHY_1065 Register
          1199. 14.5.1.2.1199 EMIF_CTLCFG_DENALI_PHY_1066 Register
          1200. 14.5.1.2.1200 EMIF_CTLCFG_DENALI_PHY_1280 Register
          1201. 14.5.1.2.1201 EMIF_CTLCFG_DENALI_PHY_1281 Register
          1202. 14.5.1.2.1202 EMIF_CTLCFG_DENALI_PHY_1282 Register
          1203. 14.5.1.2.1203 EMIF_CTLCFG_DENALI_PHY_1283 Register
          1204. 14.5.1.2.1204 EMIF_CTLCFG_DENALI_PHY_1284 Register
          1205. 14.5.1.2.1205 EMIF_CTLCFG_DENALI_PHY_1285 Register
          1206. 14.5.1.2.1206 EMIF_CTLCFG_DENALI_PHY_1286 Register
          1207. 14.5.1.2.1207 EMIF_CTLCFG_DENALI_PHY_1287 Register
          1208. 14.5.1.2.1208 EMIF_CTLCFG_DENALI_PHY_1288 Register
          1209. 14.5.1.2.1209 EMIF_CTLCFG_DENALI_PHY_1289 Register
          1210. 14.5.1.2.1210 EMIF_CTLCFG_DENALI_PHY_1290 Register
          1211. 14.5.1.2.1211 EMIF_CTLCFG_DENALI_PHY_1291 Register
          1212. 14.5.1.2.1212 EMIF_CTLCFG_DENALI_PHY_1292 Register
          1213. 14.5.1.2.1213 EMIF_CTLCFG_DENALI_PHY_1293 Register
          1214. 14.5.1.2.1214 EMIF_CTLCFG_DENALI_PHY_1294 Register
          1215. 14.5.1.2.1215 EMIF_CTLCFG_DENALI_PHY_1295 Register
          1216. 14.5.1.2.1216 EMIF_CTLCFG_DENALI_PHY_1296 Register
          1217. 14.5.1.2.1217 EMIF_CTLCFG_DENALI_PHY_1297 Register
          1218. 14.5.1.2.1218 EMIF_CTLCFG_DENALI_PHY_1298 Register
          1219. 14.5.1.2.1219 EMIF_CTLCFG_DENALI_PHY_1299 Register
          1220. 14.5.1.2.1220 EMIF_CTLCFG_DENALI_PHY_1300 Register
          1221. 14.5.1.2.1221 EMIF_CTLCFG_DENALI_PHY_1301 Register
          1222. 14.5.1.2.1222 EMIF_CTLCFG_DENALI_PHY_1302 Register
          1223. 14.5.1.2.1223 EMIF_CTLCFG_DENALI_PHY_1303 Register
          1224. 14.5.1.2.1224 EMIF_CTLCFG_DENALI_PHY_1304 Register
          1225. 14.5.1.2.1225 EMIF_CTLCFG_DENALI_PHY_1305 Register
          1226. 14.5.1.2.1226 EMIF_CTLCFG_DENALI_PHY_1306 Register
          1227. 14.5.1.2.1227 EMIF_CTLCFG_DENALI_PHY_1307 Register
          1228. 14.5.1.2.1228 EMIF_CTLCFG_DENALI_PHY_1308 Register
          1229. 14.5.1.2.1229 EMIF_CTLCFG_DENALI_PHY_1309 Register
          1230. 14.5.1.2.1230 EMIF_CTLCFG_DENALI_PHY_1310 Register
          1231. 14.5.1.2.1231 EMIF_CTLCFG_DENALI_PHY_1311 Register
          1232. 14.5.1.2.1232 EMIF_CTLCFG_DENALI_PHY_1312 Register
          1233. 14.5.1.2.1233 EMIF_CTLCFG_DENALI_PHY_1313 Register
          1234. 14.5.1.2.1234 EMIF_CTLCFG_DENALI_PHY_1314 Register
          1235. 14.5.1.2.1235 EMIF_CTLCFG_DENALI_PHY_1315 Register
          1236. 14.5.1.2.1236 EMIF_CTLCFG_DENALI_PHY_1316 Register
          1237. 14.5.1.2.1237 EMIF_CTLCFG_DENALI_PHY_1317 Register
          1238. 14.5.1.2.1238 EMIF_CTLCFG_DENALI_PHY_1318 Register
          1239. 14.5.1.2.1239 EMIF_CTLCFG_DENALI_PHY_1319 Register
          1240. 14.5.1.2.1240 EMIF_CTLCFG_DENALI_PHY_1320 Register
          1241. 14.5.1.2.1241 EMIF_CTLCFG_DENALI_PHY_1321 Register
          1242. 14.5.1.2.1242 EMIF_CTLCFG_DENALI_PHY_1322 Register
          1243. 14.5.1.2.1243 EMIF_CTLCFG_DENALI_PHY_1323 Register
          1244. 14.5.1.2.1244 EMIF_CTLCFG_DENALI_PHY_1324 Register
          1245. 14.5.1.2.1245 EMIF_CTLCFG_DENALI_PHY_1325 Register
          1246. 14.5.1.2.1246 EMIF_CTLCFG_DENALI_PHY_1326 Register
          1247. 14.5.1.2.1247 EMIF_CTLCFG_DENALI_PHY_1327 Register
          1248. 14.5.1.2.1248 EMIF_CTLCFG_DENALI_PHY_1328 Register
          1249. 14.5.1.2.1249 EMIF_CTLCFG_DENALI_PHY_1329 Register
          1250. 14.5.1.2.1250 EMIF_CTLCFG_DENALI_PHY_1330 Register
          1251. 14.5.1.2.1251 EMIF_CTLCFG_DENALI_PHY_1331 Register
          1252. 14.5.1.2.1252 EMIF_CTLCFG_DENALI_PHY_1332 Register
          1253. 14.5.1.2.1253 EMIF_CTLCFG_DENALI_PHY_1333 Register
          1254. 14.5.1.2.1254 EMIF_CTLCFG_DENALI_PHY_1334 Register
          1255. 14.5.1.2.1255 EMIF_CTLCFG_DENALI_PHY_1335 Register
          1256. 14.5.1.2.1256 EMIF_CTLCFG_DENALI_PHY_1336 Register
          1257. 14.5.1.2.1257 EMIF_CTLCFG_DENALI_PHY_1337 Register
          1258. 14.5.1.2.1258 EMIF_CTLCFG_DENALI_PHY_1338 Register
          1259. 14.5.1.2.1259 EMIF_CTLCFG_DENALI_PHY_1339 Register
          1260. 14.5.1.2.1260 EMIF_CTLCFG_DENALI_PHY_1340 Register
          1261. 14.5.1.2.1261 EMIF_CTLCFG_DENALI_PHY_1341 Register
          1262. 14.5.1.2.1262 EMIF_CTLCFG_DENALI_PHY_1342 Register
          1263. 14.5.1.2.1263 EMIF_CTLCFG_DENALI_PHY_1343 Register
          1264. 14.5.1.2.1264 EMIF_CTLCFG_DENALI_PHY_1344 Register
          1265. 14.5.1.2.1265 EMIF_CTLCFG_DENALI_PHY_1345 Register
          1266. 14.5.1.2.1266 EMIF_CTLCFG_DENALI_PHY_1346 Register
          1267. 14.5.1.2.1267 EMIF_CTLCFG_DENALI_PHY_1347 Register
          1268. 14.5.1.2.1268 EMIF_CTLCFG_DENALI_PHY_1348 Register
          1269. 14.5.1.2.1269 EMIF_CTLCFG_DENALI_PHY_1349 Register
          1270. 14.5.1.2.1270 EMIF_CTLCFG_DENALI_PHY_1350 Register
          1271. 14.5.1.2.1271 EMIF_CTLCFG_DENALI_PHY_1351 Register
          1272. 14.5.1.2.1272 EMIF_CTLCFG_DENALI_PHY_1352 Register
          1273. 14.5.1.2.1273 EMIF_CTLCFG_DENALI_PHY_1353 Register
          1274. 14.5.1.2.1274 EMIF_CTLCFG_DENALI_PHY_1354 Register
          1275. 14.5.1.2.1275 EMIF_CTLCFG_DENALI_PHY_1355 Register
          1276. 14.5.1.2.1276 EMIF_CTLCFG_DENALI_PHY_1356 Register
          1277. 14.5.1.2.1277 EMIF_CTLCFG_DENALI_PHY_1357 Register
          1278. 14.5.1.2.1278 EMIF_CTLCFG_DENALI_PHY_1358 Register
          1279. 14.5.1.2.1279 EMIF_CTLCFG_DENALI_PHY_1359 Register
          1280. 14.5.1.2.1280 EMIF_CTLCFG_DENALI_PHY_1360 Register
          1281. 14.5.1.2.1281 EMIF_CTLCFG_DENALI_PHY_1361 Register
          1282. 14.5.1.2.1282 EMIF_CTLCFG_DENALI_PHY_1362 Register
          1283. 14.5.1.2.1283 EMIF_CTLCFG_DENALI_PHY_1363 Register
          1284. 14.5.1.2.1284 EMIF_CTLCFG_DENALI_PHY_1364 Register
          1285. 14.5.1.2.1285 EMIF_CTLCFG_DENALI_PHY_1365 Register
          1286. 14.5.1.2.1286 EMIF_CTLCFG_DENALI_PHY_1366 Register
          1287. 14.5.1.2.1287 EMIF_CTLCFG_DENALI_PHY_1367 Register
          1288. 14.5.1.2.1288 EMIF_CTLCFG_DENALI_PHY_1368 Register
          1289. 14.5.1.2.1289 EMIF_CTLCFG_DENALI_PHY_1369 Register
          1290. 14.5.1.2.1290 EMIF_CTLCFG_DENALI_PHY_1370 Register
          1291. 14.5.1.2.1291 EMIF_CTLCFG_DENALI_PHY_1371 Register
          1292. 14.5.1.2.1292 EMIF_CTLCFG_DENALI_PHY_1372 Register
          1293. 14.5.1.2.1293 EMIF_CTLCFG_DENALI_PHY_1373 Register
          1294. 14.5.1.2.1294 EMIF_CTLCFG_DENALI_PHY_1374 Register
          1295. 14.5.1.2.1295 EMIF_CTLCFG_DENALI_PHY_1375 Register
          1296. 14.5.1.2.1296 EMIF_CTLCFG_DENALI_PHY_1376 Register
          1297. 14.5.1.2.1297 EMIF_CTLCFG_DENALI_PHY_1377 Register
          1298. 14.5.1.2.1298 EMIF_CTLCFG_DENALI_PHY_1378 Register
          1299. 14.5.1.2.1299 EMIF_CTLCFG_DENALI_PHY_1379 Register
          1300. 14.5.1.2.1300 EMIF_CTLCFG_DENALI_PHY_1380 Register
          1301. 14.5.1.2.1301 EMIF_CTLCFG_DENALI_PHY_1381 Register
          1302. 14.5.1.2.1302 EMIF_CTLCFG_DENALI_PHY_1382 Register
          1303. 14.5.1.2.1303 EMIF_CTLCFG_DENALI_PHY_1383 Register
          1304. 14.5.1.2.1304 EMIF_CTLCFG_DENALI_PHY_1384 Register
          1305. 14.5.1.2.1305 EMIF_CTLCFG_DENALI_PHY_1385 Register
          1306. 14.5.1.2.1306 EMIF_CTLCFG_DENALI_PHY_1386 Register
          1307. 14.5.1.2.1307 EMIF_CTLCFG_DENALI_PHY_1387 Register
          1308. 14.5.1.2.1308 EMIF_CTLCFG_DENALI_PHY_1388 Register
          1309. 14.5.1.2.1309 EMIF_CTLCFG_DENALI_PHY_1389 Register
          1310. 14.5.1.2.1310 EMIF_CTLCFG_DENALI_PHY_1390 Register
          1311. 14.5.1.2.1311 EMIF_CTLCFG_DENALI_PHY_1391 Register
          1312. 14.5.1.2.1312 EMIF_CTLCFG_DENALI_PHY_1392 Register
          1313. 14.5.1.2.1313 EMIF_CTLCFG_DENALI_PHY_1393 Register
          1314. 14.5.1.2.1314 EMIF_CTLCFG_DENALI_PHY_1394 Register
          1315. 14.5.1.2.1315 EMIF_CTLCFG_DENALI_PHY_1395 Register
          1316. 14.5.1.2.1316 EMIF_CTLCFG_DENALI_PHY_1396 Register
          1317. 14.5.1.2.1317 EMIF_CTLCFG_DENALI_PHY_1397 Register
          1318. 14.5.1.2.1318 EMIF_CTLCFG_DENALI_PHY_1398 Register
          1319. 14.5.1.2.1319 EMIF_CTLCFG_DENALI_PHY_1399 Register
          1320. 14.5.1.2.1320 EMIF_CTLCFG_DENALI_PHY_1400 Register
          1321. 14.5.1.2.1321 EMIF_CTLCFG_DENALI_PHY_1401 Register
          1322. 14.5.1.2.1322 EMIF_CTLCFG_DENALI_PHY_1402 Register
          1323. 14.5.1.2.1323 EMIF_CTLCFG_DENALI_PHY_1403 Register
          1324. 14.5.1.2.1324 EMIF_CTLCFG_DENALI_PHY_1404 Register
          1325. 14.5.1.2.1325 EMIF_CTLCFG_DENALI_PHY_1405 Register
      2. 14.5.2 RAT Registers
    6. 14.6  Interrupt Router Registers
      1. 14.6.1 MAIN_GPIOMUX_INTROUTER Registers
        1. 14.6.1.1 MAIN_GPIOMUX_INTROUTER Summary Table
        2. 14.6.1.2 INTR_ROUTER_CFG_PID Register
        3. 14.6.1.3 INTR_ROUTER_CFG_MUXCNTL_j Register
    7. 14.7  DMA Controller Registers
      1. 14.7.1 DMSS Top-Level Registers
        1. 14.7.1.1 DMASS_PKTDMA_0
          1. 14.7.1.1.1 DMASS_PKTDMA_0 Summaries
            1.         7635
            2.         7636
            3.         7637
            4.         7638
            5.         7639
            6.         7640
            7.         7641
            8.         7642
            9.         7643
          2. 14.7.1.1.2 DMASS_PKTDMA_0 Registers
            1. 14.7.1.1.2.1  LCDMA_RINGACC_CRED_RING_CRED_j Register
            2. 14.7.1.1.2.2  PKTDMA_RXFCFG_FLOW_RFA_j Register
            3. 14.7.1.1.2.3  PKTDMA_TXCCFG_CHAN_TCFG_j Register
            4. 14.7.1.1.2.4  PKTDMA_TXCCFG_CHAN_TPRI_CTRL_j Register
            5. 14.7.1.1.2.5  PKTDMA_TXCCFG_CHAN_THREAD_j Register
            6. 14.7.1.1.2.6  PKTDMA_TXCCFG_CHAN_TFIFO_DEPTH_j Register
            7. 14.7.1.1.2.7  PKTDMA_TXCCFG_CHAN_TST_SCHED_j Register
            8. 14.7.1.1.2.8  PKTDMA_RXCCFG_CHAN_RCFG_j Register
            9. 14.7.1.1.2.9  PKTDMA_RXCCFG_CHAN_RPRI_CTRL_j Register
            10. 14.7.1.1.2.10 PKTDMA_RXCCFG_CHAN_THREAD_j Register
            11. 14.7.1.1.2.11 PKTDMA_RXCCFG_CHAN_RST_SCHED_j Register
            12. 14.7.1.1.2.12 PKTDMA_GCFG_REVISION Register
            13. 14.7.1.1.2.13 PKTDMA_GCFG_PERF_CTRL Register
            14. 14.7.1.1.2.14 PKTDMA_GCFG_EMU_CTRL Register
            15. 14.7.1.1.2.15 PKTDMA_GCFG_PSIL_TO Register
            16. 14.7.1.1.2.16 PKTDMA_GCFG_CAP0 Register
            17. 14.7.1.1.2.17 PKTDMA_GCFG_CAP1 Register
            18. 14.7.1.1.2.18 PKTDMA_GCFG_CAP2 Register
            19. 14.7.1.1.2.19 PKTDMA_GCFG_CAP3 Register
            20. 14.7.1.1.2.20 PKTDMA_GCFG_CAP4 Register
            21. 14.7.1.1.2.21 PKTDMA_GCFG_PM0 Register
            22. 14.7.1.1.2.22 PKTDMA_GCFG_PM1 Register
            23. 14.7.1.1.2.23 PKTDMA_GCFG_DBGADDR Register
            24. 14.7.1.1.2.24 PKTDMA_GCFG_DBGDATA Register
            25. 14.7.1.1.2.25 PKTDMA_GCFG_RFLOWFWSTAT Register
            26. 14.7.1.1.2.26 LCDMA_RINGACC_RING_CFG_RING_BA_LO_j Register
            27. 14.7.1.1.2.27 LCDMA_RINGACC_RING_CFG_RING_BA_HI_j Register
            28. 14.7.1.1.2.28 LCDMA_RINGACC_RING_CFG_RING_SIZE_j Register
            29. 14.7.1.1.2.29 PKTDMA_RXCRT_CHAN_CTL_j Register
            30. 14.7.1.1.2.30 PKTDMA_RXCRT_CHAN_STATUS0_j Register
            31. 14.7.1.1.2.31 PKTDMA_RXCRT_CHAN_STATUS1_j Register
            32. 14.7.1.1.2.32 PKTDMA_RXCRT_CHAN_STDATA_j_k Register
            33. 14.7.1.1.2.33 PKTDMA_RXCRT_CHAN_PEER0_j Register
            34. 14.7.1.1.2.34 PKTDMA_RXCRT_CHAN_PEER1_j Register
            35. 14.7.1.1.2.35 PKTDMA_RXCRT_CHAN_PEER2_j Register
            36. 14.7.1.1.2.36 PKTDMA_RXCRT_CHAN_PEER3_j Register
            37. 14.7.1.1.2.37 PKTDMA_RXCRT_CHAN_PEER4_j Register
            38. 14.7.1.1.2.38 PKTDMA_RXCRT_CHAN_PEER5_j Register
            39. 14.7.1.1.2.39 PKTDMA_RXCRT_CHAN_PEER6_j Register
            40. 14.7.1.1.2.40 PKTDMA_RXCRT_CHAN_PEER7_j Register
            41. 14.7.1.1.2.41 PKTDMA_RXCRT_CHAN_PEER8_j Register
            42. 14.7.1.1.2.42 PKTDMA_RXCRT_CHAN_PEER9_j Register
            43. 14.7.1.1.2.43 PKTDMA_RXCRT_CHAN_PEER10_j Register
            44. 14.7.1.1.2.44 PKTDMA_RXCRT_CHAN_PEER11_j Register
            45. 14.7.1.1.2.45 PKTDMA_RXCRT_CHAN_PEER12_j Register
            46. 14.7.1.1.2.46 PKTDMA_RXCRT_CHAN_PEER13_j Register
            47. 14.7.1.1.2.47 PKTDMA_RXCRT_CHAN_PEER14_j Register
            48. 14.7.1.1.2.48 PKTDMA_RXCRT_CHAN_PEER15_j Register
            49. 14.7.1.1.2.49 PKTDMA_RXCRT_CHAN_PCNT_j Register
            50. 14.7.1.1.2.50 PKTDMA_RXCRT_CHAN_DCNT_j Register
            51. 14.7.1.1.2.51 PKTDMA_RXCRT_CHAN_BCNT_j Register
            52. 14.7.1.1.2.52 PKTDMA_RXCRT_CHAN_SBCNT_j Register
            53. 14.7.1.1.2.53 PKTDMA_TXCRT_CHAN_CTL_j Register
            54. 14.7.1.1.2.54 PKTDMA_TXCRT_CHAN_STATUS0_j Register
            55. 14.7.1.1.2.55 PKTDMA_TXCRT_CHAN_STATUS1_j Register
            56. 14.7.1.1.2.56 PKTDMA_TXCRT_CHAN_STDATA_j_k Register
            57. 14.7.1.1.2.57 PKTDMA_TXCRT_CHAN_PEER0_j Register
            58. 14.7.1.1.2.58 PKTDMA_TXCRT_CHAN_PEER1_j Register
            59. 14.7.1.1.2.59 PKTDMA_TXCRT_CHAN_PEER2_j Register
            60. 14.7.1.1.2.60 PKTDMA_TXCRT_CHAN_PEER3_j Register
            61. 14.7.1.1.2.61 PKTDMA_TXCRT_CHAN_PEER4_j Register
            62. 14.7.1.1.2.62 PKTDMA_TXCRT_CHAN_PEER5_j Register
            63. 14.7.1.1.2.63 PKTDMA_TXCRT_CHAN_PEER6_j Register
            64. 14.7.1.1.2.64 PKTDMA_TXCRT_CHAN_PEER7_j Register
            65. 14.7.1.1.2.65 PKTDMA_TXCRT_CHAN_PEER8_j Register
            66. 14.7.1.1.2.66 PKTDMA_TXCRT_CHAN_PEER9_j Register
            67. 14.7.1.1.2.67 PKTDMA_TXCRT_CHAN_PEER10_j Register
            68. 14.7.1.1.2.68 PKTDMA_TXCRT_CHAN_PEER11_j Register
            69. 14.7.1.1.2.69 PKTDMA_TXCRT_CHAN_PEER12_j Register
            70. 14.7.1.1.2.70 PKTDMA_TXCRT_CHAN_PEER13_j Register
            71. 14.7.1.1.2.71 PKTDMA_TXCRT_CHAN_PEER14_j Register
            72. 14.7.1.1.2.72 PKTDMA_TXCRT_CHAN_PEER15_j Register
            73. 14.7.1.1.2.73 PKTDMA_TXCRT_CHAN_PCNT_j Register
            74. 14.7.1.1.2.74 PKTDMA_TXCRT_CHAN_BCNT_j Register
            75. 14.7.1.1.2.75 PKTDMA_TXCRT_CHAN_SBCNT_j Register
            76. 14.7.1.1.2.76 LCDMA_RINGACC_RINGRT_RING_FDB_j Register
            77. 14.7.1.1.2.77 LCDMA_RINGACC_RINGRT_RING_FOCC_j Register
            78. 14.7.1.1.2.78 LCDMA_RINGACC_RINGRT_RING_RDB_j Register
            79. 14.7.1.1.2.79 LCDMA_RINGACC_RINGRT_RING_ROCC_j Register
        2. 14.7.1.2 DMASS_BCDMA_0
          1. 14.7.1.2.1 DMASS_BCDMA_0 Summaries
            1.         7726
            2.         7727
            3.         7728
            4.         7729
            5.         7730
            6.         7731
            7.         7732
            8.         7733
            9.         7734
            10.         7735
          2. 14.7.1.2.2 DMASS_BCDMA_0 Registers
            1. 14.7.1.2.2.1  LCDMA_RINGACC_CRED_RING_CRED_j Register
            2. 14.7.1.2.2.2  BCDMA_BCCFG_CHAN_CFG_j Register
            3. 14.7.1.2.2.3  BCDMA_BCCFG_CHAN_PRI_CTRL_j Register
            4. 14.7.1.2.2.4  BCDMA_BCCFG_CHAN_TST_SCHED_j Register
            5. 14.7.1.2.2.5  BCDMA_TXCCFG_CHAN_TCFG_j Register
            6. 14.7.1.2.2.6  BCDMA_TXCCFG_CHAN_TPRI_CTRL_j Register
            7. 14.7.1.2.2.7  BCDMA_TXCCFG_CHAN_THREAD_j Register
            8. 14.7.1.2.2.8  BCDMA_TXCCFG_CHAN_TFIFO_DEPTH_j Register
            9. 14.7.1.2.2.9  BCDMA_TXCCFG_CHAN_TST_SCHED_j Register
            10. 14.7.1.2.2.10 BCDMA_RXCCFG_CHAN_RCFG_j Register
            11. 14.7.1.2.2.11 BCDMA_RXCCFG_CHAN_RPRI_CTRL_j Register
            12. 14.7.1.2.2.12 BCDMA_RXCCFG_CHAN_THREAD_j Register
            13. 14.7.1.2.2.13 BCDMA_RXCCFG_CHAN_RST_SCHED_j Register
            14. 14.7.1.2.2.14 BCDMA_GCFG_REVISION Register
            15. 14.7.1.2.2.15 BCDMA_GCFG_PERF_CTRL Register
            16. 14.7.1.2.2.16 BCDMA_GCFG_EMU_CTRL Register
            17. 14.7.1.2.2.17 BCDMA_GCFG_PSIL_TO Register
            18. 14.7.1.2.2.18 BCDMA_GCFG_CAP0 Register
            19. 14.7.1.2.2.19 BCDMA_GCFG_CAP1 Register
            20. 14.7.1.2.2.20 BCDMA_GCFG_CAP2 Register
            21. 14.7.1.2.2.21 BCDMA_GCFG_CAP3 Register
            22. 14.7.1.2.2.22 BCDMA_GCFG_CAP4 Register
            23. 14.7.1.2.2.23 BCDMA_GCFG_PM0 Register
            24. 14.7.1.2.2.24 BCDMA_GCFG_PM1 Register
            25. 14.7.1.2.2.25 BCDMA_GCFG_DBGADDR Register
            26. 14.7.1.2.2.26 BCDMA_GCFG_DBGDATA Register
            27. 14.7.1.2.2.27 LCDMA_RINGACC_RING_CFG_RING_BA_LO_j Register
            28. 14.7.1.2.2.28 LCDMA_RINGACC_RING_CFG_RING_BA_HI_j Register
            29. 14.7.1.2.2.29 LCDMA_RINGACC_RING_CFG_RING_SIZE_j Register
            30. 14.7.1.2.2.30 BCDMA_RXCRT_CHAN_CTL_j Register
            31. 14.7.1.2.2.31 BCDMA_RXCRT_CHAN_SWTRIG_j Register
            32. 14.7.1.2.2.32 BCDMA_RXCRT_CHAN_STATUS0_j Register
            33. 14.7.1.2.2.33 BCDMA_RXCRT_CHAN_STATUS1_j Register
            34. 14.7.1.2.2.34 BCDMA_RXCRT_CHAN_STDATA_j_k Register
            35. 14.7.1.2.2.35 BCDMA_RXCRT_CHAN_PEER0_j Register
            36. 14.7.1.2.2.36 BCDMA_RXCRT_CHAN_PEER1_j Register
            37. 14.7.1.2.2.37 BCDMA_RXCRT_CHAN_PEER2_j Register
            38. 14.7.1.2.2.38 BCDMA_RXCRT_CHAN_PEER3_j Register
            39. 14.7.1.2.2.39 BCDMA_RXCRT_CHAN_PEER4_j Register
            40. 14.7.1.2.2.40 BCDMA_RXCRT_CHAN_PEER5_j Register
            41. 14.7.1.2.2.41 BCDMA_RXCRT_CHAN_PEER6_j Register
            42. 14.7.1.2.2.42 BCDMA_RXCRT_CHAN_PEER7_j Register
            43. 14.7.1.2.2.43 BCDMA_RXCRT_CHAN_PEER8_j Register
            44. 14.7.1.2.2.44 BCDMA_RXCRT_CHAN_PEER9_j Register
            45. 14.7.1.2.2.45 BCDMA_RXCRT_CHAN_PEER10_j Register
            46. 14.7.1.2.2.46 BCDMA_RXCRT_CHAN_PEER11_j Register
            47. 14.7.1.2.2.47 BCDMA_RXCRT_CHAN_PEER12_j Register
            48. 14.7.1.2.2.48 BCDMA_RXCRT_CHAN_PEER13_j Register
            49. 14.7.1.2.2.49 BCDMA_RXCRT_CHAN_PEER14_j Register
            50. 14.7.1.2.2.50 BCDMA_RXCRT_CHAN_PEER15_j Register
            51. 14.7.1.2.2.51 BCDMA_RXCRT_CHAN_PCNT_j Register
            52. 14.7.1.2.2.52 BCDMA_RXCRT_CHAN_BCNT_j Register
            53. 14.7.1.2.2.53 BCDMA_RXCRT_CHAN_SBCNT_j Register
            54. 14.7.1.2.2.54 BCDMA_TXCRT_CHAN_CTL_j Register
            55. 14.7.1.2.2.55 BCDMA_TXCRT_CHAN_SWTRIG_j Register
            56. 14.7.1.2.2.56 BCDMA_TXCRT_CHAN_STATUS0_j Register
            57. 14.7.1.2.2.57 BCDMA_TXCRT_CHAN_STATUS1_j Register
            58. 14.7.1.2.2.58 BCDMA_TXCRT_CHAN_STDATA_j_k Register
            59. 14.7.1.2.2.59 BCDMA_TXCRT_CHAN_PEER0_j Register
            60. 14.7.1.2.2.60 BCDMA_TXCRT_CHAN_PEER1_j Register
            61. 14.7.1.2.2.61 BCDMA_TXCRT_CHAN_PEER2_j Register
            62. 14.7.1.2.2.62 BCDMA_TXCRT_CHAN_PEER3_j Register
            63. 14.7.1.2.2.63 BCDMA_TXCRT_CHAN_PEER4_j Register
            64. 14.7.1.2.2.64 BCDMA_TXCRT_CHAN_PEER5_j Register
            65. 14.7.1.2.2.65 BCDMA_TXCRT_CHAN_PEER6_j Register
            66. 14.7.1.2.2.66 BCDMA_TXCRT_CHAN_PEER7_j Register
            67. 14.7.1.2.2.67 BCDMA_TXCRT_CHAN_PEER8_j Register
            68. 14.7.1.2.2.68 BCDMA_TXCRT_CHAN_PEER9_j Register
            69. 14.7.1.2.2.69 BCDMA_TXCRT_CHAN_PEER10_j Register
            70. 14.7.1.2.2.70 BCDMA_TXCRT_CHAN_PEER11_j Register
            71. 14.7.1.2.2.71 BCDMA_TXCRT_CHAN_PEER12_j Register
            72. 14.7.1.2.2.72 BCDMA_TXCRT_CHAN_PEER13_j Register
            73. 14.7.1.2.2.73 BCDMA_TXCRT_CHAN_PEER14_j Register
            74. 14.7.1.2.2.74 BCDMA_TXCRT_CHAN_PEER15_j Register
            75. 14.7.1.2.2.75 BCDMA_TXCRT_CHAN_PCNT_j Register
            76. 14.7.1.2.2.76 BCDMA_TXCRT_CHAN_BCNT_j Register
            77. 14.7.1.2.2.77 BCDMA_TXCRT_CHAN_SBCNT_j Register
            78. 14.7.1.2.2.78 LCDMA_RINGACC_RINGRT_RING_FDB_j Register
            79. 14.7.1.2.2.79 LCDMA_RINGACC_RINGRT_RING_FOCC_j Register
            80. 14.7.1.2.2.80 LCDMA_RINGACC_RINGRT_RING_RDB_j Register
            81. 14.7.1.2.2.81 LCDMA_RINGACC_RINGRT_RING_ROCC_j Register
            82. 14.7.1.2.2.82 BCDMA_BCRT_CHAN_CTL_j Register
            83. 14.7.1.2.2.83 BCDMA_BCRT_CHAN_SWTRIG_j Register
            84. 14.7.1.2.2.84 BCDMA_BCRT_CHAN_STATUS0_j Register
            85. 14.7.1.2.2.85 BCDMA_BCRT_CHAN_STATUS1_j Register
            86. 14.7.1.2.2.86 BCDMA_BCRT_CHAN_STATUS2_j Register
            87. 14.7.1.2.2.87 BCDMA_BCRT_CHAN_STATUS3_j Register
            88. 14.7.1.2.2.88 BCDMA_BCRT_CHAN_STDATA_j_k Register
            89. 14.7.1.2.2.89 BCDMA_BCRT_CHAN_STDATAW_j_k Register
            90. 14.7.1.2.2.90 BCDMA_BCRT_CHAN_PCNT_j Register
            91. 14.7.1.2.2.91 BCDMA_BCRT_CHAN_BCNT_j Register
            92. 14.7.1.2.2.92 BCDMA_BCRT_CHAN_SBCNT_j Register
      2. 14.7.2 RINGACC Registers
        1. 14.7.2.1 DMASS_RINGACC_0
          1. 14.7.2.1.1 DMASS_RINGACC_0 Summaries
            1.         7832
            2.         7833
            3.         7834
            4.         7835
            5.         7836
          2. 14.7.2.1.2 DMASS_RINGACC_0 Registers
            1. 14.7.2.1.2.1  RINGACC_ISC_EP_CONTROL_j Register
            2. 14.7.2.1.2.2  RINGACC_ISC_EP_CONTROL2_j Register
            3. 14.7.2.1.2.3  RINGACC_GCFG_REVISION Register
            4. 14.7.2.1.2.4  RINGACC_GCFG_TRACE_CTL Register
            5. 14.7.2.1.2.5  RINGACC_GCFG_OVRFLOW Register
            6. 14.7.2.1.2.6  RINGACC_GCFG_ERROR_EVT Register
            7. 14.7.2.1.2.7  RINGACC_GCFG_ERROR_LOG Register
            8. 14.7.2.1.2.8  RINGACC_RT_RINGRT_DB_j Register
            9. 14.7.2.1.2.9  RINGACC_RT_RINGRT_OCC_j Register
            10. 14.7.2.1.2.10 RINGACC_RT_RINGRT_INDX_j Register
            11. 14.7.2.1.2.11 RINGACC_RT_RINGRT_HWOCC_j Register
            12. 14.7.2.1.2.12 RINGACC_RT_RINGRT_HWINDX_j Register
            13. 14.7.2.1.2.13 RINGACC_CFG_RING_BA_LO_j Register
            14. 14.7.2.1.2.14 RINGACC_CFG_RING_BA_HI_j Register
            15. 14.7.2.1.2.15 RINGACC_CFG_RING_SIZE_j Register
            16. 14.7.2.1.2.16 RINGACC_CFG_RING_EVENT_j Register
            17. 14.7.2.1.2.17 RINGACC_CFG_RING_ORDERID_j Register
            18. 14.7.2.1.2.18 RINGACC_FIFOS_FIFO_RINGHEADDATA_j_k Register
            19. 14.7.2.1.2.19 RINGACC_FIFOS_FIFO_RINGTAILDATA_j_k Register
            20. 14.7.2.1.2.20 RINGACC_FIFOS_FIFO_PEEKHEADDATA_j_k Register
            21. 14.7.2.1.2.21 RINGACC_FIFOS_FIFO_PEEKTAILDATA_j_k Register
      3. 14.7.3 Secure Proxy Registers
        1. 14.7.3.1 DMASS_SEC_PROXY_0
          1. 14.7.3.1.1 DMASS_SEC_PROXY_0 Summaries
            1.         7862
            2.         7863
            3.         7864
            4.         7865
          2. 14.7.3.1.2 DMASS_SEC_PROXY_0 Registers
            1. 14.7.3.1.2.1  SEC_PROXY_PID Register
            2. 14.7.3.1.2.2  SEC_PROXY_CONFIG Register
            3. 14.7.3.1.2.3  SEC_PROXY_GLB_EVT Register
            4. 14.7.3.1.2.4  SEC_PROXY_SCFG_BUFFER_L Register
            5. 14.7.3.1.2.5  SEC_PROXY_SCFG_BUFFER_H Register
            6. 14.7.3.1.2.6  SEC_PROXY_SCFG_TARGET_L Register
            7. 14.7.3.1.2.7  SEC_PROXY_SCFG_TARGET_H Register
            8. 14.7.3.1.2.8  SEC_PROXY_SCFG_ORDERID Register
            9. 14.7.3.1.2.9  SEC_PROXY_SCFG_THREAD_CTL_j Register
            10. 14.7.3.1.2.10 SEC_PROXY_SCFG_THREAD_EVT_MAP_j Register
            11. 14.7.3.1.2.11 SEC_PROXY_SCFG_THREAD_DST_j Register
            12. 14.7.3.1.2.12 SEC_PROXY_RT_THREAD_STATUS_j Register
            13. 14.7.3.1.2.13 SEC_PROXY_RT_THREAD_THR_j Register
            14. 14.7.3.1.2.14 PROXY_TARGET_THREAD_DATA_j Register
            15. 14.7.3.1.2.15 PROXY_TARGET_THREAD_MESSAGE_j_k Register
      4. 14.7.4 INTAGGR Registers
        1. 14.7.4.1 DMASS_INTAGGR_0 Registers
          1. 14.7.4.1.1  DMASS_INTAGGR_0 Summary Table
          2. 14.7.4.1.2  INTAGGR_INTR_VINT_ENABLE_SET_j Register
          3. 14.7.4.1.3  INTAGGR_INTR_VINT_ENABLE_CLEAR_j Register
          4. 14.7.4.1.4  INTAGGR_INTR_VINT_STATUS_SET_j Register
          5. 14.7.4.1.5  INTAGGR_INTR_VINT_STATUS_CLEAR_j Register
          6. 14.7.4.1.6  INTAGGR_INTR_VINT_STATUSM_j Register
          7. 14.7.4.1.7  INTAGGR_IMAP_GEVI_IMAP_j Register
          8. 14.7.4.1.8  INTAGGR_CFG_REVISION Register
          9. 14.7.4.1.9  INTAGGR_CFG_INTCAP Register
          10. 14.7.4.1.10 INTAGGR_CFG_AUXCAP Register
          11. 14.7.4.1.11 INTAGGR_L2G_LEVI_MAP_j Register
          12. 14.7.4.1.12 INTAGGR_UNMAP_UNMAP0_MAP_j Register
          13. 14.7.4.1.13 INTAGGR_UNMAP_UNMAP1_MAP_j Register
          14. 14.7.4.1.14 INTAGGR_UNMAP_UNMAP2_MAP_j Register
          15. 14.7.4.1.15 INTAGGR_UNMAP_UNMAP3_MAP_j Register
          16. 14.7.4.1.16 INTAGGR_UNMAP_UNMAP4_MAP_j Register
          17. 14.7.4.1.17 INTAGGR_UNMAP_UNMAP5_MAP_j Register
          18. 14.7.4.1.18 INTAGGR_UNMAP_UNMAP6_MAP_j Register
          19. 14.7.4.1.19 INTAGGR_UNMAP_UNMAP7_MAP_j Register
          20. 14.7.4.1.20 INTAGGR_UNMAP_UNMAP8_MAP_j Register
          21. 14.7.4.1.21 INTAGGR_UNMAP_UNMAP9_MAP_j Register
          22. 14.7.4.1.22 INTAGGR_UNMAP_UNMAP10_MAP_j Register
          23. 14.7.4.1.23 INTAGGR_UNMAP_UNMAP11_MAP_j Register
          24. 14.7.4.1.24 INTAGGR_UNMAP_UNMAP12_MAP_j Register
          25. 14.7.4.1.25 INTAGGR_UNMAP_UNMAP13_MAP_j Register
          26. 14.7.4.1.26 INTAGGR_UNMAP_UNMAP14_MAP_j Register
          27. 14.7.4.1.27 INTAGGR_UNMAP_UNMAP15_MAP_j Register
          28. 14.7.4.1.28 INTAGGR_MCAST_GEVI_MCMAP_j Register
          29. 14.7.4.1.29 INTAGGR_GCNTCFG_GEVI_MAP_j Register
          30. 14.7.4.1.30 INTAGGR_GCNTRTI_GEVI_COUNT_j Register
      5. 14.7.5 PSI-L Configuration Registers
        1. 14.7.5.1 DMASS_PSILCFG_0
          1. 14.7.5.1.1 DMASS_PSILCFG_0 Summaries
            1.         7917
          2. 14.7.5.1.2 DMASS_PSILCFG_0 Registers
            1. 14.7.5.1.2.1 PSILCFG_REVISION Register
            2. 14.7.5.1.2.2 PSILCFG_PSIL_TO Register
            3. 14.7.5.1.2.3 PSILCFG_CMDA Register
            4. 14.7.5.1.2.4 PSILCFG_CMDB Register
            5. 14.7.5.1.2.5 PSILCFG_WDATA Register
            6. 14.7.5.1.2.6 PSILCFG_RDATA Register
        2. 14.7.5.2 DMASS_PSILSS_0 Registers
      6. 14.7.6 PDMA Registers
        1. 14.7.6.1 PDMA
          1. 14.7.6.1.1 PDMA Summaries
            1.         7929
          2. 14.7.6.1.2 PDMA Registers
            1. 14.7.6.1.2.1  ECC_AGGR_REV Register
            2. 14.7.6.1.2.2  ECC_AGGR_VECTOR Register
            3. 14.7.6.1.2.3  ECC_AGGR_STAT Register
            4. 14.7.6.1.2.4  ECC_AGGR_RESERVED_SVBUS_j Register
            5. 14.7.6.1.2.5  ECC_AGGR_SEC_EOI_REG Register
            6. 14.7.6.1.2.6  ECC_AGGR_SEC_STATUS_REG0 Register
            7. 14.7.6.1.2.7  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            8. 14.7.6.1.2.8  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            9. 14.7.6.1.2.9  ECC_AGGR_DED_EOI_REG Register
            10. 14.7.6.1.2.10 ECC_AGGR_DED_STATUS_REG0 Register
            11. 14.7.6.1.2.11 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            12. 14.7.6.1.2.12 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            13. 14.7.6.1.2.13 ECC_AGGR_AGGR_ENABLE_SET Register
            14. 14.7.6.1.2.14 ECC_AGGR_AGGR_ENABLE_CLR Register
            15. 14.7.6.1.2.15 ECC_AGGR_AGGR_STATUS_SET Register
            16. 14.7.6.1.2.16 ECC_AGGR_AGGR_STATUS_CLR Register
        2. 14.7.6.2 PDMA PSI-L TX Configuration Registers
        3. 14.7.6.3 PDMA PSI-L RX Configuration Registers
    8. 14.8  Time Sync Registers
      1. 14.8.1 CPTS Registers
      2. 14.8.2 Timer Manager Registers
        1. 14.8.2.1 TIMERMGR
          1. 14.8.2.1.1 TIMERMGR Summaries
            1.         7954
            2.         7955
          2. 14.8.2.1.2 TIMERMGR Registers
            1. 14.8.2.1.2.1 TIMER_MGR_TIMERS_PAGE_ENTRY_SETUP_j_k Register
            2. 14.8.2.1.2.2 TIMER_MGR_TIMERS_PAGE_ENTRY_CONTROL_j_k Register
            3. 14.8.2.1.2.3 TIMER_MGR_PID Register
            4. 14.8.2.1.2.4 TIMER_MGR_CNTL Register
            5. 14.8.2.1.2.5 TIMER_MGR_COUNTER Register
            6. 14.8.2.1.2.6 TIMER_MGR_TIMEOUT_STATUS0 Register
            7. 14.8.2.1.2.7 TIMER_MGR_TIMEOUT_STATUS1 Register
            8. 14.8.2.1.2.8 TIMER_MGR_TIMEOUT_STATUS_BANK0 Register
            9. 14.8.2.1.2.9 TIMER_MGR_STATUS_j Register
      3. 14.8.3 Time Sync Routers Registers
        1. 14.8.3.1 TIMESYNC_EVENT_INTROUTER Registers
          1. 14.8.3.1.1 TIMESYNC_EVENT_INTROUTER Summary Table
          2. 14.8.3.1.2 INTR_ROUTER_CFG_PID Register
          3. 14.8.3.1.3 INTR_ROUTER_CFG_MUXCNTL_j Register
        2. 14.8.3.2 CMP_EVENT_INTROUTER Registers
          1. 14.8.3.2.1 CMP_EVENT_INTROUTER Summary Table
          2. 14.8.3.2.2 INTR_ROUTER_CFG_PID Register
          3. 14.8.3.2.3 INTR_ROUTER_CFG_MUXCNTL_j Register
    9. 14.9  Peripherals Registers
      1. 14.9.1 General Connectivity Registers
        1. 14.9.1.1 ADC Registers
        2. 14.9.1.2 GPIO
          1. 14.9.1.2.1 GPIO Summaries
            1.         7980
          2. 14.9.1.2.2 GPIO Registers
            1. 14.9.1.2.2.1  GPIO_PID Register
            2. 14.9.1.2.2.2  GPIO_PCR Register
            3. 14.9.1.2.2.3  GPIO_BINTEN Register
            4. 14.9.1.2.2.4  GPIO_DIR01 Register
            5. 14.9.1.2.2.5  GPIO_OUT_DATA01 Register
            6. 14.9.1.2.2.6  GPIO_SET_DATA01 Register
            7. 14.9.1.2.2.7  GPIO_CLR_DATA01 Register
            8. 14.9.1.2.2.8  GPIO_IN_DATA01 Register
            9. 14.9.1.2.2.9  GPIO_SET_RIS_TRIG01 Register
            10. 14.9.1.2.2.10 GPIO_CLR_RIS_TRIG01 Register
            11. 14.9.1.2.2.11 GPIO_SET_FAL_TRIG01 Register
            12. 14.9.1.2.2.12 GPIO_CLR_FAL_TRIG01 Register
            13. 14.9.1.2.2.13 GPIO_INTSTAT01 Register
            14. 14.9.1.2.2.14 GPIO_DIR23 Register
            15. 14.9.1.2.2.15 GPIO_OUT_DATA23 Register
            16. 14.9.1.2.2.16 GPIO_SET_DATA23 Register
            17. 14.9.1.2.2.17 GPIO_CLR_DATA23 Register
            18. 14.9.1.2.2.18 GPIO_IN_DATA23 Register
            19. 14.9.1.2.2.19 GPIO_SET_RIS_TRIG23 Register
            20. 14.9.1.2.2.20 GPIO_CLR_RIS_TRIG23 Register
            21. 14.9.1.2.2.21 GPIO_SET_FAL_TRIG23 Register
            22. 14.9.1.2.2.22 GPIO_CLR_FAL_TRIG23 Register
            23. 14.9.1.2.2.23 GPIO_INTSTAT23 Register
            24. 14.9.1.2.2.24 GPIO_DIR45 Register
            25. 14.9.1.2.2.25 GPIO_OUT_DATA45 Register
            26. 14.9.1.2.2.26 GPIO_SET_DATA45 Register
            27. 14.9.1.2.2.27 GPIO_CLR_DATA45 Register
            28. 14.9.1.2.2.28 GPIO_IN_DATA45 Register
            29. 14.9.1.2.2.29 GPIO_SET_RIS_TRIG45 Register
            30. 14.9.1.2.2.30 GPIO_CLR_RIS_TRIG45 Register
            31. 14.9.1.2.2.31 GPIO_SET_FAL_TRIG45 Register
            32. 14.9.1.2.2.32 GPIO_CLR_FAL_TRIG45 Register
            33. 14.9.1.2.2.33 GPIO_INTSTAT45 Register
            34. 14.9.1.2.2.34 GPIO_DIR67 Register
            35. 14.9.1.2.2.35 GPIO_OUT_DATA67 Register
            36. 14.9.1.2.2.36 GPIO_SET_DATA67 Register
            37. 14.9.1.2.2.37 GPIO_CLR_DATA67 Register
            38. 14.9.1.2.2.38 GPIO_IN_DATA67 Register
            39. 14.9.1.2.2.39 GPIO_SET_RIS_TRIG67 Register
            40. 14.9.1.2.2.40 GPIO_CLR_RIS_TRIG67 Register
            41. 14.9.1.2.2.41 GPIO_SET_FAL_TRIG67 Register
            42. 14.9.1.2.2.42 GPIO_CLR_FAL_TRIG67 Register
            43. 14.9.1.2.2.43 GPIO_INTSTAT67 Register
            44. 14.9.1.2.2.44 GPIO_DIR8 Register
            45. 14.9.1.2.2.45 GPIO_OUT_DATA8 Register
            46. 14.9.1.2.2.46 GPIO_SET_DATA8 Register
            47. 14.9.1.2.2.47 GPIO_CLR_DATA8 Register
            48. 14.9.1.2.2.48 GPIO_IN_DATA8 Register
            49. 14.9.1.2.2.49 GPIO_SET_RIS_TRIG8 Register
            50. 14.9.1.2.2.50 GPIO_CLR_RIS_TRIG8 Register
            51. 14.9.1.2.2.51 GPIO_SET_FAL_TRIG8 Register
            52. 14.9.1.2.2.52 GPIO_CLR_FAL_TRIG8 Register
            53. 14.9.1.2.2.53 GPIO_INTSTAT8 Register
        3. 14.9.1.3 I2C Registers
        4. 14.9.1.4 MCSPI
          1. 14.9.1.4.1 MCSPI Summaries
            1.         8038
          2. 14.9.1.4.2 MCSPI Registers
            1. 14.9.1.4.2.1  MCSPI_HL_REV Register
            2. 14.9.1.4.2.2  MCSPI_HL_HWINFO Register
            3. 14.9.1.4.2.3  MCSPI_HL_SYSCONFIG Register
            4. 14.9.1.4.2.4  MCSPI_REVISION Register
            5. 14.9.1.4.2.5  MCSPI_SYSCONFIG Register
            6. 14.9.1.4.2.6  MCSPI_SYSSTATUS Register
            7. 14.9.1.4.2.7  MCSPI_IRQSTATUS Register
            8. 14.9.1.4.2.8  MCSPI_IRQENABLE Register
            9. 14.9.1.4.2.9  MCSPI_WAKEUPENABLE Register
            10. 14.9.1.4.2.10 MCSPI_SYST Register
            11. 14.9.1.4.2.11 MCSPI_MODULCTRL Register
            12. 14.9.1.4.2.12 MCSPI_CH0CONF Register
            13. 14.9.1.4.2.13 MCSPI_CH0STAT Register
            14. 14.9.1.4.2.14 MCSPI_CH0CTRL Register
            15. 14.9.1.4.2.15 MCSPI_TX0 Register
            16. 14.9.1.4.2.16 MCSPI_RX0 Register
            17. 14.9.1.4.2.17 MCSPI_CH1CONF Register
            18. 14.9.1.4.2.18 MCSPI_CH1STAT Register
            19. 14.9.1.4.2.19 MCSPI_CH1CTRL Register
            20. 14.9.1.4.2.20 MCSPI_TX1 Register
            21. 14.9.1.4.2.21 MCSPI_RX1 Register
            22. 14.9.1.4.2.22 MCSPI_CH2CONF Register
            23. 14.9.1.4.2.23 MCSPI_CH2STAT Register
            24. 14.9.1.4.2.24 MCSPI_CH2CTRL Register
            25. 14.9.1.4.2.25 MCSPI_TX2 Register
            26. 14.9.1.4.2.26 MCSPI_RX2 Register
            27. 14.9.1.4.2.27 MCSPI_CH3CONF Register
            28. 14.9.1.4.2.28 MCSPI_CH3STAT Register
            29. 14.9.1.4.2.29 MCSPI_CH3CTRL Register
            30. 14.9.1.4.2.30 MCSPI_TX3 Register
            31. 14.9.1.4.2.31 MCSPI_RX3 Register
            32. 14.9.1.4.2.32 MCSPI_XFERLEVEL Register
            33. 14.9.1.4.2.33 MCSPI_DAFTX Register
            34. 14.9.1.4.2.34 MCSPI_DAFRX Register
        5. 14.9.1.5 UART
          1. 14.9.1.5.1 UART Summaries
            1.         8076
          2. 14.9.1.5.2 UART Registers
            1. 14.9.1.5.2.1  UART_DLL Register
            2. 14.9.1.5.2.2  UART_RHR Register
            3. 14.9.1.5.2.3  UART_THR Register
            4. 14.9.1.5.2.4  UART_DLH Register
            5. 14.9.1.5.2.5  UART_IER_CIR Register
            6. 14.9.1.5.2.6  UART_IER_IRDA Register
            7. 14.9.1.5.2.7  UART_IER_UART Register
            8. 14.9.1.5.2.8  UART_EFR Register
            9. 14.9.1.5.2.9  UART_FCR Register
            10. 14.9.1.5.2.10 UART_IIR_CIR Register
            11. 14.9.1.5.2.11 UART_IIR_IRDA Register
            12. 14.9.1.5.2.12 UART_IIR_UART Register
            13. 14.9.1.5.2.13 UART_LCR Register
            14. 14.9.1.5.2.14 UART_MCR Register
            15. 14.9.1.5.2.15 UART_XON1_ADDR1 Register
            16. 14.9.1.5.2.16 UART_LSR_CIR Register
            17. 14.9.1.5.2.17 UART_LSR_IRDA Register
            18. 14.9.1.5.2.18 UART_LSR_UART Register
            19. 14.9.1.5.2.19 UART_XON2_ADDR2 Register
            20. 14.9.1.5.2.20 UART_MSR Register
            21. 14.9.1.5.2.21 UART_TCR Register
            22. 14.9.1.5.2.22 UART_XOFF1 Register
            23. 14.9.1.5.2.23 UART_SPR Register
            24. 14.9.1.5.2.24 UART_TLR Register
            25. 14.9.1.5.2.25 UART_XOFF2 Register
            26. 14.9.1.5.2.26 UART_MDR1 Register
            27. 14.9.1.5.2.27 UART_MDR2 Register
            28. 14.9.1.5.2.28 UART_SFLSR Register
            29. 14.9.1.5.2.29 UART_TXFLL Register
            30. 14.9.1.5.2.30 UART_RESUME Register
            31. 14.9.1.5.2.31 UART_TXFLH Register
            32. 14.9.1.5.2.32 UART_RXFLL Register
            33. 14.9.1.5.2.33 UART_SFREGL Register
            34. 14.9.1.5.2.34 UART_RXFLH Register
            35. 14.9.1.5.2.35 UART_SFREGH Register
            36. 14.9.1.5.2.36 UART_BLR Register
            37. 14.9.1.5.2.37 UART_UASR Register
            38. 14.9.1.5.2.38 UART_ACREG Register
            39. 14.9.1.5.2.39 UART_SCR Register
            40. 14.9.1.5.2.40 UART_SSR Register
            41. 14.9.1.5.2.41 UART_EBLR Register
            42. 14.9.1.5.2.42 UART_MVR Register
            43. 14.9.1.5.2.43 UART_SYSC Register
            44. 14.9.1.5.2.44 UART_SYSS Register
            45. 14.9.1.5.2.45 UART_WER Register
            46. 14.9.1.5.2.46 UART_CFPS Register
            47. 14.9.1.5.2.47 UART_RXFIFO_LVL Register
            48. 14.9.1.5.2.48 UART_TXFIFO_LVL Register
            49. 14.9.1.5.2.49 UART_IER2 Register
            50. 14.9.1.5.2.50 UART_ISR2 Register
            51. 14.9.1.5.2.51 UART_FREQ_SEL Register
            52. 14.9.1.5.2.52 UART_ABAUD_1ST_CHAR Register
            53. 14.9.1.5.2.53 UART_BAUD_2ND_CHAR Register
            54. 14.9.1.5.2.54 UART_MDR3 Register
            55. 14.9.1.5.2.55 UART_TX_DMA_THRESHOLD Register
            56. 14.9.1.5.2.56 UART_MDR4 Register
            57. 14.9.1.5.2.57 UART_EFR2 Register
            58. 14.9.1.5.2.58 UART_ECR Register
            59. 14.9.1.5.2.59 UART_TIMEGUARD Register
            60. 14.9.1.5.2.60 UART_TIMEOUTL Register
            61. 14.9.1.5.2.61 UART_TIMEOUTH Register
            62. 14.9.1.5.2.62 UART_SCCR Register
            63. 14.9.1.5.2.63 UART_ERHR Register
            64. 14.9.1.5.2.64 UART_ETHR Register
            65. 14.9.1.5.2.65 UART_MAR Register
            66. 14.9.1.5.2.66 UART_MMR Register
            67. 14.9.1.5.2.67 UART_MBR Register
      2. 14.9.2 High-speed Serial Interfaces Registers
        1. 14.9.2.1 CPSW Registers
          1. 14.9.2.1.1   CPSW Summary Table
          2. 14.9.2.1.2   CPSW3_ECC_ECC_REV Register
          3. 14.9.2.1.3   CPSW3_ECC_ECC_VECTOR Register
          4. 14.9.2.1.4   CPSW3_ECC_ECC_STAT Register
          5. 14.9.2.1.5   CPSW3_ECC_ECC_RESERVED_SVBUS_j Register
          6. 14.9.2.1.6   CPSW3_ECC_ECC_SEC_EOI_REG Register
          7. 14.9.2.1.7   CPSW3_ECC_ECC_SEC_STATUS_REG0 Register
          8. 14.9.2.1.8   CPSW3_ECC_ECC_SEC_ENABLE_SET_REG0 Register
          9. 14.9.2.1.9   CPSW3_ECC_ECC_SEC_ENABLE_CLR_REG0 Register
          10. 14.9.2.1.10  CPSW3_ECC_ECC_DED_EOI_REG Register
          11. 14.9.2.1.11  CPSW3_ECC_ECC_DED_STATUS_REG0 Register
          12. 14.9.2.1.12  CPSW3_ECC_ECC_DED_ENABLE_SET_REG0 Register
          13. 14.9.2.1.13  CPSW3_ECC_ECC_DED_ENABLE_CLR_REG0 Register
          14. 14.9.2.1.14  CPSW3_ECC_ECC_AGGR_ENABLE_SET Register
          15. 14.9.2.1.15  CPSW3_ECC_ECC_AGGR_ENABLE_CLR Register
          16. 14.9.2.1.16  CPSW3_ECC_ECC_AGGR_STATUS_SET Register
          17. 14.9.2.1.17  CPSW3_ECC_ECC_AGGR_STATUS_CLR Register
          18. 14.9.2.1.18  CPSW3_CPSW_NUSS_IDVER_REG Register
          19. 14.9.2.1.19  CPSW3_SYNCE_COUNT_REG Register
          20. 14.9.2.1.20  CPSW3_SYNCE_MUX_REG Register
          21. 14.9.2.1.21  CPSW3_CONTROL_REG Register
          22. 14.9.2.1.22  CPSW3_SGMII_NON_FIBER_MODE_REG Register
          23. 14.9.2.1.23  CPSW3_SERDES_RESET_ISO_REG Register
          24. 14.9.2.1.24  CPSW3_SUBSSYSTEM_STATUS_REG Register
          25. 14.9.2.1.25  CPSW3_SUBSYSTEM_CONFIG_REG Register
          26. 14.9.2.1.26  CPSW3_RGMII1_STATUS_REG Register
          27. 14.9.2.1.27  CPSW3_RGMII2_STATUS_REG Register
          28. 14.9.2.1.28  CPSW3_CPSGMII_SGMII_IDVER_REG_j Register
          29. 14.9.2.1.29  CPSW3_CPSGMII_SOFT_RESET_REG_j Register
          30. 14.9.2.1.30  CPSW3_CPSGMII_CONTROL_REG_j Register
          31. 14.9.2.1.31  CPSW3_CPSGMII_STATUS_REG_j Register
          32. 14.9.2.1.32  CPSW3_CPSGMII_MR_ADV_ABILITY_REG_j Register
          33. 14.9.2.1.33  CPSW3_CPSGMII_MR_NP_TX_REG_j Register
          34. 14.9.2.1.34  CPSW3_CPSGMII_MR_LP_ADV_ABILITY_REG_j Register
          35. 14.9.2.1.35  CPSW3_CPSGMII_MR_LP_NP_RX_REG_j Register
          36. 14.9.2.1.36  CPSW3_CPSGMII_DIAG_CLEAR_REG_j Register
          37. 14.9.2.1.37  CPSW3_CPSGMII_DIAG_CONTROL_REG_j Register
          38. 14.9.2.1.38  CPSW3_CPSGMII_DIAG_STATUS_REG_j Register
          39. 14.9.2.1.39  CPSW3_MDIO_MDIO_VERSION_REG Register
          40. 14.9.2.1.40  CPSW3_MDIO_CONTROL_REG Register
          41. 14.9.2.1.41  CPSW3_MDIO_ALIVE_REG Register
          42. 14.9.2.1.42  CPSW3_MDIO_LINK_REG Register
          43. 14.9.2.1.43  CPSW3_MDIO_LINK_INT_RAW_REG Register
          44. 14.9.2.1.44  CPSW3_MDIO_LINK_INT_MASKED_REG Register
          45. 14.9.2.1.45  CPSW3_MDIO_LINK_INT_MASK_SET_REG Register
          46. 14.9.2.1.46  CPSW3_MDIO_LINK_INT_MASK_CLEAR_REG Register
          47. 14.9.2.1.47  CPSW3_MDIO_USER_INT_RAW_REG Register
          48. 14.9.2.1.48  CPSW3_MDIO_USER_INT_MASKED_REG Register
          49. 14.9.2.1.49  CPSW3_MDIO_USER_INT_MASK_SET_REG Register
          50. 14.9.2.1.50  CPSW3_MDIO_USER_INT_MASK_CLEAR_REG Register
          51. 14.9.2.1.51  CPSW3_MDIO_MANUAL_IF_REG Register
          52. 14.9.2.1.52  CPSW3_MDIO_POLL_REG Register
          53. 14.9.2.1.53  CPSW3_MDIO_POLL_EN_REG Register
          54. 14.9.2.1.54  CPSW3_MDIO_CLAUS45_REG Register
          55. 14.9.2.1.55  CPSW3_MDIO_USER_ADDR0_REG Register
          56. 14.9.2.1.56  CPSW3_MDIO_USER_ADDR1_REG Register
          57. 14.9.2.1.57  CPSW3_MDIO_USER_GROUP_USER_ACCESS_REG_j Register
          58. 14.9.2.1.58  CPSW3_MDIO_USER_GROUP_USER_PHY_SEL_REG_j Register
          59. 14.9.2.1.59  CPSW3_INTD_REVISION Register
          60. 14.9.2.1.60  CPSW3_INTD_EOI_REG Register
          61. 14.9.2.1.61  CPSW3_INTD_INTR_VECTOR_REG Register
          62. 14.9.2.1.62  CPSW3_INTD_ENABLE_REG_OUT_PULSE_0 Register
          63. 14.9.2.1.63  CPSW3_INTD_ENABLE_CLR_REG_OUT_PULSE_0 Register
          64. 14.9.2.1.64  CPSW3_INTD_STATUS_REG_OUT_PULSE_0 Register
          65. 14.9.2.1.65  CPSW3_INTD_INTR_VECTOR_REG_OUT_PULSE Register
          66. 14.9.2.1.66  CPSW3_CPSW_NU_CPSW_ID_VER_REG Register
          67. 14.9.2.1.67  CPSW3_CPSW_NU_CONTROL_REG Register
          68. 14.9.2.1.68  CPSW3_CPSW_NU_EM_CONTROL_REG Register
          69. 14.9.2.1.69  CPSW3_CPSW_NU_STAT_PORT_EN_REG Register
          70. 14.9.2.1.70  CPSW3_CPSW_NU_PTYPE_REG Register
          71. 14.9.2.1.71  CPSW3_CPSW_NU_SOFT_IDLE_REG Register
          72. 14.9.2.1.72  CPSW3_CPSW_NU_THRU_RATE_REG Register
          73. 14.9.2.1.73  CPSW3_CPSW_NU_GAP_THRESH_REG Register
          74. 14.9.2.1.74  CPSW3_CPSW_NU_EEE_PRESCALE_REG Register
          75. 14.9.2.1.75  CPSW3_CPSW_NU_TX_G_OFLOW_THRESH_SET_REG Register
          76. 14.9.2.1.76  CPSW3_CPSW_NU_TX_G_OFLOW_THRESH_CLR_REG Register
          77. 14.9.2.1.77  CPSW3_CPSW_NU_TX_G_BUF_THRESH_SET_L_REG Register
          78. 14.9.2.1.78  CPSW3_CPSW_NU_TX_G_BUF_THRESH_SET_H_REG Register
          79. 14.9.2.1.79  CPSW3_CPSW_NU_TX_G_BUF_THRESH_CLR_L_REG Register
          80. 14.9.2.1.80  CPSW3_CPSW_NU_TX_G_BUF_THRESH_CLR_H_REG Register
          81. 14.9.2.1.81  CPSW3_CPSW_NU_VLAN_LTYPE_REG Register
          82. 14.9.2.1.82  CPSW3_CPSW_NU_EST_TS_DOMAIN_REG Register
          83. 14.9.2.1.83  CPSW3_CPSW_NU_CUT_THRESHOLD_REG Register
          84. 14.9.2.1.84  CPSW3_CPSW_NU_FREQUENCY_REG Register
          85. 14.9.2.1.85  CPSW3_CPSW_NU_IET_HOLD_CNT_LD_VAL_REG Register
          86. 14.9.2.1.86  CPSW3_CPSW_NU_TX_PRI0_MAXLEN_REG Register
          87. 14.9.2.1.87  CPSW3_CPSW_NU_TX_PRI1_MAXLEN_REG Register
          88. 14.9.2.1.88  CPSW3_CPSW_NU_TX_PRI2_MAXLEN_REG Register
          89. 14.9.2.1.89  CPSW3_CPSW_NU_TX_PRI3_MAXLEN_REG Register
          90. 14.9.2.1.90  CPSW3_CPSW_NU_TX_PRI4_MAXLEN_REG Register
          91. 14.9.2.1.91  CPSW3_CPSW_NU_TX_PRI5_MAXLEN_REG Register
          92. 14.9.2.1.92  CPSW3_CPSW_NU_TX_PRI6_MAXLEN_REG Register
          93. 14.9.2.1.93  CPSW3_CPSW_NU_TX_PRI7_MAXLEN_REG Register
          94. 14.9.2.1.94  CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_CONTROL_REG Register
          95. 14.9.2.1.95  CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_FLOW_ID_OFFSET_REG Register
          96. 14.9.2.1.96  CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_BLK_CNT_REG Register
          97. 14.9.2.1.97  CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_PORT_VLAN_REG Register
          98. 14.9.2.1.98  CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_PRI_MAP_REG Register
          99. 14.9.2.1.99  CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_PRI_CTL_REG Register
          100. 14.9.2.1.100 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_RX_PRI_MAP_REG Register
          101. 14.9.2.1.101 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_RX_MAXLEN_REG Register
          102. 14.9.2.1.102 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_BLKS_PRI_REG Register
          103. 14.9.2.1.103 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_IDLE2LPI_REG Register
          104. 14.9.2.1.104 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_LPI2WAKE_REG Register
          105. 14.9.2.1.105 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_EEE_STATUS_REG Register
          106. 14.9.2.1.106 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_FIFO_STATUS_REG Register
          107. 14.9.2.1.107 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_RX_DSCP_MAP_REG_j Register
          108. 14.9.2.1.108 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_PRI_CIR_REG_j Register
          109. 14.9.2.1.109 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_PRI_EIR_REG_j Register
          110. 14.9.2.1.110 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_D_THRESH_SET_L_REG Register
          111. 14.9.2.1.111 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_D_THRESH_SET_H_REG Register
          112. 14.9.2.1.112 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_D_THRESH_CLR_L_REG Register
          113. 14.9.2.1.113 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_D_THRESH_CLR_H_REG Register
          114. 14.9.2.1.114 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_G_BUF_THRESH_SET_L_REG Register
          115. 14.9.2.1.115 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_G_BUF_THRESH_SET_H_REG Register
          116. 14.9.2.1.116 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_G_BUF_THRESH_CLR_L_REG Register
          117. 14.9.2.1.117 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_TX_G_BUF_THRESH_CLR_H_REG Register
          118. 14.9.2.1.118 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_SRC_ID_A_REG Register
          119. 14.9.2.1.119 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_SRC_ID_B_REG Register
          120. 14.9.2.1.120 CPSW3_CPSW_NU_CPSW_NU_CPPI_P0_HOST_BLKS_PRI_REG Register
          121. 14.9.2.1.121 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_RESERVED_REG Register
          122. 14.9.2.1.122 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_CONTROL_REG Register
          123. 14.9.2.1.123 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAX_BLKS_REG Register
          124. 14.9.2.1.124 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_BLK_CNT_REG Register
          125. 14.9.2.1.125 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_PORT_VLAN_REG Register
          126. 14.9.2.1.126 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_PRI_MAP_REG Register
          127. 14.9.2.1.127 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_PRI_CTL_REG Register
          128. 14.9.2.1.128 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_RX_PRI_MAP_REG Register
          129. 14.9.2.1.129 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_RX_MAXLEN_REG Register
          130. 14.9.2.1.130 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_BLKS_PRI_REG Register
          131. 14.9.2.1.131 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IDLE2LPI_REG Register
          132. 14.9.2.1.132 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_LPI2WAKE_REG Register
          133. 14.9.2.1.133 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_EEE_STATUS_REG Register
          134. 14.9.2.1.134 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IET_CONTROL_REG Register
          135. 14.9.2.1.135 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IET_STATUS_REG Register
          136. 14.9.2.1.136 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_IET_VERIFY_REG Register
          137. 14.9.2.1.137 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_FIFO_STATUS_REG Register
          138. 14.9.2.1.138 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_EST_CONTROL_REG Register
          139. 14.9.2.1.139 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_RX_DSCP_MAP_REG_j Register
          140. 14.9.2.1.140 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_PRI_CIR_REG_j Register
          141. 14.9.2.1.141 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_PRI_EIR_REG_j Register
          142. 14.9.2.1.142 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_D_THRESH_SET_L_REG Register
          143. 14.9.2.1.143 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_D_THRESH_SET_H_REG Register
          144. 14.9.2.1.144 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_D_THRESH_CLR_L_REG Register
          145. 14.9.2.1.145 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_D_THRESH_CLR_H_REG Register
          146. 14.9.2.1.146 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_G_BUF_THRESH_SET_L_REG Register
          147. 14.9.2.1.147 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_G_BUF_THRESH_SET_H_REG Register
          148. 14.9.2.1.148 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_G_BUF_THRESH_CLR_L_REG Register
          149. 14.9.2.1.149 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_G_BUF_THRESH_CLR_H_REG Register
          150. 14.9.2.1.150 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_D_OFLOW_ADDVAL_L_REG Register
          151. 14.9.2.1.151 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TX_D_OFLOW_ADDVAL_H_REG Register
          152. 14.9.2.1.152 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_SA_L_REG Register
          153. 14.9.2.1.153 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_SA_H_REG Register
          154. 14.9.2.1.154 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TS_CTL_REG Register
          155. 14.9.2.1.155 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TS_SEQ_LTYPE_REG Register
          156. 14.9.2.1.156 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TS_VLAN_LTYPE_REG Register
          157. 14.9.2.1.157 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TS_CTL_LTYPE2_REG Register
          158. 14.9.2.1.158 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_TS_CTL2_REG Register
          159. 14.9.2.1.159 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_CONTROL_REG Register
          160. 14.9.2.1.160 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_STATUS_REG Register
          161. 14.9.2.1.161 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_SOFT_RESET_REG Register
          162. 14.9.2.1.162 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_BOFFTEST_REG Register
          163. 14.9.2.1.163 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_RX_PAUSETIMER_REG Register
          164. 14.9.2.1.164 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_RXN_PAUSETIMER_REG_j Register
          165. 14.9.2.1.165 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_TX_PAUSETIMER_REG Register
          166. 14.9.2.1.166 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_TXN_PAUSETIMER_REG_j Register
          167. 14.9.2.1.167 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_EMCONTROL_REG Register
          168. 14.9.2.1.168 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_TX_GAP_REG Register
          169. 14.9.2.1.169 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_MAC_PORT_CONFIG Register
          170. 14.9.2.1.170 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_INTERVLAN_OPX_POINTER_REG Register
          171. 14.9.2.1.171 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_INTERVLAN_OPX_A_REG Register
          172. 14.9.2.1.172 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_INTERVLAN_OPX_B_REG Register
          173. 14.9.2.1.173 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_INTERVLAN_OPX_C_REG Register
          174. 14.9.2.1.174 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_INTERVLAN_OPX_D_REG Register
          175. 14.9.2.1.175 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_CUT_THRU_REG Register
          176. 14.9.2.1.176 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_0_PN_PORT_SPEED_REG Register
          177. 14.9.2.1.177 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_RESERVED_REG Register
          178. 14.9.2.1.178 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_CONTROL_REG Register
          179. 14.9.2.1.179 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAX_BLKS_REG Register
          180. 14.9.2.1.180 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_BLK_CNT_REG Register
          181. 14.9.2.1.181 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_PORT_VLAN_REG Register
          182. 14.9.2.1.182 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_PRI_MAP_REG Register
          183. 14.9.2.1.183 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_PRI_CTL_REG Register
          184. 14.9.2.1.184 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_RX_PRI_MAP_REG Register
          185. 14.9.2.1.185 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_RX_MAXLEN_REG Register
          186. 14.9.2.1.186 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_BLKS_PRI_REG Register
          187. 14.9.2.1.187 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_IDLE2LPI_REG Register
          188. 14.9.2.1.188 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_LPI2WAKE_REG Register
          189. 14.9.2.1.189 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_EEE_STATUS_REG Register
          190. 14.9.2.1.190 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_IET_CONTROL_REG Register
          191. 14.9.2.1.191 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_IET_STATUS_REG Register
          192. 14.9.2.1.192 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_IET_VERIFY_REG Register
          193. 14.9.2.1.193 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_FIFO_STATUS_REG Register
          194. 14.9.2.1.194 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_EST_CONTROL_REG Register
          195. 14.9.2.1.195 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_RX_DSCP_MAP_REG_j Register
          196. 14.9.2.1.196 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_PRI_CIR_REG_j Register
          197. 14.9.2.1.197 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_PRI_EIR_REG_j Register
          198. 14.9.2.1.198 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_D_THRESH_SET_L_REG Register
          199. 14.9.2.1.199 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_D_THRESH_SET_H_REG Register
          200. 14.9.2.1.200 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_D_THRESH_CLR_L_REG Register
          201. 14.9.2.1.201 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_D_THRESH_CLR_H_REG Register
          202. 14.9.2.1.202 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_G_BUF_THRESH_SET_L_REG Register
          203. 14.9.2.1.203 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_G_BUF_THRESH_SET_H_REG Register
          204. 14.9.2.1.204 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_G_BUF_THRESH_CLR_L_REG Register
          205. 14.9.2.1.205 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_G_BUF_THRESH_CLR_H_REG Register
          206. 14.9.2.1.206 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_D_OFLOW_ADDVAL_L_REG Register
          207. 14.9.2.1.207 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TX_D_OFLOW_ADDVAL_H_REG Register
          208. 14.9.2.1.208 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_SA_L_REG Register
          209. 14.9.2.1.209 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_SA_H_REG Register
          210. 14.9.2.1.210 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TS_CTL_REG Register
          211. 14.9.2.1.211 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TS_SEQ_LTYPE_REG Register
          212. 14.9.2.1.212 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TS_VLAN_LTYPE_REG Register
          213. 14.9.2.1.213 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TS_CTL_LTYPE2_REG Register
          214. 14.9.2.1.214 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_TS_CTL2_REG Register
          215. 14.9.2.1.215 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_CONTROL_REG Register
          216. 14.9.2.1.216 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_STATUS_REG Register
          217. 14.9.2.1.217 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_SOFT_RESET_REG Register
          218. 14.9.2.1.218 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_BOFFTEST_REG Register
          219. 14.9.2.1.219 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_RX_PAUSETIMER_REG Register
          220. 14.9.2.1.220 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_RXN_PAUSETIMER_REG_j Register
          221. 14.9.2.1.221 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_TX_PAUSETIMER_REG Register
          222. 14.9.2.1.222 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_TXN_PAUSETIMER_REG_j Register
          223. 14.9.2.1.223 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_EMCONTROL_REG Register
          224. 14.9.2.1.224 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_TX_GAP_REG Register
          225. 14.9.2.1.225 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_MAC_PORT_CONFIG Register
          226. 14.9.2.1.226 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_INTERVLAN_OPX_POINTER_REG Register
          227. 14.9.2.1.227 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_INTERVLAN_OPX_A_REG Register
          228. 14.9.2.1.228 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_INTERVLAN_OPX_B_REG Register
          229. 14.9.2.1.229 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_INTERVLAN_OPX_C_REG Register
          230. 14.9.2.1.230 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_INTERVLAN_OPX_D_REG Register
          231. 14.9.2.1.231 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_CUT_THRU_REG Register
          232. 14.9.2.1.232 CPSW3_CPSW_NU_CPSW_NU_ETH_MAC_1_PN_PORT_SPEED_REG Register
          233. 14.9.2.1.233 CPSW3_CPSW_NU_CPSW_NU_EST_FETCH_LOC_j Register
          234. 14.9.2.1.234 CPSW3_CPSW_NU_CPSW_NU_STAT_RXGOODFRAMES_j Register
          235. 14.9.2.1.235 CPSW3_CPSW_NU_CPSW_NU_STAT_RXBROADCASTFRAMES_j Register
          236. 14.9.2.1.236 CPSW3_CPSW_NU_CPSW_NU_STAT_RXMULTICASTFRAMES_j Register
          237. 14.9.2.1.237 CPSW3_CPSW_NU_CPSW_NU_STAT_RXPAUSEFRAMES_j Register
          238. 14.9.2.1.238 CPSW3_CPSW_NU_CPSW_NU_STAT_RXCRCERRORS_j Register
          239. 14.9.2.1.239 CPSW3_CPSW_NU_CPSW_NU_STAT_RXALIGNCODEERRORS_j Register
          240. 14.9.2.1.240 CPSW3_CPSW_NU_CPSW_NU_STAT_RXOVERSIZEDFRAMES_j Register
          241. 14.9.2.1.241 CPSW3_CPSW_NU_CPSW_NU_STAT_RXJABBERFRAMES_j Register
          242. 14.9.2.1.242 CPSW3_CPSW_NU_CPSW_NU_STAT_RXUNDERSIZEDFRAMES_j Register
          243. 14.9.2.1.243 CPSW3_CPSW_NU_CPSW_NU_STAT_RXFRAGMENTS_j Register
          244. 14.9.2.1.244 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_DROP_j Register
          245. 14.9.2.1.245 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_OVERRUN_DROP_j Register
          246. 14.9.2.1.246 CPSW3_CPSW_NU_CPSW_NU_STAT_RXOCTETS_j Register
          247. 14.9.2.1.247 CPSW3_CPSW_NU_CPSW_NU_STAT_TXGOODFRAMES_j Register
          248. 14.9.2.1.248 CPSW3_CPSW_NU_CPSW_NU_STAT_TXBROADCASTFRAMES_j Register
          249. 14.9.2.1.249 CPSW3_CPSW_NU_CPSW_NU_STAT_TXMULTICASTFRAMES_j Register
          250. 14.9.2.1.250 CPSW3_CPSW_NU_CPSW_NU_STAT_TXPAUSEFRAMES_j Register
          251. 14.9.2.1.251 CPSW3_CPSW_NU_CPSW_NU_STAT_TXDEFERREDFRAMES_j Register
          252. 14.9.2.1.252 CPSW3_CPSW_NU_CPSW_NU_STAT_TXCOLLISIONFRAMES_j Register
          253. 14.9.2.1.253 CPSW3_CPSW_NU_CPSW_NU_STAT_TXSINGLECOLLFRAMES_j Register
          254. 14.9.2.1.254 CPSW3_CPSW_NU_CPSW_NU_STAT_TXMULTCOLLFRAMES_j Register
          255. 14.9.2.1.255 CPSW3_CPSW_NU_CPSW_NU_STAT_TXEXCESSIVECOLLISIONS_j Register
          256. 14.9.2.1.256 CPSW3_CPSW_NU_CPSW_NU_STAT_TXLATECOLLISIONS_j Register
          257. 14.9.2.1.257 CPSW3_CPSW_NU_CPSW_NU_STAT_RXIPGERROR_j Register
          258. 14.9.2.1.258 CPSW3_CPSW_NU_CPSW_NU_STAT_TXCARRIERSENSEERRORS_j Register
          259. 14.9.2.1.259 CPSW3_CPSW_NU_CPSW_NU_STAT_TXOCTETS_j Register
          260. 14.9.2.1.260 CPSW3_CPSW_NU_CPSW_NU_STAT_OCTETFRAMES64_j Register
          261. 14.9.2.1.261 CPSW3_CPSW_NU_CPSW_NU_STAT_OCTETFRAMES65T127_j Register
          262. 14.9.2.1.262 CPSW3_CPSW_NU_CPSW_NU_STAT_OCTETFRAMES128T255_j Register
          263. 14.9.2.1.263 CPSW3_CPSW_NU_CPSW_NU_STAT_OCTETFRAMES256T511_j Register
          264. 14.9.2.1.264 CPSW3_CPSW_NU_CPSW_NU_STAT_OCTETFRAMES512T1023_j Register
          265. 14.9.2.1.265 CPSW3_CPSW_NU_CPSW_NU_STAT_OCTETFRAMES1024TUP_j Register
          266. 14.9.2.1.266 CPSW3_CPSW_NU_CPSW_NU_STAT_NETOCTETS_j Register
          267. 14.9.2.1.267 CPSW3_CPSW_NU_CPSW_NU_STAT_RX_BOTTOM_OF_FIFO_DROP_j Register
          268. 14.9.2.1.268 CPSW3_CPSW_NU_CPSW_NU_STAT_PORTMASK_DROP_j Register
          269. 14.9.2.1.269 CPSW3_CPSW_NU_CPSW_NU_STAT_RX_TOP_OF_FIFO_DROP_j Register
          270. 14.9.2.1.270 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_RATE_LIMIT_DROP_j Register
          271. 14.9.2.1.271 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_VID_INGRESS_DROP_j Register
          272. 14.9.2.1.272 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_DA_EQ_SA_DROP_j Register
          273. 14.9.2.1.273 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_BLOCK_DROP_j Register
          274. 14.9.2.1.274 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_SECURE_DROP_j Register
          275. 14.9.2.1.275 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_AUTH_DROP_j Register
          276. 14.9.2.1.276 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_UNKN_UNI_j Register
          277. 14.9.2.1.277 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_UNKN_UNI_BCNT_j Register
          278. 14.9.2.1.278 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_UNKN_MLT_j Register
          279. 14.9.2.1.279 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_UNKN_MLT_BCNT_j Register
          280. 14.9.2.1.280 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_UNKN_BRD_j Register
          281. 14.9.2.1.281 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_UNKN_BRD_BCNT_j Register
          282. 14.9.2.1.282 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_POL_MATCH_j Register
          283. 14.9.2.1.283 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_POL_MATCH_RED_j Register
          284. 14.9.2.1.284 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_POL_MATCH_YELLOW_j Register
          285. 14.9.2.1.285 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_MULT_SA_DROP_j Register
          286. 14.9.2.1.286 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_DUAL_VLAN_DROP_j Register
          287. 14.9.2.1.287 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_LEN_ERROR_DROP_j Register
          288. 14.9.2.1.288 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_IP_NEXT_HDR_DROP_j Register
          289. 14.9.2.1.289 CPSW3_CPSW_NU_CPSW_NU_STAT_ALE_IPV4_FRAG_DROP_j Register
          290. 14.9.2.1.290 CPSW3_CPSW_NU_CPSW_NU_STAT_IET_RX_ASSEMBLY_ERROR_REG_j Register
          291. 14.9.2.1.291 CPSW3_CPSW_NU_CPSW_NU_STAT_IET_RX_ASSEMBLY_OK_REG_j Register
          292. 14.9.2.1.292 CPSW3_CPSW_NU_CPSW_NU_STAT_IET_RX_SMD_ERROR_REG_j Register
          293. 14.9.2.1.293 CPSW3_CPSW_NU_CPSW_NU_STAT_IET_RX_FRAG_REG_j Register
          294. 14.9.2.1.294 CPSW3_CPSW_NU_CPSW_NU_STAT_IET_TX_HOLD_REG_j Register
          295. 14.9.2.1.295 CPSW3_CPSW_NU_CPSW_NU_STAT_IET_TX_FRAG_REG_j Register
          296. 14.9.2.1.296 CPSW3_CPSW_NU_CPSW_NU_STAT_TX_MEMORY_PROTECT_ERROR_j Register
          297. 14.9.2.1.297 CPSW3_CPSW_NU_CPSW_NU_STAT_ENET_PN_TX_PRI_REG_j_k Register
          298. 14.9.2.1.298 CPSW3_CPSW_NU_CPSW_NU_STAT_ENET_PN_TX_PRI_BCNT_REG_j_k Register
          299. 14.9.2.1.299 CPSW3_CPSW_NU_CPSW_NU_STAT_ENET_PN_TX_PRI_DROP_REG_j_k Register
          300. 14.9.2.1.300 CPSW3_CPSW_NU_CPSW_NU_STAT_ENET_PN_TX_PRI_DROP_BCNT_REG_j_k Register
          301. 14.9.2.1.301 CPSW3_CPSW_NU_CPTS_IDVER_REG Register
          302. 14.9.2.1.302 CPSW3_CPSW_NU_CPTS_CONTROL_REG Register
          303. 14.9.2.1.303 CPSW3_CPSW_NU_CPTS_RFTCLK_SEL_REG Register
          304. 14.9.2.1.304 CPSW3_CPSW_NU_CPTS_TS_PUSH_REG Register
          305. 14.9.2.1.305 CPSW3_CPSW_NU_CPTS_TS_LOAD_VAL_REG Register
          306. 14.9.2.1.306 CPSW3_CPSW_NU_CPTS_TS_LOAD_EN_REG Register
          307. 14.9.2.1.307 CPSW3_CPSW_NU_CPTS_TS_COMP_VAL_REG Register
          308. 14.9.2.1.308 CPSW3_CPSW_NU_CPTS_TS_COMP_LEN_REG Register
          309. 14.9.2.1.309 CPSW3_CPSW_NU_CPTS_INTSTAT_RAW_REG Register
          310. 14.9.2.1.310 CPSW3_CPSW_NU_CPTS_INTSTAT_MASKED_REG Register
          311. 14.9.2.1.311 CPSW3_CPSW_NU_CPTS_INT_ENABLE_REG Register
          312. 14.9.2.1.312 CPSW3_CPSW_NU_CPTS_TS_COMP_NUDGE_REG Register
          313. 14.9.2.1.313 CPSW3_CPSW_NU_CPTS_EVENT_POP_REG Register
          314. 14.9.2.1.314 CPSW3_CPSW_NU_CPTS_EVENT_0_REG Register
          315. 14.9.2.1.315 CPSW3_CPSW_NU_CPTS_EVENT_1_REG Register
          316. 14.9.2.1.316 CPSW3_CPSW_NU_CPTS_EVENT_2_REG Register
          317. 14.9.2.1.317 CPSW3_CPSW_NU_CPTS_EVENT_3_REG Register
          318. 14.9.2.1.318 CPSW3_CPSW_NU_CPTS_TS_LOAD_HIGH_VAL_REG Register
          319. 14.9.2.1.319 CPSW3_CPSW_NU_CPTS_TS_COMP_HIGH_VAL_REG Register
          320. 14.9.2.1.320 CPSW3_CPSW_NU_CPTS_TS_ADD_VAL_REG Register
          321. 14.9.2.1.321 CPSW3_CPSW_NU_CPTS_TS_PPM_LOW_VAL_REG Register
          322. 14.9.2.1.322 CPSW3_CPSW_NU_CPTS_TS_PPM_HIGH_VAL_REG Register
          323. 14.9.2.1.323 CPSW3_CPSW_NU_CPTS_TS_NUDGE_VAL_REG Register
          324. 14.9.2.1.324 CPSW3_CPSW_NU_CPTS_TS_CONFIG Register
          325. 14.9.2.1.325 CPSW3_CPSW_NU_CPTS_TS_GENF_COMP_LOW_REG_j Register
          326. 14.9.2.1.326 CPSW3_CPSW_NU_CPTS_TS_GENF_COMP_HIGH_REG_j Register
          327. 14.9.2.1.327 CPSW3_CPSW_NU_CPTS_TS_GENF_CONTROL_REG_j Register
          328. 14.9.2.1.328 CPSW3_CPSW_NU_CPTS_TS_GENF_LENGTH_REG_j Register
          329. 14.9.2.1.329 CPSW3_CPSW_NU_CPTS_TS_GENF_PPM_LOW_REG_j Register
          330. 14.9.2.1.330 CPSW3_CPSW_NU_CPTS_TS_GENF_PPM_HIGH_REG_j Register
          331. 14.9.2.1.331 CPSW3_CPSW_NU_CPTS_TS_GENF_NUDGE_REG_j Register
          332. 14.9.2.1.332 CPSW3_CPSW_NU_CPTS_TS_ESTF_COMP_LOW_REG_j Register
          333. 14.9.2.1.333 CPSW3_CPSW_NU_CPTS_TS_ESTF_COMP_HIGH_REG_j Register
          334. 14.9.2.1.334 CPSW3_CPSW_NU_CPTS_TS_ESTF_CONTROL_REG_j Register
          335. 14.9.2.1.335 CPSW3_CPSW_NU_CPTS_TS_ESTF_LENGTH_REG_j Register
          336. 14.9.2.1.336 CPSW3_CPSW_NU_CPTS_TS_ESTF_PPM_LOW_REG_j Register
          337. 14.9.2.1.337 CPSW3_CPSW_NU_CPTS_TS_ESTF_PPM_HIGH_REG_j Register
          338. 14.9.2.1.338 CPSW3_CPSW_NU_CPTS_TS_ESTF_NUDGE_REG_j Register
          339. 14.9.2.1.339 CPSW3_CPSW_NU_ALE_MOD_VER Register
          340. 14.9.2.1.340 CPSW3_CPSW_NU_ALE_ALE_STATUS Register
          341. 14.9.2.1.341 CPSW3_CPSW_NU_ALE_ALE_CONTROL Register
          342. 14.9.2.1.342 CPSW3_CPSW_NU_ALE_ALE_CTRL2 Register
          343. 14.9.2.1.343 CPSW3_CPSW_NU_ALE_ALE_PRESCALE Register
          344. 14.9.2.1.344 CPSW3_CPSW_NU_ALE_ALE_AGING_CTRL Register
          345. 14.9.2.1.345 CPSW3_CPSW_NU_ALE_ALE_NXT_HDR Register
          346. 14.9.2.1.346 CPSW3_CPSW_NU_ALE_ALE_TBLCTL Register
          347. 14.9.2.1.347 CPSW3_CPSW_NU_ALE_ALE_TBLW2 Register
          348. 14.9.2.1.348 CPSW3_CPSW_NU_ALE_ALE_TBLW1 Register
          349. 14.9.2.1.349 CPSW3_CPSW_NU_ALE_ALE_TBLW0 Register
          350. 14.9.2.1.350 CPSW3_CPSW_NU_ALE_I0_ALE_PORTCTL0_j Register
          351. 14.9.2.1.351 CPSW3_CPSW_NU_ALE_ALE_UVLAN_MEMBER Register
          352. 14.9.2.1.352 CPSW3_CPSW_NU_ALE_ALE_UVLAN_URCAST Register
          353. 14.9.2.1.353 CPSW3_CPSW_NU_ALE_ALE_UVLAN_RMCAST Register
          354. 14.9.2.1.354 CPSW3_CPSW_NU_ALE_ALE_UVLAN_UNTAG Register
          355. 14.9.2.1.355 CPSW3_CPSW_NU_ALE_ALE_STAT_DIAG Register
          356. 14.9.2.1.356 CPSW3_CPSW_NU_ALE_ALE_OAM_LB_CTRL Register
          357. 14.9.2.1.357 CPSW3_CPSW_NU_ALE_EGRESSOP Register
          358. 14.9.2.1.358 CPSW3_CPSW_NU_ALE_POLICECFG0 Register
          359. 14.9.2.1.359 CPSW3_CPSW_NU_ALE_POLICECFG1 Register
          360. 14.9.2.1.360 CPSW3_CPSW_NU_ALE_POLICECFG2 Register
          361. 14.9.2.1.361 CPSW3_CPSW_NU_ALE_POLICECFG3 Register
          362. 14.9.2.1.362 CPSW3_CPSW_NU_ALE_POLICECFG4 Register
          363. 14.9.2.1.363 CPSW3_CPSW_NU_ALE_POLICECFG6 Register
          364. 14.9.2.1.364 CPSW3_CPSW_NU_ALE_POLICECFG7 Register
          365. 14.9.2.1.365 CPSW3_CPSW_NU_ALE_POLICETBLCTL Register
          366. 14.9.2.1.366 CPSW3_CPSW_NU_ALE_POLICECONTROL Register
          367. 14.9.2.1.367 CPSW3_CPSW_NU_ALE_POLICETESTCTL Register
          368. 14.9.2.1.368 CPSW3_CPSW_NU_ALE_POLICEHSTAT Register
          369. 14.9.2.1.369 CPSW3_CPSW_NU_ALE_THREADMAPDEF Register
          370. 14.9.2.1.370 CPSW3_CPSW_NU_ALE_THREADMAPCTL Register
          371. 14.9.2.1.371 CPSW3_CPSW_NU_ALE_THREADMAPVAL Register
        2. 14.9.2.2 PCIe
          1. 14.9.2.2.1 PCIe Summaries
            1.         8520
            2.         8521
            3.         8522
            4.         8523
            5.         8524
            6.         8525
            7.         8526
            8.         8527
            9.         8528
          2. 14.9.2.2.2 PCIe Registers
            1. 14.9.2.2.2.1   ECC_AGGR_REV Register
            2. 14.9.2.2.2.2   ECC_AGGR_VECTOR Register
            3. 14.9.2.2.2.3   ECC_AGGR_STAT Register
            4. 14.9.2.2.2.4   ECC_AGGR_RESERVED_SVBUS_j Register
            5. 14.9.2.2.2.5   ECC_AGGR_SEC_EOI_REG Register
            6. 14.9.2.2.2.6   ECC_AGGR_SEC_STATUS_REG0 Register
            7. 14.9.2.2.2.7   ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            8. 14.9.2.2.2.8   ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            9. 14.9.2.2.2.9   ECC_AGGR_DED_EOI_REG Register
            10. 14.9.2.2.2.10  ECC_AGGR_DED_STATUS_REG0 Register
            11. 14.9.2.2.2.11  ECC_AGGR_DED_ENABLE_SET_REG0 Register
            12. 14.9.2.2.2.12  ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            13. 14.9.2.2.2.13  ECC_AGGR_AGGR_ENABLE_SET Register
            14. 14.9.2.2.2.14  ECC_AGGR_AGGR_ENABLE_CLR Register
            15. 14.9.2.2.2.15  ECC_AGGR_AGGR_STATUS_SET Register
            16. 14.9.2.2.2.16  ECC_AGGR_AGGR_STATUS_CLR Register
            17. 14.9.2.2.2.17  ECC_AGGR_REV Register
            18. 14.9.2.2.2.18  ECC_AGGR_VECTOR Register
            19. 14.9.2.2.2.19  ECC_AGGR_STAT Register
            20. 14.9.2.2.2.20  ECC_AGGR_RESERVED_SVBUS_j Register
            21. 14.9.2.2.2.21  ECC_AGGR_SEC_EOI_REG Register
            22. 14.9.2.2.2.22  ECC_AGGR_SEC_STATUS_REG0 Register
            23. 14.9.2.2.2.23  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            24. 14.9.2.2.2.24  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            25. 14.9.2.2.2.25  ECC_AGGR_DED_EOI_REG Register
            26. 14.9.2.2.2.26  ECC_AGGR_DED_STATUS_REG0 Register
            27. 14.9.2.2.2.27  ECC_AGGR_DED_ENABLE_SET_REG0 Register
            28. 14.9.2.2.2.28  ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            29. 14.9.2.2.2.29  ECC_AGGR_AGGR_ENABLE_SET Register
            30. 14.9.2.2.2.30  ECC_AGGR_AGGR_ENABLE_CLR Register
            31. 14.9.2.2.2.31  ECC_AGGR_AGGR_STATUS_SET Register
            32. 14.9.2.2.2.32  ECC_AGGR_AGGR_STATUS_CLR Register
            33. 14.9.2.2.2.33  PCIE_CORE_RC_I_RC_PCIE_BASE_I_VENDOR_ID_DEVICE_ID Register
            34. 14.9.2.2.2.34  PCIE_CORE_RC_I_RC_PCIE_BASE_I_COMMAND_STATUS Register
            35. 14.9.2.2.2.35  PCIE_CORE_RC_I_RC_PCIE_BASE_I_REVISION_ID_CLASS_CODE Register
            36. 14.9.2.2.2.36  PCIE_CORE_RC_I_RC_PCIE_BASE_I_BIST_HEADER_LATENCY_CACHE_LINE Register
            37. 14.9.2.2.2.37  PCIE_CORE_RC_I_RC_PCIE_BASE_I_RC_BAR_0 Register
            38. 14.9.2.2.2.38  PCIE_CORE_RC_I_RC_PCIE_BASE_I_RC_BAR_1 Register
            39. 14.9.2.2.2.39  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_BUS_NUMBERS Register
            40. 14.9.2.2.2.40  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_IO_BASE_LIMIT Register
            41. 14.9.2.2.2.41  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_MEM_BASE_LIMIT Register
            42. 14.9.2.2.2.42  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_PREFETCH_BASE_LIMIT Register
            43. 14.9.2.2.2.43  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_PREFETCH_BASE_UPPER Register
            44. 14.9.2.2.2.44  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_PREFETCH_LIMIT_UPPER Register
            45. 14.9.2.2.2.45  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_IO_BASE_LIMIT_UPPER Register
            46. 14.9.2.2.2.46  PCIE_CORE_RC_I_RC_PCIE_BASE_I_CAPABILITIES_POINTER Register
            47. 14.9.2.2.2.47  PCIE_CORE_RC_I_RC_PCIE_BASE_RSVD_0E Register
            48. 14.9.2.2.2.48  PCIE_CORE_RC_I_RC_PCIE_BASE_I_INTRPT_LINE_INTRPT_PIN Register
            49. 14.9.2.2.2.49  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PWR_MGMT_CAP Register
            50. 14.9.2.2.2.50  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PWR_MGMT_CTRL_STAT_REP Register
            51. 14.9.2.2.2.51  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSI_CTRL_REG Register
            52. 14.9.2.2.2.52  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_LOW_ADDR Register
            53. 14.9.2.2.2.53  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_HI_ADDR Register
            54. 14.9.2.2.2.54  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSI_MSG_DATA Register
            55. 14.9.2.2.2.55  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSI_MASK Register
            56. 14.9.2.2.2.56  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSI_PENDING_BITS Register
            57. 14.9.2.2.2.57  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSIX_CTRL Register
            58. 14.9.2.2.2.58  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSIX_TBL_OFFSET Register
            59. 14.9.2.2.2.59  PCIE_CORE_RC_I_RC_PCIE_BASE_I_MSIX_PENDING_INTRPT Register
            60. 14.9.2.2.2.60  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_CAP_LIST Register
            61. 14.9.2.2.2.61  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_CAP Register
            62. 14.9.2.2.2.62  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS Register
            63. 14.9.2.2.2.63  PCIE_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP Register
            64. 14.9.2.2.2.64  PCIE_CORE_RC_I_RC_PCIE_BASE_I_LINK_CTRL_STATUS Register
            65. 14.9.2.2.2.65  PCIE_CORE_RC_I_RC_PCIE_BASE_I_SLOT_CAPABILITY Register
            66. 14.9.2.2.2.66  PCIE_CORE_RC_I_RC_PCIE_BASE_I_SLOT_CTRL_STATUS Register
            67. 14.9.2.2.2.67  PCIE_CORE_RC_I_RC_PCIE_BASE_I_ROOT_CTRL_CAP Register
            68. 14.9.2.2.2.68  PCIE_CORE_RC_I_RC_PCIE_BASE_I_ROOT_STATUS Register
            69. 14.9.2.2.2.69  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_CAP_2 Register
            70. 14.9.2.2.2.70  PCIE_CORE_RC_I_RC_PCIE_BASE_I_PCIE_DEV_CTRL_STATUS_2 Register
            71. 14.9.2.2.2.71  PCIE_CORE_RC_I_RC_PCIE_BASE_I_LINK_CAP_2 Register
            72. 14.9.2.2.2.72  PCIE_CORE_RC_I_RC_PCIE_BASE_I_LINK_CTRL_STATUS_2 Register
            73. 14.9.2.2.2.73  PCIE_CORE_RC_I_RC_PCIE_BASE_I_AER_ENHNCD_CAP Register
            74. 14.9.2.2.2.74  PCIE_CORE_RC_I_RC_PCIE_BASE_I_UNCORR_ERR_STATUS Register
            75. 14.9.2.2.2.75  PCIE_CORE_RC_I_RC_PCIE_BASE_I_UNCORR_ERR_MASK Register
            76. 14.9.2.2.2.76  PCIE_CORE_RC_I_RC_PCIE_BASE_I_UNCORR_ERR_SEVERITY Register
            77. 14.9.2.2.2.77  PCIE_CORE_RC_I_RC_PCIE_BASE_I_CORR_ERR_STATUS Register
            78. 14.9.2.2.2.78  PCIE_CORE_RC_I_RC_PCIE_BASE_I_CORR_ERR_MASK Register
            79. 14.9.2.2.2.79  PCIE_CORE_RC_I_RC_PCIE_BASE_I_ADV_ERR_CAP_CTL Register
            80. 14.9.2.2.2.80  PCIE_CORE_RC_I_RC_PCIE_BASE_I_HDR_LOG_0 Register
            81. 14.9.2.2.2.81  PCIE_CORE_RC_I_RC_PCIE_BASE_I_HDR_LOG_1 Register
            82. 14.9.2.2.2.82  PCIE_CORE_RC_I_RC_PCIE_BASE_I_HDR_LOG_2 Register
            83. 14.9.2.2.2.83  PCIE_CORE_RC_I_RC_PCIE_BASE_I_HDR_LOG_3 Register
            84. 14.9.2.2.2.84  PCIE_CORE_RC_I_RC_PCIE_BASE_I_ROOT_ERR_CMD Register
            85. 14.9.2.2.2.85  PCIE_CORE_RC_I_RC_PCIE_BASE_I_ROOT_ERR_STAT Register
            86. 14.9.2.2.2.86  PCIE_CORE_RC_I_RC_PCIE_BASE_I_ERR_SRC_ID Register
            87. 14.9.2.2.2.87  PCIE_CORE_RC_I_RC_PCIE_BASE_I_TLP_PRE_LOG_0 Register
            88. 14.9.2.2.2.88  PCIE_CORE_RC_I_RC_PCIE_BASE_I_DEV_SER_NUM_CAP_HDR Register
            89. 14.9.2.2.2.89  PCIE_CORE_RC_I_RC_PCIE_BASE_I_DEV_SER_NUM_0 Register
            90. 14.9.2.2.2.90  PCIE_CORE_RC_I_RC_PCIE_BASE_I_DEV_SER_NUM_1 Register
            91. 14.9.2.2.2.91  PCIE_CORE_RC_I_RC_PCIE_BASE_I_SEC_PCIE_CAP_HDR_REG Register
            92. 14.9.2.2.2.92  PCIE_CORE_RC_I_RC_PCIE_BASE_I_LINK_CONTROL3 Register
            93. 14.9.2.2.2.93  PCIE_CORE_RC_I_RC_PCIE_BASE_I_LANE_ERROR_STATUS Register
            94. 14.9.2.2.2.94  PCIE_CORE_RC_I_RC_PCIE_BASE_I_LANE_EQUALIZATION_CONTROL_0 Register
            95. 14.9.2.2.2.95  PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_ENH_CAP_HEADER_REG Register
            96. 14.9.2.2.2.96  PCIE_CORE_RC_I_VC_CAP_STRUCT_I_PORT_VC_CAP_REG_1 Register
            97. 14.9.2.2.2.97  PCIE_CORE_RC_I_VC_CAP_STRUCT_I_PORT_VC_CAP_REG_2 Register
            98. 14.9.2.2.2.98  PCIE_CORE_RC_I_VC_CAP_STRUCT_I_PORT_VC_CTRL_STS_REG Register
            99. 14.9.2.2.2.99  PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_CAP_REG_0 Register
            100. 14.9.2.2.2.100 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_CTRL_REG_0 Register
            101. 14.9.2.2.2.101 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_STS_REG_0 Register
            102. 14.9.2.2.2.102 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_CAP_REG_1 Register
            103. 14.9.2.2.2.103 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_CTRL_REG_1 Register
            104. 14.9.2.2.2.104 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_STS_REG_1 Register
            105. 14.9.2.2.2.105 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_CAP_REG_2 Register
            106. 14.9.2.2.2.106 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_CTRL_REG_2 Register
            107. 14.9.2.2.2.107 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_STS_REG_2 Register
            108. 14.9.2.2.2.108 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_CAP_REG_3 Register
            109. 14.9.2.2.2.109 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_CTRL_REG_3 Register
            110. 14.9.2.2.2.110 PCIE_CORE_RC_I_VC_CAP_STRUCT_I_VC_RES_STS_REG_3 Register
            111. 14.9.2.2.2.111 PCIE_CORE_RC_I_REGF_L1_PM_CAP_STRUCT_I_L1_PM_EXT_CAP_HDR Register
            112. 14.9.2.2.2.112 PCIE_CORE_RC_I_REGF_L1_PM_CAP_STRUCT_I_L1_PM_CAP Register
            113. 14.9.2.2.2.113 PCIE_CORE_RC_I_REGF_L1_PM_CAP_STRUCT_I_L1_PM_CTRL_1 Register
            114. 14.9.2.2.2.114 PCIE_CORE_RC_I_REGF_L1_PM_CAP_STRUCT_I_L1_PM_CTRL_2 Register
            115. 14.9.2.2.2.115 PCIE_CORE_RC_I_REGF_PTM_CAP_I_PTM_EXTENDED_CAPABILITY_HEADER_REG Register
            116. 14.9.2.2.2.116 PCIE_CORE_RC_I_REGF_PTM_CAP_I_PTM_CAPABILITIES_REG Register
            117. 14.9.2.2.2.117 PCIE_CORE_RC_I_REGF_PTM_CAP_I_PTM_CONTROL_REG Register
            118. 14.9.2.2.2.118 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PL_CONFIG_0_REG Register
            119. 14.9.2.2.2.119 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PL_CONFIG_1_REG Register
            120. 14.9.2.2.2.120 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_DLL_TMR_CONFIG_REG Register
            121. 14.9.2.2.2.121 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_0_REG Register
            122. 14.9.2.2.2.122 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_1_REG Register
            123. 14.9.2.2.2.123 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_0_REG Register
            124. 14.9.2.2.2.124 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_1_REG Register
            125. 14.9.2.2.2.125 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_UPDATE_INT_CONFIG_0_REG Register
            126. 14.9.2.2.2.126 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_UPDATE_INT_CONFIG_1_REG Register
            127. 14.9.2.2.2.127 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_L0S_TIMEOUT_LIMIT_REG Register
            128. 14.9.2.2.2.128 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSMIT_TLP_COUNT_REG Register
            129. 14.9.2.2.2.129 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSMIT_TLP_PAYLOAD_DWORD_COUNT_REG Register
            130. 14.9.2.2.2.130 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RECEIVE_TLP_COUNT_REG Register
            131. 14.9.2.2.2.131 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RECEIVE_TLP_PAYLOAD_DWORD_COUNT_REG Register
            132. 14.9.2.2.2.132 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_COMPLN_TMOUT_LIM_0_REG Register
            133. 14.9.2.2.2.133 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_COMPLN_TMOUT_LIM_1_REG Register
            134. 14.9.2.2.2.134 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_L1_ST_REENTRY_DELAY_REG Register
            135. 14.9.2.2.2.135 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_VENDOR_ID_REG Register
            136. 14.9.2.2.2.136 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_ASPM_L1_ENTRY_TMOUT_DELAY_REG Register
            137. 14.9.2.2.2.137 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PME_TURNOFF_ACK_DELAY_REG Register
            138. 14.9.2.2.2.138 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LINKWIDTH_CONTROL_REG Register
            139. 14.9.2.2.2.139 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PL_CONFIG_2_REG Register
            140. 14.9.2.2.2.140 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_MULTI_VC_CONROL_REG Register
            141. 14.9.2.2.2.141 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_SRIS_CONTROL_REG Register
            142. 14.9.2.2.2.142 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_0_REG_VC1 Register
            143. 14.9.2.2.2.143 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_1_REG_VC1 Register
            144. 14.9.2.2.2.144 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_0_REG_VC1 Register
            145. 14.9.2.2.2.145 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_1_REG_VC1 Register
            146. 14.9.2.2.2.146 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_0_REG_VC2 Register
            147. 14.9.2.2.2.147 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_1_REG_VC2 Register
            148. 14.9.2.2.2.148 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_0_REG_VC2 Register
            149. 14.9.2.2.2.149 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_1_REG_VC2 Register
            150. 14.9.2.2.2.150 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_0_REG_VC3 Register
            151. 14.9.2.2.2.151 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RCV_CRED_LIM_1_REG_VC3 Register
            152. 14.9.2.2.2.152 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_0_REG_VC3 Register
            153. 14.9.2.2.2.153 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_TRANSM_CRED_LIM_1_REG_VC3 Register
            154. 14.9.2.2.2.154 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_FC_INIT_DELAY_REG Register
            155. 14.9.2.2.2.155 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_SHDW_HDR_LOG_0_REG Register
            156. 14.9.2.2.2.156 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_SHDW_HDR_LOG_1_REG Register
            157. 14.9.2.2.2.157 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_SHDW_HDR_LOG_2_REG Register
            158. 14.9.2.2.2.158 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_SHDW_HDR_LOG_3_REG Register
            159. 14.9.2.2.2.159 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_SHDW_FUNC_NUM_REG Register
            160. 14.9.2.2.2.160 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_SHDW_UR_ERR_REG Register
            161. 14.9.2.2.2.161 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PM_CLK_FREQUENCY_REG Register
            162. 14.9.2.2.2.162 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_DLLP_COUNT_GEN1_REG Register
            163. 14.9.2.2.2.163 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_DLLP_COUNT_GEN2_REG Register
            164. 14.9.2.2.2.164 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_DLLP_COUNT_GEN3_REG Register
            165. 14.9.2.2.2.165 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_VENDOR_DEFINED_MESSAGE_TAG_REG Register
            166. 14.9.2.2.2.166 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_NEGOTIATED_LANE_MAP_REG Register
            167. 14.9.2.2.2.167 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RECEIVE_FTS_COUNT_REG Register
            168. 14.9.2.2.2.168 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_MUX_CONTROL_REG Register
            169. 14.9.2.2.2.169 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LOCAL_ERROR_STATUS_REGISTER Register
            170. 14.9.2.2.2.170 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LOCAL_INTRPT_MASK_REG Register
            171. 14.9.2.2.2.171 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LCRC_ERR_COUNT_REG Register
            172. 14.9.2.2.2.172 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_ECC_CORR_ERR_COUNT_REG Register
            173. 14.9.2.2.2.173 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LTR_SNOOP_LAT_REG Register
            174. 14.9.2.2.2.174 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LTR_MSG_GEN_CTL_REG Register
            175. 14.9.2.2.2.175 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PME_SERVICE_TIMEOUT_DELAY_REG Register
            176. 14.9.2.2.2.176 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_ROOT_PORT_REQUESTOR_ID_REG Register
            177. 14.9.2.2.2.177 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_EP_BUS_DEVICE_NUMBER_REG Register
            178. 14.9.2.2.2.178 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_MUX_CONTROL_2_REG Register
            179. 14.9.2.2.2.179 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PHY_STATUS_1_REG Register
            180. 14.9.2.2.2.180 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_DEBUG_MUX_CONTROL_3_REG Register
            181. 14.9.2.2.2.181 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RC_BAR_CONFIG_REG Register
            182. 14.9.2.2.2.182 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_GEN3_DEFAULT_PRESET_REG Register
            183. 14.9.2.2.2.183 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_GEN3_LINK_EQ_TIMEOUT_2MS_REG Register
            184. 14.9.2.2.2.184 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PIPE_FIFO_LATENCY_CTRL_REG Register
            185. 14.9.2.2.2.185 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_GEN3_LINK_EQ_CTRL_REG Register
            186. 14.9.2.2.2.186 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_GEN3_LINK_EQ_DEBUG_STATUS_REG_LANE0 Register
            187. 14.9.2.2.2.187 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_ECC_CORR_ERR_COUNT_REG_AXI Register
            188. 14.9.2.2.2.188 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_LOW_POWER_DEBUG_AND_CONTROL0 Register
            189. 14.9.2.2.2.189 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_LOW_POWER_DEBUG_AND_CONTROL1 Register
            190. 14.9.2.2.2.190 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_LOW_POWER_DEBUG_AND_CONTROL2 Register
            191. 14.9.2.2.2.191 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_TL_INTERNAL_CONTROL Register
            192. 14.9.2.2.2.192 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LOCAL_ERROR_STATUS_2_REGISTER Register
            193. 14.9.2.2.2.193 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LOCAL_INTRPT_MASK_2_REG Register
            194. 14.9.2.2.2.194 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LD_CTRL Register
            195. 14.9.2.2.2.195 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_RX_ELEC_IDLE_FILTER_CONTROL Register
            196. 14.9.2.2.2.196 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_LOCAL_CONTROL_REG Register
            197. 14.9.2.2.2.197 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_LOCAL_STATUS_REG Register
            198. 14.9.2.2.2.198 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_LATENCY_PARAMETERS_INDEX_REG Register
            199. 14.9.2.2.2.199 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_LATENCY_PARAMETERS_REG Register
            200. 14.9.2.2.2.200 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_1_REG Register
            201. 14.9.2.2.2.201 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_2_REG Register
            202. 14.9.2.2.2.202 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_3_REG Register
            203. 14.9.2.2.2.203 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_4_REG Register
            204. 14.9.2.2.2.204 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_5_REG Register
            205. 14.9.2.2.2.205 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_6_REG Register
            206. 14.9.2.2.2.206 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_7_REG Register
            207. 14.9.2.2.2.207 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_8_REG Register
            208. 14.9.2.2.2.208 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_9_REG Register
            209. 14.9.2.2.2.209 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_10_REG Register
            210. 14.9.2.2.2.210 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_PTM_CONTEXT_11_REG Register
            211. 14.9.2.2.2.211 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_EQ_DEBUG_MON_CONTROL_REG Register
            212. 14.9.2.2.2.212 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_EQ_DEBUG_MON_STATUS0_REG Register
            213. 14.9.2.2.2.213 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_EQ_DEBUG_MON_STATUS_REG Register
            214. 14.9.2.2.2.214 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_AXI_FEATURE_REG Register
            215. 14.9.2.2.2.215 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_LINK_EQ_CONTROL_2_REG Register
            216. 14.9.2.2.2.216 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_CORE_FEATURE_REG Register
            217. 14.9.2.2.2.217 PCIE_CORE_LM_I_REGF_LM_PCIE_BASE_I_RX_INVERT_POLARITY_REG Register
            218. 14.9.2.2.2.218 PCIE_CORE_ATU_WRAPPER_OB_0_ADDR0 Register
            219. 14.9.2.2.2.219 PCIE_CORE_ATU_WRAPPER_OB_0_ADDR1 Register
            220. 14.9.2.2.2.220 PCIE_CORE_ATU_WRAPPER_OB_0_DESC0 Register
            221. 14.9.2.2.2.221 PCIE_CORE_ATU_WRAPPER_OB_0_DESC1 Register
            222. 14.9.2.2.2.222 PCIE_CORE_ATU_WRAPPER_OB_0_DESC3 Register
            223. 14.9.2.2.2.223 PCIE_CORE_ATU_WRAPPER_OB_0_AXI_ADDR0 Register
            224. 14.9.2.2.2.224 PCIE_CORE_ATU_WRAPPER_OB_0_AXI_ADDR1 Register
            225. 14.9.2.2.2.225 PCIE_CORE_ATU_WRAPPER_OB_1_ADDR0 Register
            226. 14.9.2.2.2.226 PCIE_CORE_ATU_WRAPPER_OB_1_ADDR1 Register
            227. 14.9.2.2.2.227 PCIE_CORE_ATU_WRAPPER_OB_1_DESC0 Register
            228. 14.9.2.2.2.228 PCIE_CORE_ATU_WRAPPER_OB_1_DESC1 Register
            229. 14.9.2.2.2.229 PCIE_CORE_ATU_WRAPPER_OB_1_DESC3 Register
            230. 14.9.2.2.2.230 PCIE_CORE_ATU_WRAPPER_OB_1_AXI_ADDR0 Register
            231. 14.9.2.2.2.231 PCIE_CORE_ATU_WRAPPER_OB_1_AXI_ADDR1 Register
            232. 14.9.2.2.2.232 PCIE_CORE_ATU_WRAPPER_OB_2_ADDR0 Register
            233. 14.9.2.2.2.233 PCIE_CORE_ATU_WRAPPER_OB_2_ADDR1 Register
            234. 14.9.2.2.2.234 PCIE_CORE_ATU_WRAPPER_OB_2_DESC0 Register
            235. 14.9.2.2.2.235 PCIE_CORE_ATU_WRAPPER_OB_2_DESC1 Register
            236. 14.9.2.2.2.236 PCIE_CORE_ATU_WRAPPER_OB_2_DESC3 Register
            237. 14.9.2.2.2.237 PCIE_CORE_ATU_WRAPPER_OB_2_AXI_ADDR0 Register
            238. 14.9.2.2.2.238 PCIE_CORE_ATU_WRAPPER_OB_2_AXI_ADDR1 Register
            239. 14.9.2.2.2.239 PCIE_CORE_ATU_WRAPPER_OB_3_ADDR0 Register
            240. 14.9.2.2.2.240 PCIE_CORE_ATU_WRAPPER_OB_3_ADDR1 Register
            241. 14.9.2.2.2.241 PCIE_CORE_ATU_WRAPPER_OB_3_DESC0 Register
            242. 14.9.2.2.2.242 PCIE_CORE_ATU_WRAPPER_OB_3_DESC1 Register
            243. 14.9.2.2.2.243 PCIE_CORE_ATU_WRAPPER_OB_3_DESC3 Register
            244. 14.9.2.2.2.244 PCIE_CORE_ATU_WRAPPER_OB_3_AXI_ADDR0 Register
            245. 14.9.2.2.2.245 PCIE_CORE_ATU_WRAPPER_OB_3_AXI_ADDR1 Register
            246. 14.9.2.2.2.246 PCIE_CORE_ATU_WRAPPER_OB_4_ADDR0 Register
            247. 14.9.2.2.2.247 PCIE_CORE_ATU_WRAPPER_OB_4_ADDR1 Register
            248. 14.9.2.2.2.248 PCIE_CORE_ATU_WRAPPER_OB_4_DESC0 Register
            249. 14.9.2.2.2.249 PCIE_CORE_ATU_WRAPPER_OB_4_DESC1 Register
            250. 14.9.2.2.2.250 PCIE_CORE_ATU_WRAPPER_OB_4_DESC3 Register
            251. 14.9.2.2.2.251 PCIE_CORE_ATU_WRAPPER_OB_4_AXI_ADDR0 Register
            252. 14.9.2.2.2.252 PCIE_CORE_ATU_WRAPPER_OB_4_AXI_ADDR1 Register
            253. 14.9.2.2.2.253 PCIE_CORE_ATU_WRAPPER_OB_5_ADDR0 Register
            254. 14.9.2.2.2.254 PCIE_CORE_ATU_WRAPPER_OB_5_ADDR1 Register
            255. 14.9.2.2.2.255 PCIE_CORE_ATU_WRAPPER_OB_5_DESC0 Register
            256. 14.9.2.2.2.256 PCIE_CORE_ATU_WRAPPER_OB_5_DESC1 Register
            257. 14.9.2.2.2.257 PCIE_CORE_ATU_WRAPPER_OB_5_DESC3 Register
            258. 14.9.2.2.2.258 PCIE_CORE_ATU_WRAPPER_OB_5_AXI_ADDR0 Register
            259. 14.9.2.2.2.259 PCIE_CORE_ATU_WRAPPER_OB_5_AXI_ADDR1 Register
            260. 14.9.2.2.2.260 PCIE_CORE_ATU_WRAPPER_OB_6_ADDR0 Register
            261. 14.9.2.2.2.261 PCIE_CORE_ATU_WRAPPER_OB_6_ADDR1 Register
            262. 14.9.2.2.2.262 PCIE_CORE_ATU_WRAPPER_OB_6_DESC0 Register
            263. 14.9.2.2.2.263 PCIE_CORE_ATU_WRAPPER_OB_6_DESC1 Register
            264. 14.9.2.2.2.264 PCIE_CORE_ATU_WRAPPER_OB_6_DESC3 Register
            265. 14.9.2.2.2.265 PCIE_CORE_ATU_WRAPPER_OB_6_AXI_ADDR0 Register
            266. 14.9.2.2.2.266 PCIE_CORE_ATU_WRAPPER_OB_6_AXI_ADDR1 Register
            267. 14.9.2.2.2.267 PCIE_CORE_ATU_WRAPPER_OB_7_ADDR0 Register
            268. 14.9.2.2.2.268 PCIE_CORE_ATU_WRAPPER_OB_7_ADDR1 Register
            269. 14.9.2.2.2.269 PCIE_CORE_ATU_WRAPPER_OB_7_DESC0 Register
            270. 14.9.2.2.2.270 PCIE_CORE_ATU_WRAPPER_OB_7_DESC1 Register
            271. 14.9.2.2.2.271 PCIE_CORE_ATU_WRAPPER_OB_7_DESC3 Register
            272. 14.9.2.2.2.272 PCIE_CORE_ATU_WRAPPER_OB_7_AXI_ADDR0 Register
            273. 14.9.2.2.2.273 PCIE_CORE_ATU_WRAPPER_OB_7_AXI_ADDR1 Register
            274. 14.9.2.2.2.274 PCIE_CORE_ATU_WRAPPER_OB_8_ADDR0 Register
            275. 14.9.2.2.2.275 PCIE_CORE_ATU_WRAPPER_OB_8_ADDR1 Register
            276. 14.9.2.2.2.276 PCIE_CORE_ATU_WRAPPER_OB_8_DESC0 Register
            277. 14.9.2.2.2.277 PCIE_CORE_ATU_WRAPPER_OB_8_DESC1 Register
            278. 14.9.2.2.2.278 PCIE_CORE_ATU_WRAPPER_OB_8_DESC3 Register
            279. 14.9.2.2.2.279 PCIE_CORE_ATU_WRAPPER_OB_8_AXI_ADDR0 Register
            280. 14.9.2.2.2.280 PCIE_CORE_ATU_WRAPPER_OB_8_AXI_ADDR1 Register
            281. 14.9.2.2.2.281 PCIE_CORE_ATU_WRAPPER_OB_9_ADDR0 Register
            282. 14.9.2.2.2.282 PCIE_CORE_ATU_WRAPPER_OB_9_ADDR1 Register
            283. 14.9.2.2.2.283 PCIE_CORE_ATU_WRAPPER_OB_9_DESC0 Register
            284. 14.9.2.2.2.284 PCIE_CORE_ATU_WRAPPER_OB_9_DESC1 Register
            285. 14.9.2.2.2.285 PCIE_CORE_ATU_WRAPPER_OB_9_DESC3 Register
            286. 14.9.2.2.2.286 PCIE_CORE_ATU_WRAPPER_OB_9_AXI_ADDR0 Register
            287. 14.9.2.2.2.287 PCIE_CORE_ATU_WRAPPER_OB_9_AXI_ADDR1 Register
            288. 14.9.2.2.2.288 PCIE_CORE_ATU_WRAPPER_OB_10_ADDR0 Register
            289. 14.9.2.2.2.289 PCIE_CORE_ATU_WRAPPER_OB_10_ADDR1 Register
            290. 14.9.2.2.2.290 PCIE_CORE_ATU_WRAPPER_OB_10_DESC0 Register
            291. 14.9.2.2.2.291 PCIE_CORE_ATU_WRAPPER_OB_10_DESC1 Register
            292. 14.9.2.2.2.292 PCIE_CORE_ATU_WRAPPER_OB_10_DESC3 Register
            293. 14.9.2.2.2.293 PCIE_CORE_ATU_WRAPPER_OB_10_AXI_ADDR0 Register
            294. 14.9.2.2.2.294 PCIE_CORE_ATU_WRAPPER_OB_10_AXI_ADDR1 Register
            295. 14.9.2.2.2.295 PCIE_CORE_ATU_WRAPPER_OB_11_ADDR0 Register
            296. 14.9.2.2.2.296 PCIE_CORE_ATU_WRAPPER_OB_11_ADDR1 Register
            297. 14.9.2.2.2.297 PCIE_CORE_ATU_WRAPPER_OB_11_DESC0 Register
            298. 14.9.2.2.2.298 PCIE_CORE_ATU_WRAPPER_OB_11_DESC1 Register
            299. 14.9.2.2.2.299 PCIE_CORE_ATU_WRAPPER_OB_11_DESC3 Register
            300. 14.9.2.2.2.300 PCIE_CORE_ATU_WRAPPER_OB_11_AXI_ADDR0 Register
            301. 14.9.2.2.2.301 PCIE_CORE_ATU_WRAPPER_OB_11_AXI_ADDR1 Register
            302. 14.9.2.2.2.302 PCIE_CORE_ATU_WRAPPER_OB_12_ADDR0 Register
            303. 14.9.2.2.2.303 PCIE_CORE_ATU_WRAPPER_OB_12_ADDR1 Register
            304. 14.9.2.2.2.304 PCIE_CORE_ATU_WRAPPER_OB_12_DESC0 Register
            305. 14.9.2.2.2.305 PCIE_CORE_ATU_WRAPPER_OB_12_DESC1 Register
            306. 14.9.2.2.2.306 PCIE_CORE_ATU_WRAPPER_OB_12_DESC3 Register
            307. 14.9.2.2.2.307 PCIE_CORE_ATU_WRAPPER_OB_12_AXI_ADDR0 Register
            308. 14.9.2.2.2.308 PCIE_CORE_ATU_WRAPPER_OB_12_AXI_ADDR1 Register
            309. 14.9.2.2.2.309 PCIE_CORE_ATU_WRAPPER_OB_13_ADDR0 Register
            310. 14.9.2.2.2.310 PCIE_CORE_ATU_WRAPPER_OB_13_ADDR1 Register
            311. 14.9.2.2.2.311 PCIE_CORE_ATU_WRAPPER_OB_13_DESC0 Register
            312. 14.9.2.2.2.312 PCIE_CORE_ATU_WRAPPER_OB_13_DESC1 Register
            313. 14.9.2.2.2.313 PCIE_CORE_ATU_WRAPPER_OB_13_DESC3 Register
            314. 14.9.2.2.2.314 PCIE_CORE_ATU_WRAPPER_OB_13_AXI_ADDR0 Register
            315. 14.9.2.2.2.315 PCIE_CORE_ATU_WRAPPER_OB_13_AXI_ADDR1 Register
            316. 14.9.2.2.2.316 PCIE_CORE_ATU_WRAPPER_OB_14_ADDR0 Register
            317. 14.9.2.2.2.317 PCIE_CORE_ATU_WRAPPER_OB_14_ADDR1 Register
            318. 14.9.2.2.2.318 PCIE_CORE_ATU_WRAPPER_OB_14_DESC0 Register
            319. 14.9.2.2.2.319 PCIE_CORE_ATU_WRAPPER_OB_14_DESC1 Register
            320. 14.9.2.2.2.320 PCIE_CORE_ATU_WRAPPER_OB_14_DESC3 Register
            321. 14.9.2.2.2.321 PCIE_CORE_ATU_WRAPPER_OB_14_AXI_ADDR0 Register
            322. 14.9.2.2.2.322 PCIE_CORE_ATU_WRAPPER_OB_14_AXI_ADDR1 Register
            323. 14.9.2.2.2.323 PCIE_CORE_ATU_WRAPPER_OB_15_ADDR0 Register
            324. 14.9.2.2.2.324 PCIE_CORE_ATU_WRAPPER_OB_15_ADDR1 Register
            325. 14.9.2.2.2.325 PCIE_CORE_ATU_WRAPPER_OB_15_DESC0 Register
            326. 14.9.2.2.2.326 PCIE_CORE_ATU_WRAPPER_OB_15_DESC1 Register
            327. 14.9.2.2.2.327 PCIE_CORE_ATU_WRAPPER_OB_15_DESC3 Register
            328. 14.9.2.2.2.328 PCIE_CORE_ATU_WRAPPER_OB_15_AXI_ADDR0 Register
            329. 14.9.2.2.2.329 PCIE_CORE_ATU_WRAPPER_OB_15_AXI_ADDR1 Register
            330. 14.9.2.2.2.330 PCIE_CORE_ATU_WRAPPER_OB_16_ADDR0 Register
            331. 14.9.2.2.2.331 PCIE_CORE_ATU_WRAPPER_OB_16_ADDR1 Register
            332. 14.9.2.2.2.332 PCIE_CORE_ATU_WRAPPER_OB_16_DESC0 Register
            333. 14.9.2.2.2.333 PCIE_CORE_ATU_WRAPPER_OB_16_DESC1 Register
            334. 14.9.2.2.2.334 PCIE_CORE_ATU_WRAPPER_OB_16_DESC3 Register
            335. 14.9.2.2.2.335 PCIE_CORE_ATU_WRAPPER_OB_16_AXI_ADDR0 Register
            336. 14.9.2.2.2.336 PCIE_CORE_ATU_WRAPPER_OB_16_AXI_ADDR1 Register
            337. 14.9.2.2.2.337 PCIE_CORE_ATU_WRAPPER_OB_17_ADDR0 Register
            338. 14.9.2.2.2.338 PCIE_CORE_ATU_WRAPPER_OB_17_ADDR1 Register
            339. 14.9.2.2.2.339 PCIE_CORE_ATU_WRAPPER_OB_17_DESC0 Register
            340. 14.9.2.2.2.340 PCIE_CORE_ATU_WRAPPER_OB_17_DESC1 Register
            341. 14.9.2.2.2.341 PCIE_CORE_ATU_WRAPPER_OB_17_DESC3 Register
            342. 14.9.2.2.2.342 PCIE_CORE_ATU_WRAPPER_OB_17_AXI_ADDR0 Register
            343. 14.9.2.2.2.343 PCIE_CORE_ATU_WRAPPER_OB_17_AXI_ADDR1 Register
            344. 14.9.2.2.2.344 PCIE_CORE_ATU_WRAPPER_OB_18_ADDR0 Register
            345. 14.9.2.2.2.345 PCIE_CORE_ATU_WRAPPER_OB_18_ADDR1 Register
            346. 14.9.2.2.2.346 PCIE_CORE_ATU_WRAPPER_OB_18_DESC0 Register
            347. 14.9.2.2.2.347 PCIE_CORE_ATU_WRAPPER_OB_18_DESC1 Register
            348. 14.9.2.2.2.348 PCIE_CORE_ATU_WRAPPER_OB_18_DESC3 Register
            349. 14.9.2.2.2.349 PCIE_CORE_ATU_WRAPPER_OB_18_AXI_ADDR0 Register
            350. 14.9.2.2.2.350 PCIE_CORE_ATU_WRAPPER_OB_18_AXI_ADDR1 Register
            351. 14.9.2.2.2.351 PCIE_CORE_ATU_WRAPPER_OB_19_ADDR0 Register
            352. 14.9.2.2.2.352 PCIE_CORE_ATU_WRAPPER_OB_19_ADDR1 Register
            353. 14.9.2.2.2.353 PCIE_CORE_ATU_WRAPPER_OB_19_DESC0 Register
            354. 14.9.2.2.2.354 PCIE_CORE_ATU_WRAPPER_OB_19_DESC1 Register
            355. 14.9.2.2.2.355 PCIE_CORE_ATU_WRAPPER_OB_19_DESC3 Register
            356. 14.9.2.2.2.356 PCIE_CORE_ATU_WRAPPER_OB_19_AXI_ADDR0 Register
            357. 14.9.2.2.2.357 PCIE_CORE_ATU_WRAPPER_OB_19_AXI_ADDR1 Register
            358. 14.9.2.2.2.358 PCIE_CORE_ATU_WRAPPER_OB_20_ADDR0 Register
            359. 14.9.2.2.2.359 PCIE_CORE_ATU_WRAPPER_OB_20_ADDR1 Register
            360. 14.9.2.2.2.360 PCIE_CORE_ATU_WRAPPER_OB_20_DESC0 Register
            361. 14.9.2.2.2.361 PCIE_CORE_ATU_WRAPPER_OB_20_DESC1 Register
            362. 14.9.2.2.2.362 PCIE_CORE_ATU_WRAPPER_OB_20_DESC3 Register
            363. 14.9.2.2.2.363 PCIE_CORE_ATU_WRAPPER_OB_20_AXI_ADDR0 Register
            364. 14.9.2.2.2.364 PCIE_CORE_ATU_WRAPPER_OB_20_AXI_ADDR1 Register
            365. 14.9.2.2.2.365 PCIE_CORE_ATU_WRAPPER_OB_21_ADDR0 Register
            366. 14.9.2.2.2.366 PCIE_CORE_ATU_WRAPPER_OB_21_ADDR1 Register
            367. 14.9.2.2.2.367 PCIE_CORE_ATU_WRAPPER_OB_21_DESC0 Register
            368. 14.9.2.2.2.368 PCIE_CORE_ATU_WRAPPER_OB_21_DESC1 Register
            369. 14.9.2.2.2.369 PCIE_CORE_ATU_WRAPPER_OB_21_DESC3 Register
            370. 14.9.2.2.2.370 PCIE_CORE_ATU_WRAPPER_OB_21_AXI_ADDR0 Register
            371. 14.9.2.2.2.371 PCIE_CORE_ATU_WRAPPER_OB_21_AXI_ADDR1 Register
            372. 14.9.2.2.2.372 PCIE_CORE_ATU_WRAPPER_OB_22_ADDR0 Register
            373. 14.9.2.2.2.373 PCIE_CORE_ATU_WRAPPER_OB_22_ADDR1 Register
            374. 14.9.2.2.2.374 PCIE_CORE_ATU_WRAPPER_OB_22_DESC0 Register
            375. 14.9.2.2.2.375 PCIE_CORE_ATU_WRAPPER_OB_22_DESC1 Register
            376. 14.9.2.2.2.376 PCIE_CORE_ATU_WRAPPER_OB_22_DESC3 Register
            377. 14.9.2.2.2.377 PCIE_CORE_ATU_WRAPPER_OB_22_AXI_ADDR0 Register
            378. 14.9.2.2.2.378 PCIE_CORE_ATU_WRAPPER_OB_22_AXI_ADDR1 Register
            379. 14.9.2.2.2.379 PCIE_CORE_ATU_WRAPPER_OB_23_ADDR0 Register
            380. 14.9.2.2.2.380 PCIE_CORE_ATU_WRAPPER_OB_23_ADDR1 Register
            381. 14.9.2.2.2.381 PCIE_CORE_ATU_WRAPPER_OB_23_DESC0 Register
            382. 14.9.2.2.2.382 PCIE_CORE_ATU_WRAPPER_OB_23_DESC1 Register
            383. 14.9.2.2.2.383 PCIE_CORE_ATU_WRAPPER_OB_23_DESC3 Register
            384. 14.9.2.2.2.384 PCIE_CORE_ATU_WRAPPER_OB_23_AXI_ADDR0 Register
            385. 14.9.2.2.2.385 PCIE_CORE_ATU_WRAPPER_OB_23_AXI_ADDR1 Register
            386. 14.9.2.2.2.386 PCIE_CORE_ATU_WRAPPER_OB_24_ADDR0 Register
            387. 14.9.2.2.2.387 PCIE_CORE_ATU_WRAPPER_OB_24_ADDR1 Register
            388. 14.9.2.2.2.388 PCIE_CORE_ATU_WRAPPER_OB_24_DESC0 Register
            389. 14.9.2.2.2.389 PCIE_CORE_ATU_WRAPPER_OB_24_DESC1 Register
            390. 14.9.2.2.2.390 PCIE_CORE_ATU_WRAPPER_OB_24_DESC3 Register
            391. 14.9.2.2.2.391 PCIE_CORE_ATU_WRAPPER_OB_24_AXI_ADDR0 Register
            392. 14.9.2.2.2.392 PCIE_CORE_ATU_WRAPPER_OB_24_AXI_ADDR1 Register
            393. 14.9.2.2.2.393 PCIE_CORE_ATU_WRAPPER_OB_25_ADDR0 Register
            394. 14.9.2.2.2.394 PCIE_CORE_ATU_WRAPPER_OB_25_ADDR1 Register
            395. 14.9.2.2.2.395 PCIE_CORE_ATU_WRAPPER_OB_25_DESC0 Register
            396. 14.9.2.2.2.396 PCIE_CORE_ATU_WRAPPER_OB_25_DESC1 Register
            397. 14.9.2.2.2.397 PCIE_CORE_ATU_WRAPPER_OB_25_DESC3 Register
            398. 14.9.2.2.2.398 PCIE_CORE_ATU_WRAPPER_OB_25_AXI_ADDR0 Register
            399. 14.9.2.2.2.399 PCIE_CORE_ATU_WRAPPER_OB_25_AXI_ADDR1 Register
            400. 14.9.2.2.2.400 PCIE_CORE_ATU_WRAPPER_OB_26_ADDR0 Register
            401. 14.9.2.2.2.401 PCIE_CORE_ATU_WRAPPER_OB_26_ADDR1 Register
            402. 14.9.2.2.2.402 PCIE_CORE_ATU_WRAPPER_OB_26_DESC0 Register
            403. 14.9.2.2.2.403 PCIE_CORE_ATU_WRAPPER_OB_26_DESC1 Register
            404. 14.9.2.2.2.404 PCIE_CORE_ATU_WRAPPER_OB_26_DESC3 Register
            405. 14.9.2.2.2.405 PCIE_CORE_ATU_WRAPPER_OB_26_AXI_ADDR0 Register
            406. 14.9.2.2.2.406 PCIE_CORE_ATU_WRAPPER_OB_26_AXI_ADDR1 Register
            407. 14.9.2.2.2.407 PCIE_CORE_ATU_WRAPPER_OB_27_ADDR0 Register
            408. 14.9.2.2.2.408 PCIE_CORE_ATU_WRAPPER_OB_27_ADDR1 Register
            409. 14.9.2.2.2.409 PCIE_CORE_ATU_WRAPPER_OB_27_DESC0 Register
            410. 14.9.2.2.2.410 PCIE_CORE_ATU_WRAPPER_OB_27_DESC1 Register
            411. 14.9.2.2.2.411 PCIE_CORE_ATU_WRAPPER_OB_27_DESC3 Register
            412. 14.9.2.2.2.412 PCIE_CORE_ATU_WRAPPER_OB_27_AXI_ADDR0 Register
            413. 14.9.2.2.2.413 PCIE_CORE_ATU_WRAPPER_OB_27_AXI_ADDR1 Register
            414. 14.9.2.2.2.414 PCIE_CORE_ATU_WRAPPER_OB_28_ADDR0 Register
            415. 14.9.2.2.2.415 PCIE_CORE_ATU_WRAPPER_OB_28_ADDR1 Register
            416. 14.9.2.2.2.416 PCIE_CORE_ATU_WRAPPER_OB_28_DESC0 Register
            417. 14.9.2.2.2.417 PCIE_CORE_ATU_WRAPPER_OB_28_DESC1 Register
            418. 14.9.2.2.2.418 PCIE_CORE_ATU_WRAPPER_OB_28_DESC3 Register
            419. 14.9.2.2.2.419 PCIE_CORE_ATU_WRAPPER_OB_28_AXI_ADDR0 Register
            420. 14.9.2.2.2.420 PCIE_CORE_ATU_WRAPPER_OB_28_AXI_ADDR1 Register
            421. 14.9.2.2.2.421 PCIE_CORE_ATU_WRAPPER_OB_29_ADDR0 Register
            422. 14.9.2.2.2.422 PCIE_CORE_ATU_WRAPPER_OB_29_ADDR1 Register
            423. 14.9.2.2.2.423 PCIE_CORE_ATU_WRAPPER_OB_29_DESC0 Register
            424. 14.9.2.2.2.424 PCIE_CORE_ATU_WRAPPER_OB_29_DESC1 Register
            425. 14.9.2.2.2.425 PCIE_CORE_ATU_WRAPPER_OB_29_DESC3 Register
            426. 14.9.2.2.2.426 PCIE_CORE_ATU_WRAPPER_OB_29_AXI_ADDR0 Register
            427. 14.9.2.2.2.427 PCIE_CORE_ATU_WRAPPER_OB_29_AXI_ADDR1 Register
            428. 14.9.2.2.2.428 PCIE_CORE_ATU_WRAPPER_OB_30_ADDR0 Register
            429. 14.9.2.2.2.429 PCIE_CORE_ATU_WRAPPER_OB_30_ADDR1 Register
            430. 14.9.2.2.2.430 PCIE_CORE_ATU_WRAPPER_OB_30_DESC0 Register
            431. 14.9.2.2.2.431 PCIE_CORE_ATU_WRAPPER_OB_30_DESC1 Register
            432. 14.9.2.2.2.432 PCIE_CORE_ATU_WRAPPER_OB_30_DESC3 Register
            433. 14.9.2.2.2.433 PCIE_CORE_ATU_WRAPPER_OB_30_AXI_ADDR0 Register
            434. 14.9.2.2.2.434 PCIE_CORE_ATU_WRAPPER_OB_30_AXI_ADDR1 Register
            435. 14.9.2.2.2.435 PCIE_CORE_ATU_WRAPPER_OB_31_ADDR0 Register
            436. 14.9.2.2.2.436 PCIE_CORE_ATU_WRAPPER_OB_31_ADDR1 Register
            437. 14.9.2.2.2.437 PCIE_CORE_ATU_WRAPPER_OB_31_DESC0 Register
            438. 14.9.2.2.2.438 PCIE_CORE_ATU_WRAPPER_OB_31_DESC1 Register
            439. 14.9.2.2.2.439 PCIE_CORE_ATU_WRAPPER_OB_31_DESC3 Register
            440. 14.9.2.2.2.440 PCIE_CORE_ATU_WRAPPER_OB_31_AXI_ADDR0 Register
            441. 14.9.2.2.2.441 PCIE_CORE_ATU_WRAPPER_OB_31_AXI_ADDR1 Register
            442. 14.9.2.2.2.442 PCIE_CORE_ATU_WRAPPER_IB_0_ADDR0 Register
            443. 14.9.2.2.2.443 PCIE_CORE_ATU_WRAPPER_IB_0_ADDR1 Register
            444. 14.9.2.2.2.444 PCIE_CORE_ATU_WRAPPER_IB_1_ADDR0 Register
            445. 14.9.2.2.2.445 PCIE_CORE_ATU_WRAPPER_IB_1_ADDR1 Register
            446. 14.9.2.2.2.446 PCIE_CORE_ATU_WRAPPER_IB_7_ADDR0 Register
            447. 14.9.2.2.2.447 PCIE_CORE_ATU_WRAPPER_IB_7_ADDR1 Register
            448. 14.9.2.2.2.448 PCIE_CORE_ATU_CREDIT_THRESHOLD_C0 Register
            449. 14.9.2.2.2.449 PCIE_CORE_ATU_LINK_DOWN_INDICATOR_BIT_L0 Register
            450. 14.9.2.2.2.450 USER_CFG_REVID Register
            451. 14.9.2.2.2.451 USER_CFG_CMD_STATUS Register
            452. 14.9.2.2.2.452 USER_CFG_RSTCMD Register
            453. 14.9.2.2.2.453 USER_CFG_INITCFG Register
            454. 14.9.2.2.2.454 USER_CFG_PMCMD Register
            455. 14.9.2.2.2.455 USER_CFG_LINKSTATUS Register
            456. 14.9.2.2.2.456 USER_CFG_LEGACY_INTR_SET Register
            457. 14.9.2.2.2.457 USER_CFG_LEGACY_INT_PENDING Register
            458. 14.9.2.2.2.458 USER_CFG_MSI_STAT Register
            459. 14.9.2.2.2.459 USER_CFG_MSI_VECTOR Register
            460. 14.9.2.2.2.460 USER_CFG_MSI_MASK_PF0 Register
            461. 14.9.2.2.2.461 USER_CFG_MSI_PENDING_STATUS_PF0 Register
            462. 14.9.2.2.2.462 USER_CFG_MSIX_STAT Register
            463. 14.9.2.2.2.463 USER_CFG_MSIX_MASK Register
            464. 14.9.2.2.2.464 USER_CFG_FLR_DONE Register
            465. 14.9.2.2.2.465 USER_CFG_PTM_CFG Register
            466. 14.9.2.2.2.466 USER_CFG_PTM_TIMER_LOW Register
            467. 14.9.2.2.2.467 USER_CFG_PTM_TIMER_HIGH Register
            468. 14.9.2.2.2.468 USER_CFG_EOI_VECTOR Register
            469. 14.9.2.2.2.469 VMAP_OB_VIRTID_MATCH Register
            470. 14.9.2.2.2.470 VMAP_EXT_DESC_j Register
            471. 14.9.2.2.2.471 INTD_CFG_REVISION Register
            472. 14.9.2.2.2.472 INTD_CFG_ENABLE_REG_SYS_0 Register
            473. 14.9.2.2.2.473 INTD_CFG_ENABLE_REG_SYS_1 Register
            474. 14.9.2.2.2.474 INTD_CFG_ENABLE_REG_SYS_2 Register
            475. 14.9.2.2.2.475 INTD_CFG_ENABLE_CLR_REG_SYS_0 Register
            476. 14.9.2.2.2.476 INTD_CFG_ENABLE_CLR_REG_SYS_1 Register
            477. 14.9.2.2.2.477 INTD_CFG_ENABLE_CLR_REG_SYS_2 Register
            478. 14.9.2.2.2.478 INTD_CFG_STATUS_REG_SYS_0 Register
            479. 14.9.2.2.2.479 INTD_CFG_STATUS_REG_SYS_1 Register
            480. 14.9.2.2.2.480 INTD_CFG_STATUS_REG_SYS_2 Register
            481. 14.9.2.2.2.481 INTD_CFG_STATUS_CLR_REG_SYS_2 Register
            482. 14.9.2.2.2.482 INTD_CFG_INTR_VECTOR_REG_SYS Register
            483. 14.9.2.2.2.483 CPTS_IDVER_REG Register
            484. 14.9.2.2.2.484 CPTS_CONTROL_REG Register
            485. 14.9.2.2.2.485 CPTS_RFTCLK_SEL_REG Register
            486. 14.9.2.2.2.486 CPTS_TS_PUSH_REG Register
            487. 14.9.2.2.2.487 CPTS_TS_LOAD_VAL_REG Register
            488. 14.9.2.2.2.488 CPTS_TS_LOAD_EN_REG Register
            489. 14.9.2.2.2.489 CPTS_TS_COMP_VAL_REG Register
            490. 14.9.2.2.2.490 CPTS_TS_COMP_LEN_REG Register
            491. 14.9.2.2.2.491 CPTS_INTSTAT_RAW_REG Register
            492. 14.9.2.2.2.492 CPTS_INTSTAT_MASKED_REG Register
            493. 14.9.2.2.2.493 CPTS_INT_ENABLE_REG Register
            494. 14.9.2.2.2.494 CPTS_TS_COMP_NUDGE_REG Register
            495. 14.9.2.2.2.495 CPTS_EVENT_POP_REG Register
            496. 14.9.2.2.2.496 CPTS_EVENT_0_REG Register
            497. 14.9.2.2.2.497 CPTS_EVENT_1_REG Register
            498. 14.9.2.2.2.498 CPTS_EVENT_2_REG Register
            499. 14.9.2.2.2.499 CPTS_EVENT_3_REG Register
            500. 14.9.2.2.2.500 CPTS_TS_LOAD_HIGH_VAL_REG Register
            501. 14.9.2.2.2.501 CPTS_TS_COMP_HIGH_VAL_REG Register
            502. 14.9.2.2.2.502 CPTS_TS_ADD_VAL_REG Register
            503. 14.9.2.2.2.503 CPTS_TS_PPM_LOW_VAL_REG Register
            504. 14.9.2.2.2.504 CPTS_TS_PPM_HIGH_VAL_REG Register
            505. 14.9.2.2.2.505 CPTS_TS_NUDGE_VAL_REG Register
            506. 14.9.2.2.2.506 CPTS_TS_CONFIG Register
            507. 14.9.2.2.2.507 CPTS_TS_GENF_COMP_LOW_REG Register
            508. 14.9.2.2.2.508 CPTS_TS_GENF_COMP_HIGH_REG Register
            509. 14.9.2.2.2.509 CPTS_TS_GENF_CONTROL_REG Register
            510. 14.9.2.2.2.510 CPTS_TS_GENF_LENGTH_REG Register
            511. 14.9.2.2.2.511 CPTS_TS_GENF_PPM_LOW_REG Register
            512. 14.9.2.2.2.512 CPTS_TS_GENF_PPM_HIGH_REG Register
            513. 14.9.2.2.2.513 CPTS_TS_GENF_NUDGE_REG Register
            514. 14.9.2.2.2.514 CPTS_TS_ESTF_COMP_LOW_REG Register
            515. 14.9.2.2.2.515 CPTS_TS_ESTF_COMP_HIGH_REG Register
            516. 14.9.2.2.2.516 CPTS_TS_ESTF_CONTROL_REG Register
            517. 14.9.2.2.2.517 CPTS_TS_ESTF_LENGTH_REG Register
            518. 14.9.2.2.2.518 CPTS_TS_ESTF_PPM_LOW_REG Register
            519. 14.9.2.2.2.519 CPTS_TS_ESTF_PPM_HIGH_REG Register
            520. 14.9.2.2.2.520 CPTS_TS_ESTF_NUDGE_REG Register
            521. 14.9.2.2.2.521 PCIE_DAT0_PCIE_DATA_MEM_j Register
            522. 14.9.2.2.2.522 PCIE_DAT1_PCIE_DATA_MEM_j Register
        3. 14.9.2.3 USB
          1. 14.9.2.3.1 USB Summaries
            1.         9054
            2.         9055
            3.         9056
          2. 14.9.2.3.2 USB Registers
            1. 14.9.2.3.2.1  ECC_AGGR_REV Register
            2. 14.9.2.3.2.2  ECC_AGGR_VECTOR Register
            3. 14.9.2.3.2.3  ECC_AGGR_STAT Register
            4. 14.9.2.3.2.4  ECC_AGGR_RESERVED_SVBUS_j Register
            5. 14.9.2.3.2.5  ECC_AGGR_SEC_EOI_REG Register
            6. 14.9.2.3.2.6  ECC_AGGR_SEC_STATUS_REG0 Register
            7. 14.9.2.3.2.7  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            8. 14.9.2.3.2.8  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            9. 14.9.2.3.2.9  ECC_AGGR_DED_EOI_REG Register
            10. 14.9.2.3.2.10 ECC_AGGR_DED_STATUS_REG0 Register
            11. 14.9.2.3.2.11 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            12. 14.9.2.3.2.12 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            13. 14.9.2.3.2.13 ECC_AGGR_AGGR_ENABLE_SET Register
            14. 14.9.2.3.2.14 ECC_AGGR_AGGR_ENABLE_CLR Register
            15. 14.9.2.3.2.15 ECC_AGGR_AGGR_STATUS_SET Register
            16. 14.9.2.3.2.16 ECC_AGGR_AGGR_STATUS_CLR Register
            17. 14.9.2.3.2.17 USB3P0SS_CMN_PID Register
            18. 14.9.2.3.2.18 USB3P0SS_CMN_USB3P0SS_W1 Register
            19. 14.9.2.3.2.19 USB3P0SS_CMN_STATIC_CONFIG Register
            20. 14.9.2.3.2.20 USB3P0SS_CMN_PHY_TEST Register
            21. 14.9.2.3.2.21 USB3P0SS_CMN_USB3P0SS_DEBUG_CTRL Register
            22. 14.9.2.3.2.22 USB3P0SS_CMN_USB3P0SS_DEBUG_INFO Register
            23. 14.9.2.3.2.23 USB3P0SS_CMN_USB3P0SS_DEBUG_LINK_STATE Register
            24. 14.9.2.3.2.24 USB3P0SS_CMN_USB3P0SS_DEVICE_CTRL Register
            25. 14.9.2.3.2.25 USB3P0SS_ERR_INJ_PID Register
            26. 14.9.2.3.2.26 USB3P0SS_ERR_INJ_INFO Register
            27. 14.9.2.3.2.27 USB3P0SS_ERR_INJ_SFT_RST Register
            28. 14.9.2.3.2.28 USB3P0SS_ERR_INJ_BIT1 Register
            29. 14.9.2.3.2.29 USB3P0SS_ERR_INJ_BIT2 Register
            30. 14.9.2.3.2.30 USB3P0SS_ERR_INJ_TRGT Register
            31. 14.9.2.3.2.31 USB3P0SS_ERR_INJ_CTRL Register
            32. 14.9.2.3.2.32 USB3P0SS_ERR_INJ_STATUS Register
      3. 14.9.3 Memory Interfaces Registers
        1. 14.9.3.1 FSS
          1. 14.9.3.1.1 FSS Summaries
            1.         9093
          2. 14.9.3.1.2 FSS Registers
            1. 14.9.3.1.2.1 FSS_GENREGS_REVISION Register
        2. 14.9.3.2 FSS_FSAS_0
          1. 14.9.3.2.1 FSS_FSAS_0 Summaries
            1.         9098
            2.         9099
            3.         9100
            4.         9101
            5.         9102
          2. 14.9.3.2.2 FSS_FSAS_0 Registers
            1. 14.9.3.2.2.1   FSS_FSAS_GENREGS_REVISION Register
            2. 14.9.3.2.2.2   FSS_FSAS_GENREGS_SYSCONFIG Register
            3. 14.9.3.2.2.3   FSS_FSAS_GENREGS_FRAG_ADR Register
            4. 14.9.3.2.2.4   FSS_FSAS_GENREGS_FRAG_CTL Register
            5. 14.9.3.2.2.5   FSS_FSAS_GENREGS_IRQ_EOI Register
            6. 14.9.3.2.2.6   FSS_FSAS_GENREGS_IRQ_STATUS_RAW Register
            7. 14.9.3.2.2.7   FSS_FSAS_GENREGS_IRQ_STATUS Register
            8. 14.9.3.2.2.8   FSS_FSAS_GENREGS_IRQ_ENABLE_SET Register
            9. 14.9.3.2.2.9   FSS_FSAS_GENREGS_IRQ_ENABLE_CLR Register
            10. 14.9.3.2.2.10  FSS_FSAS_GENREGS_ECC_REGCTRL_ECC_RGSTRT_j Register
            11. 14.9.3.2.2.11  FSS_FSAS_GENREGS_ECC_REGCTRL_ECC_RGSIZ_j Register
            12. 14.9.3.2.2.12  FSS_FSAS_GENREGS_ERR_ECC_BLOCK_ADR Register
            13. 14.9.3.2.2.13  FSS_FSAS_GENREGS_ERR_ECC_TYPE Register
            14. 14.9.3.2.2.14  FSS_FSAS_GENREGS_ERR_WRT_TYPE Register
            15. 14.9.3.2.2.15  FSS_FSAS_OTFA_REGS_REVID Register
            16. 14.9.3.2.2.16  FSS_FSAS_OTFA_REGS_SCFG Register
            17. 14.9.3.2.2.17  FSS_FSAS_OTFA_REGS_ISR Register
            18. 14.9.3.2.2.18  FSS_FSAS_OTFA_REGS_IS Register
            19. 14.9.3.2.2.19  FSS_FSAS_OTFA_REGS_IES Register
            20. 14.9.3.2.2.20  FSS_FSAS_OTFA_REGS_IEC Register
            21. 14.9.3.2.2.21  FSS_FSAS_OTFA_REGS_CCFG Register
            22. 14.9.3.2.2.22  FSS_FSAS_OTFA_REGS_CSTATUS Register
            23. 14.9.3.2.2.23  FSS_FSAS_OTFA_REGS_RGCFG0 Register
            24. 14.9.3.2.2.24  FSS_FSAS_OTFA_REGS_RGMACST0 Register
            25. 14.9.3.2.2.25  FSS_FSAS_OTFA_REGS_RGST0 Register
            26. 14.9.3.2.2.26  FSS_FSAS_OTFA_REGS_RGSI0 Register
            27. 14.9.3.2.2.27  FSS_FSAS_OTFA_REGS_RKEYE00 Register
            28. 14.9.3.2.2.28  FSS_FSAS_OTFA_REGS_RKEYE01 Register
            29. 14.9.3.2.2.29  FSS_FSAS_OTFA_REGS_RKEYE02 Register
            30. 14.9.3.2.2.30  FSS_FSAS_OTFA_REGS_RKEYE03 Register
            31. 14.9.3.2.2.31  FSS_FSAS_OTFA_REGS_RKEYE04 Register
            32. 14.9.3.2.2.32  FSS_FSAS_OTFA_REGS_RKEYE05 Register
            33. 14.9.3.2.2.33  FSS_FSAS_OTFA_REGS_RKEYE06 Register
            34. 14.9.3.2.2.34  FSS_FSAS_OTFA_REGS_RKEYE07 Register
            35. 14.9.3.2.2.35  FSS_FSAS_OTFA_REGS_RKEYEP00 Register
            36. 14.9.3.2.2.36  FSS_FSAS_OTFA_REGS_RKEYEP01 Register
            37. 14.9.3.2.2.37  FSS_FSAS_OTFA_REGS_RKEYEP02 Register
            38. 14.9.3.2.2.38  FSS_FSAS_OTFA_REGS_RKEYEP03 Register
            39. 14.9.3.2.2.39  FSS_FSAS_OTFA_REGS_RKEYEP04 Register
            40. 14.9.3.2.2.40  FSS_FSAS_OTFA_REGS_RKEYEP05 Register
            41. 14.9.3.2.2.41  FSS_FSAS_OTFA_REGS_RKEYEP06 Register
            42. 14.9.3.2.2.42  FSS_FSAS_OTFA_REGS_RKEYEP07 Register
            43. 14.9.3.2.2.43  FSS_FSAS_OTFA_REGS_RKEYA00 Register
            44. 14.9.3.2.2.44  FSS_FSAS_OTFA_REGS_RKEYA01 Register
            45. 14.9.3.2.2.45  FSS_FSAS_OTFA_REGS_RKEYA02 Register
            46. 14.9.3.2.2.46  FSS_FSAS_OTFA_REGS_RKEYA03 Register
            47. 14.9.3.2.2.47  FSS_FSAS_OTFA_REGS_RKEYAP00 Register
            48. 14.9.3.2.2.48  FSS_FSAS_OTFA_REGS_RKEYAP01 Register
            49. 14.9.3.2.2.49  FSS_FSAS_OTFA_REGS_RKEYAP02 Register
            50. 14.9.3.2.2.50  FSS_FSAS_OTFA_REGS_RKEYAP03 Register
            51. 14.9.3.2.2.51  FSS_FSAS_OTFA_REGS_RIV00 Register
            52. 14.9.3.2.2.52  FSS_FSAS_OTFA_REGS_RIV01 Register
            53. 14.9.3.2.2.53  FSS_FSAS_OTFA_REGS_RIV02 Register
            54. 14.9.3.2.2.54  FSS_FSAS_OTFA_REGS_RIV03 Register
            55. 14.9.3.2.2.55  FSS_FSAS_OTFA_REGS_RGCFG1 Register
            56. 14.9.3.2.2.56  FSS_FSAS_OTFA_REGS_RGMACST1 Register
            57. 14.9.3.2.2.57  FSS_FSAS_OTFA_REGS_RGST1 Register
            58. 14.9.3.2.2.58  FSS_FSAS_OTFA_REGS_RGSI1 Register
            59. 14.9.3.2.2.59  FSS_FSAS_OTFA_REGS_RKEYE10 Register
            60. 14.9.3.2.2.60  FSS_FSAS_OTFA_REGS_RKEYE11 Register
            61. 14.9.3.2.2.61  FSS_FSAS_OTFA_REGS_RKEYE12 Register
            62. 14.9.3.2.2.62  FSS_FSAS_OTFA_REGS_RKEYE13 Register
            63. 14.9.3.2.2.63  FSS_FSAS_OTFA_REGS_RKEYE14 Register
            64. 14.9.3.2.2.64  FSS_FSAS_OTFA_REGS_RKEYE15 Register
            65. 14.9.3.2.2.65  FSS_FSAS_OTFA_REGS_RKEYE16 Register
            66. 14.9.3.2.2.66  FSS_FSAS_OTFA_REGS_RKEYE17 Register
            67. 14.9.3.2.2.67  FSS_FSAS_OTFA_REGS_RKEYEP10 Register
            68. 14.9.3.2.2.68  FSS_FSAS_OTFA_REGS_RKEYEP11 Register
            69. 14.9.3.2.2.69  FSS_FSAS_OTFA_REGS_RKEYEP12 Register
            70. 14.9.3.2.2.70  FSS_FSAS_OTFA_REGS_RKEYEP13 Register
            71. 14.9.3.2.2.71  FSS_FSAS_OTFA_REGS_RKEYEP14 Register
            72. 14.9.3.2.2.72  FSS_FSAS_OTFA_REGS_RKEYEP15 Register
            73. 14.9.3.2.2.73  FSS_FSAS_OTFA_REGS_RKEYEP16 Register
            74. 14.9.3.2.2.74  FSS_FSAS_OTFA_REGS_RKEYEP17 Register
            75. 14.9.3.2.2.75  FSS_FSAS_OTFA_REGS_RKEYA10 Register
            76. 14.9.3.2.2.76  FSS_FSAS_OTFA_REGS_RKEYA11 Register
            77. 14.9.3.2.2.77  FSS_FSAS_OTFA_REGS_RKEYA12 Register
            78. 14.9.3.2.2.78  FSS_FSAS_OTFA_REGS_RKEYA13 Register
            79. 14.9.3.2.2.79  FSS_FSAS_OTFA_REGS_RKEYAP10 Register
            80. 14.9.3.2.2.80  FSS_FSAS_OTFA_REGS_RKEYAP11 Register
            81. 14.9.3.2.2.81  FSS_FSAS_OTFA_REGS_RKEYAP12 Register
            82. 14.9.3.2.2.82  FSS_FSAS_OTFA_REGS_RKEYAP13 Register
            83. 14.9.3.2.2.83  FSS_FSAS_OTFA_REGS_RIV10 Register
            84. 14.9.3.2.2.84  FSS_FSAS_OTFA_REGS_RIV11 Register
            85. 14.9.3.2.2.85  FSS_FSAS_OTFA_REGS_RIV12 Register
            86. 14.9.3.2.2.86  FSS_FSAS_OTFA_REGS_RIV13 Register
            87. 14.9.3.2.2.87  FSS_FSAS_OTFA_REGS_RGCFG2 Register
            88. 14.9.3.2.2.88  FSS_FSAS_OTFA_REGS_RGMACST2 Register
            89. 14.9.3.2.2.89  FSS_FSAS_OTFA_REGS_RGST2 Register
            90. 14.9.3.2.2.90  FSS_FSAS_OTFA_REGS_RGSI2 Register
            91. 14.9.3.2.2.91  FSS_FSAS_OTFA_REGS_RKEYE20 Register
            92. 14.9.3.2.2.92  FSS_FSAS_OTFA_REGS_RKEYE21 Register
            93. 14.9.3.2.2.93  FSS_FSAS_OTFA_REGS_RKEYE22 Register
            94. 14.9.3.2.2.94  FSS_FSAS_OTFA_REGS_RKEYE23 Register
            95. 14.9.3.2.2.95  FSS_FSAS_OTFA_REGS_RKEYE24 Register
            96. 14.9.3.2.2.96  FSS_FSAS_OTFA_REGS_RKEYE25 Register
            97. 14.9.3.2.2.97  FSS_FSAS_OTFA_REGS_RKEYE26 Register
            98. 14.9.3.2.2.98  FSS_FSAS_OTFA_REGS_RKEYE27 Register
            99. 14.9.3.2.2.99  FSS_FSAS_OTFA_REGS_RKEYEP20 Register
            100. 14.9.3.2.2.100 FSS_FSAS_OTFA_REGS_RKEYEP21 Register
            101. 14.9.3.2.2.101 FSS_FSAS_OTFA_REGS_RKEYEP22 Register
            102. 14.9.3.2.2.102 FSS_FSAS_OTFA_REGS_RKEYEP23 Register
            103. 14.9.3.2.2.103 FSS_FSAS_OTFA_REGS_RKEYEP24 Register
            104. 14.9.3.2.2.104 FSS_FSAS_OTFA_REGS_RKEYEP25 Register
            105. 14.9.3.2.2.105 FSS_FSAS_OTFA_REGS_RKEYEP26 Register
            106. 14.9.3.2.2.106 FSS_FSAS_OTFA_REGS_RKEYEP27 Register
            107. 14.9.3.2.2.107 FSS_FSAS_OTFA_REGS_RKEYA20 Register
            108. 14.9.3.2.2.108 FSS_FSAS_OTFA_REGS_RKEYA21 Register
            109. 14.9.3.2.2.109 FSS_FSAS_OTFA_REGS_RKEYA22 Register
            110. 14.9.3.2.2.110 FSS_FSAS_OTFA_REGS_RKEYA23 Register
            111. 14.9.3.2.2.111 FSS_FSAS_OTFA_REGS_RKEYAP20 Register
            112. 14.9.3.2.2.112 FSS_FSAS_OTFA_REGS_RKEYAP21 Register
            113. 14.9.3.2.2.113 FSS_FSAS_OTFA_REGS_RKEYAP22 Register
            114. 14.9.3.2.2.114 FSS_FSAS_OTFA_REGS_RKEYAP23 Register
            115. 14.9.3.2.2.115 FSS_FSAS_OTFA_REGS_RIV20 Register
            116. 14.9.3.2.2.116 FSS_FSAS_OTFA_REGS_RIV21 Register
            117. 14.9.3.2.2.117 FSS_FSAS_OTFA_REGS_RIV22 Register
            118. 14.9.3.2.2.118 FSS_FSAS_OTFA_REGS_RIV23 Register
            119. 14.9.3.2.2.119 FSS_FSAS_OTFA_REGS_RGCFG3 Register
            120. 14.9.3.2.2.120 FSS_FSAS_OTFA_REGS_RGMACST3 Register
            121. 14.9.3.2.2.121 FSS_FSAS_OTFA_REGS_RGST3 Register
            122. 14.9.3.2.2.122 FSS_FSAS_OTFA_REGS_RGSI3 Register
            123. 14.9.3.2.2.123 FSS_FSAS_OTFA_REGS_RKEYE30 Register
            124. 14.9.3.2.2.124 FSS_FSAS_OTFA_REGS_RKEYE31 Register
            125. 14.9.3.2.2.125 FSS_FSAS_OTFA_REGS_RKEYE32 Register
            126. 14.9.3.2.2.126 FSS_FSAS_OTFA_REGS_RKEYE33 Register
            127. 14.9.3.2.2.127 FSS_FSAS_OTFA_REGS_RKEYE34 Register
            128. 14.9.3.2.2.128 FSS_FSAS_OTFA_REGS_RKEYE35 Register
            129. 14.9.3.2.2.129 FSS_FSAS_OTFA_REGS_RKEYE36 Register
            130. 14.9.3.2.2.130 FSS_FSAS_OTFA_REGS_RKEYE37 Register
            131. 14.9.3.2.2.131 FSS_FSAS_OTFA_REGS_RKEYEP30 Register
            132. 14.9.3.2.2.132 FSS_FSAS_OTFA_REGS_RKEYEP31 Register
            133. 14.9.3.2.2.133 FSS_FSAS_OTFA_REGS_RKEYEP32 Register
            134. 14.9.3.2.2.134 FSS_FSAS_OTFA_REGS_RKEYEP33 Register
            135. 14.9.3.2.2.135 FSS_FSAS_OTFA_REGS_RKEYEP34 Register
            136. 14.9.3.2.2.136 FSS_FSAS_OTFA_REGS_RKEYEP35 Register
            137. 14.9.3.2.2.137 FSS_FSAS_OTFA_REGS_RKEYEP36 Register
            138. 14.9.3.2.2.138 FSS_FSAS_OTFA_REGS_RKEYEP37 Register
            139. 14.9.3.2.2.139 FSS_FSAS_OTFA_REGS_RKEYA30 Register
            140. 14.9.3.2.2.140 FSS_FSAS_OTFA_REGS_RKEYA31 Register
            141. 14.9.3.2.2.141 FSS_FSAS_OTFA_REGS_RKEYA32 Register
            142. 14.9.3.2.2.142 FSS_FSAS_OTFA_REGS_RKEYA33 Register
            143. 14.9.3.2.2.143 FSS_FSAS_OTFA_REGS_RKEYAP30 Register
            144. 14.9.3.2.2.144 FSS_FSAS_OTFA_REGS_RKEYAP31 Register
            145. 14.9.3.2.2.145 FSS_FSAS_OTFA_REGS_RKEYAP32 Register
            146. 14.9.3.2.2.146 FSS_FSAS_OTFA_REGS_RKEYAP33 Register
            147. 14.9.3.2.2.147 FSS_FSAS_OTFA_REGS_RIV30 Register
            148. 14.9.3.2.2.148 FSS_FSAS_OTFA_REGS_RIV31 Register
            149. 14.9.3.2.2.149 FSS_FSAS_OTFA_REGS_RIV32 Register
            150. 14.9.3.2.2.150 FSS_FSAS_OTFA_REGS_RIV33 Register
            151. 14.9.3.2.2.151 FSS_FSAS_OTFA_REGS_IRQADDINFO0 Register
            152. 14.9.3.2.2.152 FSS_FSAS_OTFA_REGS_IRQADDINFO1 Register
            153. 14.9.3.2.2.153 FSS_FSAS_OTFA_REGS_MACCACHEINFO Register
            154. 14.9.3.2.2.154 FSS_FSAS_OTFA_REGS_RMWRMCNT Register
            155. 14.9.3.2.2.155 FSS_DAT_REG1_HPB_DATA_MEM_j Register
            156. 14.9.3.2.2.156 FSS_DAT_REG0_HPB_DATA_MEM_j Register
            157. 14.9.3.2.2.157 FSS_DAT_REG3_HPB_DATA_MEM_j Register
        3. 14.9.3.3 FSS_OSPI_0
          1. 14.9.3.3.1 FSS_OSPI_0 Summaries
            1.         9263
            2.         9264
            3.         9265
          2. 14.9.3.3.2 FSS_OSPI_0 Registers
            1. 14.9.3.3.2.1  ECC_AGGR_REV Register
            2. 14.9.3.3.2.2  ECC_AGGR_VECTOR Register
            3. 14.9.3.3.2.3  ECC_AGGR_STAT Register
            4. 14.9.3.3.2.4  ECC_AGGR_RESERVED_SVBUS_j Register
            5. 14.9.3.3.2.5  ECC_AGGR_SEC_EOI_REG Register
            6. 14.9.3.3.2.6  ECC_AGGR_SEC_STATUS_REG0 Register
            7. 14.9.3.3.2.7  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            8. 14.9.3.3.2.8  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            9. 14.9.3.3.2.9  ECC_AGGR_DED_EOI_REG Register
            10. 14.9.3.3.2.10 ECC_AGGR_DED_STATUS_REG0 Register
            11. 14.9.3.3.2.11 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            12. 14.9.3.3.2.12 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            13. 14.9.3.3.2.13 ECC_AGGR_AGGR_ENABLE_SET Register
            14. 14.9.3.3.2.14 ECC_AGGR_AGGR_ENABLE_CLR Register
            15. 14.9.3.3.2.15 ECC_AGGR_AGGR_STATUS_SET Register
            16. 14.9.3.3.2.16 ECC_AGGR_AGGR_STATUS_CLR Register
            17. 14.9.3.3.2.17 OSPI_FLASH_CFG_CONFIG_REG Register
            18. 14.9.3.3.2.18 OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG Register
            19. 14.9.3.3.2.19 OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG Register
            20. 14.9.3.3.2.20 OSPI_FLASH_CFG_DEV_DELAY_REG Register
            21. 14.9.3.3.2.21 OSPI_FLASH_CFG_RD_DATA_CAPTURE_REG Register
            22. 14.9.3.3.2.22 OSPI_FLASH_CFG_DEV_SIZE_CONFIG_REG Register
            23. 14.9.3.3.2.23 OSPI_FLASH_CFG_SRAM_PARTITION_CFG_REG Register
            24. 14.9.3.3.2.24 OSPI_FLASH_CFG_IND_AHB_ADDR_TRIGGER_REG Register
            25. 14.9.3.3.2.25 OSPI_FLASH_CFG_DMA_PERIPH_CONFIG_REG Register
            26. 14.9.3.3.2.26 OSPI_FLASH_CFG_REMAP_ADDR_REG Register
            27. 14.9.3.3.2.27 OSPI_FLASH_CFG_MODE_BIT_CONFIG_REG Register
            28. 14.9.3.3.2.28 OSPI_FLASH_CFG_SRAM_FILL_REG Register
            29. 14.9.3.3.2.29 OSPI_FLASH_CFG_TX_THRESH_REG Register
            30. 14.9.3.3.2.30 OSPI_FLASH_CFG_RX_THRESH_REG Register
            31. 14.9.3.3.2.31 OSPI_FLASH_CFG_WRITE_COMPLETION_CTRL_REG Register
            32. 14.9.3.3.2.32 OSPI_FLASH_CFG_NO_OF_POLLS_BEF_EXP_REG Register
            33. 14.9.3.3.2.33 OSPI_FLASH_CFG_IRQ_STATUS_REG Register
            34. 14.9.3.3.2.34 OSPI_FLASH_CFG_IRQ_MASK_REG Register
            35. 14.9.3.3.2.35 OSPI_FLASH_CFG_LOWER_WR_PROT_REG Register
            36. 14.9.3.3.2.36 OSPI_FLASH_CFG_UPPER_WR_PROT_REG Register
            37. 14.9.3.3.2.37 OSPI_FLASH_CFG_WR_PROT_CTRL_REG Register
            38. 14.9.3.3.2.38 OSPI_FLASH_CFG_INDIRECT_READ_XFER_CTRL_REG Register
            39. 14.9.3.3.2.39 OSPI_FLASH_CFG_INDIRECT_READ_XFER_WATERMARK_REG Register
            40. 14.9.3.3.2.40 OSPI_FLASH_CFG_INDIRECT_READ_XFER_START_REG Register
            41. 14.9.3.3.2.41 OSPI_FLASH_CFG_INDIRECT_READ_XFER_NUM_BYTES_REG Register
            42. 14.9.3.3.2.42 OSPI_FLASH_CFG_INDIRECT_WRITE_XFER_CTRL_REG Register
            43. 14.9.3.3.2.43 OSPI_FLASH_CFG_INDIRECT_WRITE_XFER_WATERMARK_REG Register
            44. 14.9.3.3.2.44 OSPI_FLASH_CFG_INDIRECT_WRITE_XFER_START_REG Register
            45. 14.9.3.3.2.45 OSPI_FLASH_CFG_INDIRECT_WRITE_XFER_NUM_BYTES_REG Register
            46. 14.9.3.3.2.46 OSPI_FLASH_CFG_INDIRECT_TRIGGER_ADDR_RANGE_REG Register
            47. 14.9.3.3.2.47 OSPI_FLASH_CFG_FLASH_COMMAND_CTRL_MEM_REG Register
            48. 14.9.3.3.2.48 OSPI_FLASH_CFG_FLASH_CMD_CTRL_REG Register
            49. 14.9.3.3.2.49 OSPI_FLASH_CFG_FLASH_CMD_ADDR_REG Register
            50. 14.9.3.3.2.50 OSPI_FLASH_CFG_FLASH_RD_DATA_LOWER_REG Register
            51. 14.9.3.3.2.51 OSPI_FLASH_CFG_FLASH_RD_DATA_UPPER_REG Register
            52. 14.9.3.3.2.52 OSPI_FLASH_CFG_FLASH_WR_DATA_LOWER_REG Register
            53. 14.9.3.3.2.53 OSPI_FLASH_CFG_FLASH_WR_DATA_UPPER_REG Register
            54. 14.9.3.3.2.54 OSPI_FLASH_CFG_POLLING_FLASH_STATUS_REG Register
            55. 14.9.3.3.2.55 OSPI_FLASH_CFG_PHY_CONFIGURATION_REG Register
            56. 14.9.3.3.2.56 OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG Register
            57. 14.9.3.3.2.57 OSPI_FLASH_CFG_DLL_OBSERVABLE_LOWER_REG Register
            58. 14.9.3.3.2.58 OSPI_FLASH_CFG_DLL_OBSERVABLE_UPPER_REG Register
            59. 14.9.3.3.2.59 OSPI_FLASH_CFG_OPCODE_EXT_LOWER_REG Register
            60. 14.9.3.3.2.60 OSPI_FLASH_CFG_OPCODE_EXT_UPPER_REG Register
            61. 14.9.3.3.2.61 OSPI_FLASH_CFG_MODULE_ID_REG Register
            62. 14.9.3.3.2.62 OSPI_CFG_PID Register
            63. 14.9.3.3.2.63 OSPI_CFG_CTRL Register
            64. 14.9.3.3.2.64 OSPI_CFG_STAT Register
            65. 14.9.3.3.2.65 OSPI_CFG_EOI Register
        4. 14.9.3.4 GPMC
          1. 14.9.3.4.1 GPMC Summaries
            1.         9334
          2. 14.9.3.4.2 GPMC Registers
            1. 14.9.3.4.2.1  GPMC_REVISION Register
            2. 14.9.3.4.2.2  GPMC_SYSCONFIG Register
            3. 14.9.3.4.2.3  GPMC_SYSSTATUS Register
            4. 14.9.3.4.2.4  GPMC_IRQSTATUS Register
            5. 14.9.3.4.2.5  GPMC_IRQENABLE Register
            6. 14.9.3.4.2.6  GPMC_TIMEOUT_CONTROL Register
            7. 14.9.3.4.2.7  GPMC_ERR_ADDRESS Register
            8. 14.9.3.4.2.8  GPMC_ERR_TYPE Register
            9. 14.9.3.4.2.9  GPMC_CONFIG Register
            10. 14.9.3.4.2.10 GPMC_STATUS Register
            11. 14.9.3.4.2.11 GPMC_PREFETCH_CONFIG1 Register
            12. 14.9.3.4.2.12 GPMC_PREFETCH_CONFIG2 Register
            13. 14.9.3.4.2.13 GPMC_PREFETCH_CONTROL Register
            14. 14.9.3.4.2.14 GPMC_PREFETCH_STATUS Register
            15. 14.9.3.4.2.15 GPMC_ECC_CONFIG Register
            16. 14.9.3.4.2.16 GPMC_ECC_CONTROL Register
            17. 14.9.3.4.2.17 GPMC_ECC_SIZE_CONFIG Register
            18. 14.9.3.4.2.18 GPMC_ECC_RESULT_j Register
            19. 14.9.3.4.2.19 GPMC_BCH_SWDATA Register
            20. 14.9.3.4.2.20 GPMC_CONFIG1_j Register
            21. 14.9.3.4.2.21 GPMC_CONFIG2_j Register
            22. 14.9.3.4.2.22 GPMC_CONFIG3_j Register
            23. 14.9.3.4.2.23 GPMC_CONFIG4_j Register
            24. 14.9.3.4.2.24 GPMC_CONFIG5_j Register
            25. 14.9.3.4.2.25 GPMC_CONFIG6_j Register
            26. 14.9.3.4.2.26 GPMC_CONFIG7_j Register
            27. 14.9.3.4.2.27 GPMC_NAND_COMMAND_j Register
            28. 14.9.3.4.2.28 GPMC_NAND_ADDRESS_j Register
            29. 14.9.3.4.2.29 GPMC_NAND_DATA_j Register
            30. 14.9.3.4.2.30 GPMC_BCH_RESULT_0_j Register
            31. 14.9.3.4.2.31 GPMC_BCH_RESULT_1_j Register
            32. 14.9.3.4.2.32 GPMC_BCH_RESULT_2_j Register
            33. 14.9.3.4.2.33 GPMC_BCH_RESULT_3_j Register
            34. 14.9.3.4.2.34 GPMC_BCH_RESULT_4_j Register
            35. 14.9.3.4.2.35 GPMC_BCH_RESULT_5_j Register
            36. 14.9.3.4.2.36 GPMC_BCH_RESULT_6_j Register
        5. 14.9.3.5 ELM Registers
        6. 14.9.3.6 MMCSD Registers
          1. 14.9.3.6.1 MMCSD0 Subsystem Registers
          2. 14.9.3.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 14.9.3.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 14.9.3.6.4 MMCSD0 Host Controller Registers
          5. 14.9.3.6.5 MMCSD1 Subsystem Registers
          6. 14.9.3.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 14.9.3.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 14.9.3.6.8 MMCSD1 Host Controller Registers
      4. 14.9.4 Industrial and Control Interfaces Registers
        1. 14.9.4.1 MCAN
          1. 14.9.4.1.1 MCAN Summaries
            1.         9385
            2.         9386
            3.         9387
            4.         9388
          2. 14.9.4.1.2 MCAN Registers
            1. 14.9.4.1.2.1  MCAN_PID Register
            2. 14.9.4.1.2.2  MCAN_CTRL Register
            3. 14.9.4.1.2.3  MCAN_STAT Register
            4. 14.9.4.1.2.4  MCAN_ICS Register
            5. 14.9.4.1.2.5  MCAN_IRS Register
            6. 14.9.4.1.2.6  MCAN_IECS Register
            7. 14.9.4.1.2.7  MCAN_IE Register
            8. 14.9.4.1.2.8  MCAN_IES Register
            9. 14.9.4.1.2.9  MCAN_EOI Register
            10. 14.9.4.1.2.10 MCAN_EXT_TS_PRESCALER Register
            11. 14.9.4.1.2.11 MCAN_EXT_TS_UNSERVICED_INTR_CNTR Register
            12. 14.9.4.1.2.12 MCAN_CORE_CREL Register
            13. 14.9.4.1.2.13 MCAN_CORE_ENDN Register
            14. 14.9.4.1.2.14 MCAN_CORE_CUST Register
            15. 14.9.4.1.2.15 MCAN_CORE_DBTP Register
            16. 14.9.4.1.2.16 MCAN_CORE_TEST Register
            17. 14.9.4.1.2.17 MCAN_CORE_RWD Register
            18. 14.9.4.1.2.18 MCAN_CORE_CCCR Register
            19. 14.9.4.1.2.19 MCAN_CORE_NBTP Register
            20. 14.9.4.1.2.20 MCAN_CORE_TSCC Register
            21. 14.9.4.1.2.21 MCAN_CORE_TSCV Register
            22. 14.9.4.1.2.22 MCAN_CORE_TOCC Register
            23. 14.9.4.1.2.23 MCAN_CORE_TOCV Register
            24. 14.9.4.1.2.24 MCAN_CORE_RESERVED00 Register
            25. 14.9.4.1.2.25 MCAN_CORE_RESERVED11 Register
            26. 14.9.4.1.2.26 MCAN_CORE_RESERVED22 Register
            27. 14.9.4.1.2.27 MCAN_CORE_RESERVED33 Register
            28. 14.9.4.1.2.28 MCAN_CORE_ECR Register
            29. 14.9.4.1.2.29 MCAN_CORE_PSR Register
            30. 14.9.4.1.2.30 MCAN_CORE_TDCR Register
            31. 14.9.4.1.2.31 MCAN_CORE_RESERVED44 Register
            32. 14.9.4.1.2.32 MCAN_CORE_IR Register
            33. 14.9.4.1.2.33 MCAN_CORE_IE Register
            34. 14.9.4.1.2.34 MCAN_CORE_ILS Register
            35. 14.9.4.1.2.35 MCAN_CORE_ILE Register
            36. 14.9.4.1.2.36 MCAN_CORE_RESERVED55 Register
            37. 14.9.4.1.2.37 MCAN_CORE_RESERVED66 Register
            38. 14.9.4.1.2.38 MCAN_CORE_RESERVED77 Register
            39. 14.9.4.1.2.39 MCAN_CORE_RESERVED88 Register
            40. 14.9.4.1.2.40 MCAN_CORE_RESERVED99 Register
            41. 14.9.4.1.2.41 MCAN_CORE_RESERVED1010 Register
            42. 14.9.4.1.2.42 MCAN_CORE_RESERVED1111 Register
            43. 14.9.4.1.2.43 MCAN_CORE_RESERVED1212 Register
            44. 14.9.4.1.2.44 MCAN_CORE_GFC Register
            45. 14.9.4.1.2.45 MCAN_CORE_SIDFC Register
            46. 14.9.4.1.2.46 MCAN_CORE_XIDFC Register
            47. 14.9.4.1.2.47 MCAN_CORE_RESERVED1313 Register
            48. 14.9.4.1.2.48 MCAN_CORE_XIDAM Register
            49. 14.9.4.1.2.49 MCAN_CORE_HPMS Register
            50. 14.9.4.1.2.50 MCAN_CORE_NDAT1 Register
            51. 14.9.4.1.2.51 MCAN_CORE_NDAT2 Register
            52. 14.9.4.1.2.52 MCAN_CORE_RXF0C Register
            53. 14.9.4.1.2.53 MCAN_CORE_RXF0S Register
            54. 14.9.4.1.2.54 MCAN_CORE_RXF0A Register
            55. 14.9.4.1.2.55 MCAN_CORE_RXBC Register
            56. 14.9.4.1.2.56 MCAN_CORE_RXF1C Register
            57. 14.9.4.1.2.57 MCAN_CORE_RXF1S Register
            58. 14.9.4.1.2.58 MCAN_CORE_RXF1A Register
            59. 14.9.4.1.2.59 MCAN_CORE_RXESC Register
            60. 14.9.4.1.2.60 MCAN_CORE_TXBC Register
            61. 14.9.4.1.2.61 MCAN_CORE_TXFQS Register
            62. 14.9.4.1.2.62 MCAN_CORE_TXESC Register
            63. 14.9.4.1.2.63 MCAN_CORE_TXBRP Register
            64. 14.9.4.1.2.64 MCAN_CORE_TXBAR Register
            65. 14.9.4.1.2.65 MCAN_CORE_TXBCR Register
            66. 14.9.4.1.2.66 MCAN_CORE_TXBTO Register
            67. 14.9.4.1.2.67 MCAN_CORE_TXBCF Register
            68. 14.9.4.1.2.68 MCAN_CORE_TXBTIE Register
            69. 14.9.4.1.2.69 MCAN_CORE_TXBCIE Register
            70. 14.9.4.1.2.70 MCAN_CORE_RESERVED1414 Register
            71. 14.9.4.1.2.71 MCAN_CORE_RESERVED1515 Register
            72. 14.9.4.1.2.72 MCAN_CORE_TXEFC Register
            73. 14.9.4.1.2.73 MCAN_CORE_TXEFS Register
            74. 14.9.4.1.2.74 MCAN_CORE_TXEFA Register
            75. 14.9.4.1.2.75 MCAN_CORE_RESERVED1616 Register
            76. 14.9.4.1.2.76 MCAN_CORE_RESERVUPPER256_j Register
            77. 14.9.4.1.2.77 MCAN_MSGMEM_WRAP_MSGMEM_VBP_RAM_RAM_REG_j Register
            78. 14.9.4.1.2.78 ECC_AGGR_REV Register
            79. 14.9.4.1.2.79 ECC_AGGR_VECTOR Register
            80. 14.9.4.1.2.80 ECC_AGGR_STAT Register
            81. 14.9.4.1.2.81 ECC_AGGR_RESERVED_SVBUS_j Register
            82. 14.9.4.1.2.82 ECC_AGGR_SEC_EOI_REG Register
            83. 14.9.4.1.2.83 ECC_AGGR_SEC_STATUS_REG0 Register
            84. 14.9.4.1.2.84 ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            85. 14.9.4.1.2.85 ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            86. 14.9.4.1.2.86 ECC_AGGR_DED_EOI_REG Register
            87. 14.9.4.1.2.87 ECC_AGGR_DED_STATUS_REG0 Register
            88. 14.9.4.1.2.88 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            89. 14.9.4.1.2.89 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            90. 14.9.4.1.2.90 ECC_AGGR_AGGR_ENABLE_SET Register
            91. 14.9.4.1.2.91 ECC_AGGR_AGGR_ENABLE_CLR Register
            92. 14.9.4.1.2.92 ECC_AGGR_AGGR_STATUS_SET Register
            93. 14.9.4.1.2.93 ECC_AGGR_AGGR_STATUS_CLR Register
        2. 14.9.4.2 ECAP
          1. 14.9.4.2.1 ECAP Summaries
            1.         9485
          2. 14.9.4.2.2 ECAP Registers
            1. 14.9.4.2.2.1  ECAP_TSCNT Register
            2. 14.9.4.2.2.2  ECAP_CNTPHS Register
            3. 14.9.4.2.2.3  ECAP_CAP1 Register
            4. 14.9.4.2.2.4  ECAP_CAP2 Register
            5. 14.9.4.2.2.5  ECAP_CAP3 Register
            6. 14.9.4.2.2.6  ECAP_CAP4 Register
            7. 14.9.4.2.2.7  ECAP_ECCTL Register
            8. 14.9.4.2.2.8  ECAP_ECINT_EN_FLG Register
            9. 14.9.4.2.2.9  ECAP_ECINT_CLR_FRC Register
            10. 14.9.4.2.2.10 ECAP_PID Register
        3. 14.9.4.3 EPWM
          1. 14.9.4.3.1 EPWM Summaries
            1.         9499
          2. 14.9.4.3.2 EPWM Registers
            1. 14.9.4.3.2.1  EPWM_TBCTL Register
            2. 14.9.4.3.2.2  EPWM_TBSTS Register
            3. 14.9.4.3.2.3  EPWM_TBPHSHR Register
            4. 14.9.4.3.2.4  EPWM_TBPHS Register
            5. 14.9.4.3.2.5  EPWM_TBCNT Register
            6. 14.9.4.3.2.6  EPWM_TBPRD Register
            7. 14.9.4.3.2.7  EPWM_CMPCTL Register
            8. 14.9.4.3.2.8  EPWM_CMPAHR Register
            9. 14.9.4.3.2.9  EPWM_CMPA Register
            10. 14.9.4.3.2.10 EPWM_CMPB Register
            11. 14.9.4.3.2.11 EPWM_AQCTLA Register
            12. 14.9.4.3.2.12 EPWM_AQCTLB Register
            13. 14.9.4.3.2.13 EPWM_AQSFRC Register
            14. 14.9.4.3.2.14 EPWM_AQCSFRC Register
            15. 14.9.4.3.2.15 EPWM_DBCTL Register
            16. 14.9.4.3.2.16 EPWM_DBRED Register
            17. 14.9.4.3.2.17 EPWM_DBFED Register
            18. 14.9.4.3.2.18 EPWM_TZSEL Register
            19. 14.9.4.3.2.19 EPWM_TZCTL Register
            20. 14.9.4.3.2.20 EPWM_TZEINT Register
            21. 14.9.4.3.2.21 EPWM_TZFLG Register
            22. 14.9.4.3.2.22 EPWM_TZCLR Register
            23. 14.9.4.3.2.23 EPWM_TZFRC Register
            24. 14.9.4.3.2.24 EPWM_ETSEL Register
            25. 14.9.4.3.2.25 EPWM_ETPS Register
            26. 14.9.4.3.2.26 EPWM_ETFLG Register
            27. 14.9.4.3.2.27 EPWM_ETCLR Register
            28. 14.9.4.3.2.28 EPWM_ETFRC Register
            29. 14.9.4.3.2.29 EPWM_PCCTL Register
            30. 14.9.4.3.2.30 EPWM_PID Register
        4. 14.9.4.4 EQEP
          1. 14.9.4.4.1 EQEP Summaries
            1.         9533
          2. 14.9.4.4.2 EQEP Registers
            1. 14.9.4.4.2.1  EQEP_QPOSCNT Register
            2. 14.9.4.4.2.2  EQEP_QPOSINIT Register
            3. 14.9.4.4.2.3  EQEP_QPOSMAX Register
            4. 14.9.4.4.2.4  EQEP_QPOSCMP Register
            5. 14.9.4.4.2.5  EQEP_QPOSILAT Register
            6. 14.9.4.4.2.6  EQEP_QPOSSLAT Register
            7. 14.9.4.4.2.7  EQEP_QPOSLAT Register
            8. 14.9.4.4.2.8  EQEP_QUTMR Register
            9. 14.9.4.4.2.9  EQEP_QUPRD Register
            10. 14.9.4.4.2.10 EQEP_QWDTMR Register
            11. 14.9.4.4.2.11 EQEP_QWDPRD Register
            12. 14.9.4.4.2.12 EQEP_QDECCTL_TYPE2 Register
            13. 14.9.4.4.2.13 EQEP_QEPCTL Register
            14. 14.9.4.4.2.14 EQEP_QCAPCTL Register
            15. 14.9.4.4.2.15 EQEP_QPOSCTL Register
            16. 14.9.4.4.2.16 EQEP_QEINT_TYPE1 Register
            17. 14.9.4.4.2.17 EQEP_QFLG_TYPE1 Register
            18. 14.9.4.4.2.18 EQEP_QCLR_TYPE1 Register
            19. 14.9.4.4.2.19 EQEP_QFRC_TYPE1 Register
            20. 14.9.4.4.2.20 EQEP_QEPSTS_TYPE1 Register
            21. 14.9.4.4.2.21 EQEP_QCTMR Register
            22. 14.9.4.4.2.22 EQEP_QCPRD Register
            23. 14.9.4.4.2.23 EQEP_QCTMRLAT Register
            24. 14.9.4.4.2.24 EQEP_QCPRDLAT Register
            25. 14.9.4.4.2.25 EQEP_RESERVED_1_j Register
            26. 14.9.4.4.2.26 EQEP_PID Register
            27. 14.9.4.4.2.27 EQEP_REV_TYPE2 Register
            28. 14.9.4.4.2.28 EQEP_QEPSTROBESEL Register
            29. 14.9.4.4.2.29 EQEP_QMACTRL Register
            30. 14.9.4.4.2.30 EQEP_QEPSRCSEL Register
            31. 14.9.4.4.2.31 EQEP_RESERVED_2_j Register
        5. 14.9.4.5 FSITX
          1. 14.9.4.5.1 FSITX Summaries
            1.         9568
          2. 14.9.4.5.2 FSITX Registers
            1. 14.9.4.5.2.1  FSI_TX_CFG_TX_MASTER_CTRL Register
            2. 14.9.4.5.2.2  FSI_TX_CFG_RESERVED_1 Register
            3. 14.9.4.5.2.3  FSI_TX_CFG_TX_CLK_CTRL Register
            4. 14.9.4.5.2.4  FSI_TX_CFG_RESERVED_2 Register
            5. 14.9.4.5.2.5  FSI_TX_CFG_TX_OPER_CTRL_LO_ALT1_ Register
            6. 14.9.4.5.2.6  FSI_TX_CFG_TX_OPER_CTRL_HI_ALT1_ Register
            7. 14.9.4.5.2.7  FSI_TX_CFG_TX_FRAME_CTRL Register
            8. 14.9.4.5.2.8  FSI_TX_CFG_TX_FRAME_TAG_UDATA Register
            9. 14.9.4.5.2.9  FSI_TX_CFG_TX_BUF_PTR_LOAD Register
            10. 14.9.4.5.2.10 FSI_TX_CFG_TX_BUF_PTR_STS Register
            11. 14.9.4.5.2.11 FSI_TX_CFG_TX_PING_CTRL_ALT1_ Register
            12. 14.9.4.5.2.12 FSI_TX_CFG_TX_PING_TAG Register
            13. 14.9.4.5.2.13 FSI_TX_CFG_TX_PING_TO_REF Register
            14. 14.9.4.5.2.14 FSI_TX_CFG_TX_PING_TO_CNT Register
            15. 14.9.4.5.2.15 FSI_TX_CFG_TX_INT_CTRL Register
            16. 14.9.4.5.2.16 FSI_TX_CFG_TX_DMA_CTRL Register
            17. 14.9.4.5.2.17 FSI_TX_CFG_TX_LOCK_CTRL Register
            18. 14.9.4.5.2.18 FSI_TX_CFG_RESERVED_3 Register
            19. 14.9.4.5.2.19 FSI_TX_CFG_TX_EVT_STS Register
            20. 14.9.4.5.2.20 FSI_TX_CFG_RESERVED_4 Register
            21. 14.9.4.5.2.21 FSI_TX_CFG_TX_EVT_CLR Register
            22. 14.9.4.5.2.22 FSI_TX_CFG_TX_EVT_FRC Register
            23. 14.9.4.5.2.23 FSI_TX_CFG_TX_USER_CRC Register
            24. 14.9.4.5.2.24 FSI_TX_CFG_RESERVED_5 Register
            25. 14.9.4.5.2.25 FSI_TX_CFG_RESERVED_6 Register
            26. 14.9.4.5.2.26 FSI_TX_CFG_RESERVED_7 Register
            27. 14.9.4.5.2.27 FSI_TX_CFG_RESERVED_8 Register
            28. 14.9.4.5.2.28 FSI_TX_CFG_TX_ECC_DATA Register
            29. 14.9.4.5.2.29 FSI_TX_CFG_TX_ECC_VAL Register
            30. 14.9.4.5.2.30 FSI_TX_CFG_RESERVED_9_j Register
            31. 14.9.4.5.2.31 FSI_TX_CFG_TX_BUF_BASE_j Register
        6. 14.9.4.6 FSIRX
          1. 14.9.4.6.1 FSIRX Summaries
            1.         9603
          2. 14.9.4.6.2 FSIRX Registers
            1. 14.9.4.6.2.1  FSI_RX_CFG_RX_MASTER_CTRL_ALTB_ Register
            2. 14.9.4.6.2.2  FSI_RX_CFG_RESERVED_1 Register
            3. 14.9.4.6.2.3  FSI_RX_CFG_RESERVED_2 Register
            4. 14.9.4.6.2.4  FSI_RX_CFG_RESERVED_3 Register
            5. 14.9.4.6.2.5  FSI_RX_CFG_RX_OPER_CTRL Register
            6. 14.9.4.6.2.6  FSI_RX_CFG_RESERVED_4 Register
            7. 14.9.4.6.2.7  FSI_RX_CFG_RX_FRAME_INFO Register
            8. 14.9.4.6.2.8  FSI_RX_CFG_RX_FRAME_TAG_UDATA Register
            9. 14.9.4.6.2.9  FSI_RX_CFG_RX_DMA_CTRL Register
            10. 14.9.4.6.2.10 FSI_RX_CFG_RESERVED_5 Register
            11. 14.9.4.6.2.11 FSI_RX_CFG_RX_EVT_STS_ALT1_ Register
            12. 14.9.4.6.2.12 FSI_RX_CFG_RX_CRC_INFO Register
            13. 14.9.4.6.2.13 FSI_RX_CFG_RX_EVT_CLR_ALT1_ Register
            14. 14.9.4.6.2.14 FSI_RX_CFG_RX_EVT_FRC_ALT1_ Register
            15. 14.9.4.6.2.15 FSI_RX_CFG_RX_BUF_PTR_LOAD Register
            16. 14.9.4.6.2.16 FSI_RX_CFG_RX_BUF_PTR_STS Register
            17. 14.9.4.6.2.17 FSI_RX_CFG_RX_FRAME_WD_CTRL Register
            18. 14.9.4.6.2.18 FSI_RX_CFG_RESERVED_6 Register
            19. 14.9.4.6.2.19 FSI_RX_CFG_RX_FRAME_WD_REF Register
            20. 14.9.4.6.2.20 FSI_RX_CFG_RX_FRAME_WD_CNT Register
            21. 14.9.4.6.2.21 FSI_RX_CFG_RX_PING_WD_CTRL Register
            22. 14.9.4.6.2.22 FSI_RX_CFG_RX_PING_TAG Register
            23. 14.9.4.6.2.23 FSI_RX_CFG_RX_PING_WD_REF Register
            24. 14.9.4.6.2.24 FSI_RX_CFG_RX_PING_WD_CNT Register
            25. 14.9.4.6.2.25 FSI_RX_CFG_RX_INT1_CTRL_ALT1_ Register
            26. 14.9.4.6.2.26 FSI_RX_CFG_RX_INT2_CTRL_ALT1_ Register
            27. 14.9.4.6.2.27 FSI_RX_CFG_RX_LOCK_CTRL Register
            28. 14.9.4.6.2.28 FSI_RX_CFG_RESERVED_7 Register
            29. 14.9.4.6.2.29 FSI_RX_CFG_RX_ECC_DATA Register
            30. 14.9.4.6.2.30 FSI_RX_CFG_RX_ECC_VAL Register
            31. 14.9.4.6.2.31 FSI_RX_CFG_RESERVED_8 Register
            32. 14.9.4.6.2.32 FSI_RX_CFG_RX_ECC_SEC_DATA Register
            33. 14.9.4.6.2.33 FSI_RX_CFG_RX_ECC_LOG Register
            34. 14.9.4.6.2.34 FSI_RX_CFG_RESERVED_9 Register
            35. 14.9.4.6.2.35 FSI_RX_CFG_RX_FRAME_TAG_CMP Register
            36. 14.9.4.6.2.36 FSI_RX_CFG_RX_PING_TAG_CMP Register
            37. 14.9.4.6.2.37 FSI_RX_CFG_RESERVED_10_j Register
            38. 14.9.4.6.2.38 FSI_RX_CFG_RX_DLYLINE_CTRL Register
            39. 14.9.4.6.2.39 FSI_RX_CFG_RESERVED_11_j Register
            40. 14.9.4.6.2.40 FSI_RX_CFG_RX_VIS_1 Register
            41. 14.9.4.6.2.41 FSI_RX_CFG_RESERVED_12_j Register
            42. 14.9.4.6.2.42 FSI_RX_CFG_RX_BUF_BASE_j Register
      5. 14.9.5 Timer Modules Registers
        1. 14.9.5.1 GTC
          1. 14.9.5.1.1 GTC Summaries
            1.         9650
            2.         9651
            3.         9652
            4.         9653
          2. 14.9.5.1.2 GTC Registers
            1. 14.9.5.1.2.1  GTC_CFG0_PID Register
            2. 14.9.5.1.2.2  GTC_CFG0_GTC_PID Register
            3. 14.9.5.1.2.3  GTC_CFG0_PUSHEVT Register
            4. 14.9.5.1.2.4  GTC_CFG1_CNTCR Register
            5. 14.9.5.1.2.5  GTC_CFG1_CNTSR Register
            6. 14.9.5.1.2.6  GTC_CFG1_CNTCV_LO Register
            7. 14.9.5.1.2.7  GTC_CFG1_CNTCV_HI Register
            8. 14.9.5.1.2.8  GTC_CFG1_CNTFID0 Register
            9. 14.9.5.1.2.9  GTC_CFG1_CNTFID1 Register
            10. 14.9.5.1.2.10 GTC_CFG2_CNTCVS_LO Register
            11. 14.9.5.1.2.11 GTC_CFG2_CNTCVS_HI Register
            12. 14.9.5.1.2.12 GTC_CFG3_CNTTIDR Register
        2. 14.9.5.2 RTI_CFG1
          1. 14.9.5.2.1 RTI_CFG1 Summaries
            1.         9669
          2. 14.9.5.2.2 RTI_CFG1 Registers
            1. 14.9.5.2.2.1  RTI_RTIGCTRL Register
            2. 14.9.5.2.2.2  RTI_RTITBCTRL Register
            3. 14.9.5.2.2.3  RTI_RTICAPCTRL Register
            4. 14.9.5.2.2.4  RTI_RTICOMPCTRL Register
            5. 14.9.5.2.2.5  RTI_RTIFRC0 Register
            6. 14.9.5.2.2.6  RTI_RTIUC0 Register
            7. 14.9.5.2.2.7  RTI_RTICPUC0 Register
            8. 14.9.5.2.2.8  RTI_RTICAFRC0 Register
            9. 14.9.5.2.2.9  RTI_RTICAUC0 Register
            10. 14.9.5.2.2.10 RTI_RTIFRC1 Register
            11. 14.9.5.2.2.11 RTI_RTIUC1 Register
            12. 14.9.5.2.2.12 RTI_RTICPUC1 Register
            13. 14.9.5.2.2.13 RTI_RTICAFRC1 Register
            14. 14.9.5.2.2.14 RTI_RTICAUC1 Register
            15. 14.9.5.2.2.15 RTI_RTICOMP0 Register
            16. 14.9.5.2.2.16 RTI_RTIUDCP0 Register
            17. 14.9.5.2.2.17 RTI_RTICOMP1 Register
            18. 14.9.5.2.2.18 RTI_RTIUDCP1 Register
            19. 14.9.5.2.2.19 RTI_RTICOMP2 Register
            20. 14.9.5.2.2.20 RTI_RTIUDCP2 Register
            21. 14.9.5.2.2.21 RTI_RTICOMP3 Register
            22. 14.9.5.2.2.22 RTI_RTIUDCP3 Register
            23. 14.9.5.2.2.23 RTI_RTITBLCOMP Register
            24. 14.9.5.2.2.24 RTI_RTITBHCOMP Register
            25. 14.9.5.2.2.25 RTI_RTISETINT Register
            26. 14.9.5.2.2.26 RTI_RTICLEARINT Register
            27. 14.9.5.2.2.27 RTI_RTIINTFLAG Register
            28. 14.9.5.2.2.28 RTI_RTIDWDCTRL Register
            29. 14.9.5.2.2.29 RTI_RTIDWDPRLD Register
            30. 14.9.5.2.2.30 RTI_RTIWDSTATUS Register
            31. 14.9.5.2.2.31 RTI_RTIWDKEY Register
            32. 14.9.5.2.2.32 RTI_RTIDWDCNTR Register
            33. 14.9.5.2.2.33 RTI_RTIDWWDRXNCTRL Register
            34. 14.9.5.2.2.34 RTI_RTIDWWDSIZECTRL Register
            35. 14.9.5.2.2.35 RTI_RTIINTCLRENABLE Register
            36. 14.9.5.2.2.36 RTI_RTICOMP0CLR Register
            37. 14.9.5.2.2.37 RTI_RTICOMP1CLR Register
            38. 14.9.5.2.2.38 RTI_RTICOMP2CLR Register
            39. 14.9.5.2.2.39 RTI_RTICOMP3CLR Register
        3. 14.9.5.3 TIMER
          1. 14.9.5.3.1 TIMER Summaries
            1.         9712
          2. 14.9.5.3.2 TIMER Registers
            1. 14.9.5.3.2.1  DMTIMER1MS_TIDR Register
            2. 14.9.5.3.2.2  DMTIMER1MS_TIOCP_CFG Register
            3. 14.9.5.3.2.3  DMTIMER1MS_IRQ_EOI Register
            4. 14.9.5.3.2.4  DMTIMER1MS_IRQSTATUS_RAW Register
            5. 14.9.5.3.2.5  DMTIMER1MS_IRQSTATUS Register
            6. 14.9.5.3.2.6  DMTIMER1MS_IRQSTATUS_SET Register
            7. 14.9.5.3.2.7  DMTIMER1MS_IRQSTATUS_CLR Register
            8. 14.9.5.3.2.8  DMTIMER1MS_IRQWAKEEN Register
            9. 14.9.5.3.2.9  DMTIMER1MS_TCLR Register
            10. 14.9.5.3.2.10 DMTIMER1MS_TCRR Register
            11. 14.9.5.3.2.11 DMTIMER1MS_TLDR Register
            12. 14.9.5.3.2.12 DMTIMER1MS_TTGR Register
            13. 14.9.5.3.2.13 DMTIMER1MS_TWPS Register
            14. 14.9.5.3.2.14 DMTIMER1MS_TMAR Register
            15. 14.9.5.3.2.15 DMTIMER1MS_TCAR1 Register
            16. 14.9.5.3.2.16 DMTIMER1MS_TSICR Register
            17. 14.9.5.3.2.17 DMTIMER1MS_TCAR2 Register
            18. 14.9.5.3.2.18 DMTIMER1MS_TPIR Register
            19. 14.9.5.3.2.19 DMTIMER1MS_TNIR Register
            20. 14.9.5.3.2.20 DMTIMER1MS_TCVR Register
            21. 14.9.5.3.2.21 DMTIMER1MS_TOCR Register
            22. 14.9.5.3.2.22 DMTIMER1MS_TOWR Register
      6. 14.9.6 Internal Diagnostics Modules Registers
        1. 14.9.6.1 DCC
          1. 14.9.6.1.1 INTAGGR_GCNTCFG_DMASS_INTAGGR_0_GEVI_MAP_J Registers
            1.         9739
          2. 14.9.6.1.2 INTAGGR_MCAST_DMASS_INTAGGR_0_GEVI_MCMAP_J Registers
            1. 14.9.6.1.2.1  DCC2_DCCGCTRL Register
            2. 14.9.6.1.2.2  DCC2_DCCREV Register
            3. 14.9.6.1.2.3  DCC2_DCCCNTSEED0 Register
            4. 14.9.6.1.2.4  DCC2_DCCVALIDSEED0 Register
            5. 14.9.6.1.2.5  DCC2_DCCCNTSEED1 Register
            6. 14.9.6.1.2.6  DCC2_DCCSTATUS Register
            7. 14.9.6.1.2.7  DCC2_DCCCNT0 Register
            8. 14.9.6.1.2.8  DCC2_DCCVALID0 Register
            9. 14.9.6.1.2.9  DCC2_DCCCNT1 Register
            10. 14.9.6.1.2.10 DCC2_DCCCLKSRC1 Register
            11. 14.9.6.1.2.11 DCC2_DCCCLKSRC0 Register
            12. 14.9.6.1.2.12 DCC2_DCCGCTRL2 Register
            13. 14.9.6.1.2.13 DCC2_DCCSTATUS2 Register
            14. 14.9.6.1.2.14 DCC2_DCCERRCNT Register
        2. 14.9.6.2 ESM Registers
        3. 14.9.6.3 MCRC64
          1. 14.9.6.3.1 MCRC64 Summaries
            1.         9758
          2. 14.9.6.3.2 MCRC64 Registers
            1. 14.9.6.3.2.1  CRC_CTRL0 Register
            2. 14.9.6.3.2.2  CRC_CTRL1 Register
            3. 14.9.6.3.2.3  CRC_CTRL2 Register
            4. 14.9.6.3.2.4  CRC_INTS Register
            5. 14.9.6.3.2.5  CRC_INTR Register
            6. 14.9.6.3.2.6  CRC_STATUS Register
            7. 14.9.6.3.2.7  CRC_INT_OFFSET_REG Register
            8. 14.9.6.3.2.8  CRC_BUSY Register
            9. 14.9.6.3.2.9  CRC_PCOUNT_REG1 Register
            10. 14.9.6.3.2.10 CRC_SCOUNT_REG1 Register
            11. 14.9.6.3.2.11 CRC_CURSEC_REG1 Register
            12. 14.9.6.3.2.12 CRC_WDTOPLD1 Register
            13. 14.9.6.3.2.13 CRC_BCTOPLD1 Register
            14. 14.9.6.3.2.14 CRC_PSA_SIGREGL1 Register
            15. 14.9.6.3.2.15 CRC_PSA_SIGREGH1 Register
            16. 14.9.6.3.2.16 CRC_REGL1 Register
            17. 14.9.6.3.2.17 CRC_REGH1 Register
            18. 14.9.6.3.2.18 CRC_PSA_SECSIGREGL1 Register
            19. 14.9.6.3.2.19 CRC_PSA_SECSIGREGH1 Register
            20. 14.9.6.3.2.20 CRC_RAW_DATAREGL1 Register
            21. 14.9.6.3.2.21 CRC_RAW_DATAREGH1 Register
            22. 14.9.6.3.2.22 CRC_PCOUNT_REG2 Register
            23. 14.9.6.3.2.23 CRC_SCOUNT_REG2 Register
            24. 14.9.6.3.2.24 CRC_CURSEC_REG2 Register
            25. 14.9.6.3.2.25 CRC_WDTOPLD2 Register
            26. 14.9.6.3.2.26 CRC_BCTOPLD2 Register
            27. 14.9.6.3.2.27 CRC_PSA_SIGREGL2 Register
            28. 14.9.6.3.2.28 CRC_PSA_SIGREGH2 Register
            29. 14.9.6.3.2.29 CRC_REGL2 Register
            30. 14.9.6.3.2.30 CRC_REGH2 Register
            31. 14.9.6.3.2.31 CRC_PSA_SECSIGREGL2 Register
            32. 14.9.6.3.2.32 CRC_PSA_SECSIGREGH2 Register
            33. 14.9.6.3.2.33 CRC_RAW_DATAREGL2 Register
            34. 14.9.6.3.2.34 CRC_RAW_DATAREGH2 Register
            35. 14.9.6.3.2.35 CRC_PCOUNT_REG3 Register
            36. 14.9.6.3.2.36 CRC_SCOUNT_REG3 Register
            37. 14.9.6.3.2.37 CRC_CURSEC_REG3 Register
            38. 14.9.6.3.2.38 CRC_WDTOPLD3 Register
            39. 14.9.6.3.2.39 CRC_BCTOPLD3 Register
            40. 14.9.6.3.2.40 CRC_PSA_SIGREGL3 Register
            41. 14.9.6.3.2.41 CRC_PSA_SIGREGH3 Register
            42. 14.9.6.3.2.42 CRC_REGL3 Register
            43. 14.9.6.3.2.43 CRC_REGH3 Register
            44. 14.9.6.3.2.44 CRC_PSA_SECSIGREGL3 Register
            45. 14.9.6.3.2.45 CRC_PSA_SECSIGREGH3 Register
            46. 14.9.6.3.2.46 CRC_RAW_DATAREGL3 Register
            47. 14.9.6.3.2.47 CRC_RAW_DATAREGH3 Register
            48. 14.9.6.3.2.48 CRC_PCOUNT_REG4 Register
            49. 14.9.6.3.2.49 CRC_SCOUNT_REG4 Register
            50. 14.9.6.3.2.50 CRC_CURSEC_REG4 Register
            51. 14.9.6.3.2.51 CRC_WDTOPLD4 Register
            52. 14.9.6.3.2.52 CRC_BCTOPLD4 Register
            53. 14.9.6.3.2.53 CRC_PSA_SIGREGL4 Register
            54. 14.9.6.3.2.54 CRC_PSA_SIGREGH4 Register
            55. 14.9.6.3.2.55 CRC_REGL4 Register
            56. 14.9.6.3.2.56 CRC_REGH4 Register
            57. 14.9.6.3.2.57 CRC_PSA_SECSIGREGL4 Register
            58. 14.9.6.3.2.58 CRC_PSA_SECSIGREGH4 Register
            59. 14.9.6.3.2.59 CRC_RAW_DATAREGL4 Register
            60. 14.9.6.3.2.60 CRC_RAW_DATAREGH4 Register
            61. 14.9.6.3.2.61 CRC_MBUS_SEL Register
            62. 14.9.6.3.2.62 CRC_I0_PSA_SIGREG1_CPY_j Register
            63. 14.9.6.3.2.63 CRC_I0_PSA_SIGREG2_CPY_j Register
            64. 14.9.6.3.2.64 CRC_I0_PSA_SIGREG3_CPY_j Register
            65. 14.9.6.3.2.65 CRC_I0_PSA_SIGREG4_CPY_j Register
        4. 14.9.6.4 ecc_aggr
          1. 14.9.6.4.1 ecc_aggr Summaries
            1.         9827
          2. 14.9.6.4.2 ecc_aggr Registers
            1. 14.9.6.4.2.1  ECC_AGGR_REV Register
            2. 14.9.6.4.2.2  ECC_AGGR_VECTOR Register
            3. 14.9.6.4.2.3  ECC_AGGR_STAT Register
            4. 14.9.6.4.2.4  ECC_AGGR_RESERVED_SVBUS_j Register
            5. 14.9.6.4.2.5  ECC_AGGR_SEC_EOI_REG Register
            6. 14.9.6.4.2.6  ECC_AGGR_SEC_STATUS_REG0 Register
            7. 14.9.6.4.2.7  ECC_AGGR_SEC_ENABLE_SET_REG0 Register
            8. 14.9.6.4.2.8  ECC_AGGR_SEC_ENABLE_CLR_REG0 Register
            9. 14.9.6.4.2.9  ECC_AGGR_DED_EOI_REG Register
            10. 14.9.6.4.2.10 ECC_AGGR_DED_STATUS_REG0 Register
            11. 14.9.6.4.2.11 ECC_AGGR_DED_ENABLE_SET_REG0 Register
            12. 14.9.6.4.2.12 ECC_AGGR_DED_ENABLE_CLR_REG0 Register
            13. 14.9.6.4.2.13 ECC_AGGR_AGGR_ENABLE_SET Register
            14. 14.9.6.4.2.14 ECC_AGGR_AGGR_ENABLE_CLR Register
            15. 14.9.6.4.2.15 ECC_AGGR_AGGR_STATUS_SET Register
            16. 14.9.6.4.2.16 ECC_AGGR_AGGR_STATUS_CLR Register
    10. 14.10 PBIST Registers
      1. 14.10.1 PBIST
        1. 14.10.1.1 PBIST Summaries
          1.        9848
        2. 14.10.1.2 PBIST Registers
          1. 14.10.1.2.1  PBIST_A0 Register
          2. 14.10.1.2.2  PBIST_A1 Register
          3. 14.10.1.2.3  PBIST_A2 Register
          4. 14.10.1.2.4  PBIST_A3 Register
          5. 14.10.1.2.5  PBIST_L0 Register
          6. 14.10.1.2.6  PBIST_L1 Register
          7. 14.10.1.2.7  PBIST_L2 Register
          8. 14.10.1.2.8  PBIST_L3 Register
          9. 14.10.1.2.9  PBIST_D Register
          10. 14.10.1.2.10 PBIST_E Register
          11. 14.10.1.2.11 PBIST_CA0 Register
          12. 14.10.1.2.12 PBIST_CA1 Register
          13. 14.10.1.2.13 PBIST_CA2 Register
          14. 14.10.1.2.14 PBIST_CA3 Register
          15. 14.10.1.2.15 PBIST_CL0 Register
          16. 14.10.1.2.16 PBIST_CL1 Register
          17. 14.10.1.2.17 PBIST_CL2 Register
          18. 14.10.1.2.18 PBIST_CL3 Register
          19. 14.10.1.2.19 PBIST_I0 Register
          20. 14.10.1.2.20 PBIST_I1 Register
          21. 14.10.1.2.21 PBIST_I2 Register
          22. 14.10.1.2.22 PBIST_I3 Register
          23. 14.10.1.2.23 PBIST_RAMT Register
          24. 14.10.1.2.24 PBIST_DLR Register
          25. 14.10.1.2.25 PBIST_CMS Register
          26. 14.10.1.2.26 PBIST_STR Register
          27. 14.10.1.2.27 PBIST_SCR Register
          28. 14.10.1.2.28 PBIST_CSR Register
          29. 14.10.1.2.29 PBIST_FDLY Register
          30. 14.10.1.2.30 PBIST_PACT Register
          31. 14.10.1.2.31 PBIST_PID Register
          32. 14.10.1.2.32 PBIST_OVER Register
          33. 14.10.1.2.33 PBIST_FSRF Register
          34. 14.10.1.2.34 PBIST_FSRC Register
          35. 14.10.1.2.35 PBIST_FSRA Register
          36. 14.10.1.2.36 PBIST_FSRDL0 Register
          37. 14.10.1.2.37 PBIST_FSRDL1 Register
          38. 14.10.1.2.38 PBIST_MARGIN_MODE Register
          39. 14.10.1.2.39 PBIST_WRENZ Register
          40. 14.10.1.2.40 PBIST_PAGE_PGS Register
          41. 14.10.1.2.41 PBIST_ROM Register
          42. 14.10.1.2.42 PBIST_ALGO Register
          43. 14.10.1.2.43 PBIST_RINFO Register
    11. 14.11 On-Chip Debug Registers
      1. 14.11.1 debugss
        1. 14.11.1.1 debugss Summaries
          1.        9896
          2.        9897
          3.        9898
          4.        9899
          5.        9900
          6.        9901
          7.        9902
          8.        9903
          9.        9904
          10.        9905
          11.        9906
          12.        9907
          13.        9908
          14.        9909
        2. 14.11.1.2 debugss Registers
          1. 14.11.1.2.1   DEBUGSS_SYS_TRACE Register
          2. 14.11.1.2.2   DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY1 Register
          3. 14.11.1.2.3   DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY2 Register
          4. 14.11.1.2.4   DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY3 Register
          5. 14.11.1.2.5   DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY4 Register
          6. 14.11.1.2.6   DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY5 Register
          7. 14.11.1.2.7   DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY6 Register
          8. 14.11.1.2.8   DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY7 Register
          9. 14.11.1.2.9   DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY8 Register
          10. 14.11.1.2.10  DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY9 Register
          11. 14.11.1.2.11  DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY10 Register
          12. 14.11.1.2.12  DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY11 Register
          13. 14.11.1.2.13  DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY12 Register
          14. 14.11.1.2.14  DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY13 Register
          15. 14.11.1.2.15  DEBUGSS_DEBUG_CELL_ROM_SLV_ENTRY14 Register
          16. 14.11.1.2.16  DEBUGSS_DEBUG_CELL_ROM_SLV_PERIPHID4 Register
          17. 14.11.1.2.17  DEBUGSS_DEBUG_CELL_ROM_SLV_PERIPHID5 Register
          18. 14.11.1.2.18  DEBUGSS_DEBUG_CELL_ROM_SLV_PERIPHID6 Register
          19. 14.11.1.2.19  DEBUGSS_DEBUG_CELL_ROM_SLV_PERIPHID7 Register
          20. 14.11.1.2.20  DEBUGSS_DEBUG_CELL_ROM_SLV_PERIPHID0 Register
          21. 14.11.1.2.21  DEBUGSS_DEBUG_CELL_ROM_SLV_PERIPHID1 Register
          22. 14.11.1.2.22  DEBUGSS_DEBUG_CELL_ROM_SLV_PERIPHID2 Register
          23. 14.11.1.2.23  DEBUGSS_DEBUG_CELL_ROM_SLV_PERIPHID3 Register
          24. 14.11.1.2.24  DEBUGSS_DEBUG_CELL_ROM_SLV_COMPONENTID0 Register
          25. 14.11.1.2.25  DEBUGSS_DEBUG_CELL_ROM_SLV_COMPONENTID1 Register
          26. 14.11.1.2.26  DEBUGSS_DEBUG_CELL_ROM_SLV_COMPONENTID2 Register
          27. 14.11.1.2.27  DEBUGSS_DEBUG_CELL_ROM_SLV_COMPONENTID3 Register
          28. 14.11.1.2.28  CTSET2_CFG_CTSETID Register
          29. 14.11.1.2.29  CTSET2_CFG_CTSETSYSCFG Register
          30. 14.11.1.2.30  CTSET2_CFG_SETSTR Register
          31. 14.11.1.2.31  CTSET2_CFG_DBGTIMELOW Register
          32. 14.11.1.2.32  CTSET2_CFG_DBGTIMEHI Register
          33. 14.11.1.2.33  CTSET2_CFG_CTSETCFG Register
          34. 14.11.1.2.34  CTSET2_CFG_SETSPLREG Register
          35. 14.11.1.2.35  CTSET2_CFG_SETEVTENBL1 Register
          36. 14.11.1.2.36  CTSET2_CFG_SETEVTENBL2 Register
          37. 14.11.1.2.37  CTSET2_CFG_SETEVTENBL3 Register
          38. 14.11.1.2.38  CTSET2_CFG_SETEVTENBL4 Register
          39. 14.11.1.2.39  CTSET2_CFG_SETEVTENBL5 Register
          40. 14.11.1.2.40  CTSET2_CFG_SETEVTENBL6 Register
          41. 14.11.1.2.41  CTSET2_CFG_SETEVTENBL7 Register
          42. 14.11.1.2.42  CTSET2_CFG_SETEVTENBL8 Register
          43. 14.11.1.2.43  CTSET2_CFG_SETMSTID Register
          44. 14.11.1.2.44  CTSET2_CFG_CTCNTL Register
          45. 14.11.1.2.45  CTSET2_CFG_CTNUMDBG Register
          46. 14.11.1.2.46  CTSET2_CFG_CTUSERACCCTL Register
          47. 14.11.1.2.47  CTSET2_CFG_CTSTMCNTL Register
          48. 14.11.1.2.48  CTSET2_CFG_CTSTMMSTID Register
          49. 14.11.1.2.49  CTSET2_CFG_CTSTMINTVL Register
          50. 14.11.1.2.50  CTSET2_CFG_CTSTMSEL0 Register
          51. 14.11.1.2.51  CTSET2_CFG_CTSTMSEL1 Register
          52. 14.11.1.2.52  CTSET2_CFG_CTINTVLR0 Register
          53. 14.11.1.2.53  CTSET2_CFG_CTINTVLR1 Register
          54. 14.11.1.2.54  CTSET2_CFG_CTINTVLR2 Register
          55. 14.11.1.2.55  CTSET2_CFG_CTINTVLR3 Register
          56. 14.11.1.2.56  CTSET2_CFG_CTINTVLR4 Register
          57. 14.11.1.2.57  CTSET2_CFG_CTINTVLR5 Register
          58. 14.11.1.2.58  CTSET2_CFG_CTINTVLR6 Register
          59. 14.11.1.2.59  CTSET2_CFG_CTINTVLR7 Register
          60. 14.11.1.2.60  CTSET2_CFG_CTINTVLR8 Register
          61. 14.11.1.2.61  CTSET2_CFG_CTINTVLR9 Register
          62. 14.11.1.2.62  CTSET2_CFG_CTINTVLR10 Register
          63. 14.11.1.2.63  CTSET2_CFG_CTINTVLR11 Register
          64. 14.11.1.2.64  CTSET2_CFG_CTINTVLR12 Register
          65. 14.11.1.2.65  CTSET2_CFG_CTINTVLR13 Register
          66. 14.11.1.2.66  CTSET2_CFG_CTINTVLR14 Register
          67. 14.11.1.2.67  CTSET2_CFG_CTINTVLR15 Register
          68. 14.11.1.2.68  CTSET2_CFG_CTDBGSGL0 Register
          69. 14.11.1.2.69  CTSET2_CFG_CTDBGSGL1 Register
          70. 14.11.1.2.70  CTSET2_CFG_CTDBGSGL2 Register
          71. 14.11.1.2.71  CTSET2_CFG_CTDBGSGL3 Register
          72. 14.11.1.2.72  CTSET2_CFG_CTDBGSGL4 Register
          73. 14.11.1.2.73  CTSET2_CFG_CTDBGSGL5 Register
          74. 14.11.1.2.74  CTSET2_CFG_CTDBGSGL6 Register
          75. 14.11.1.2.75  CTSET2_CFG_CTDBGSGL7 Register
          76. 14.11.1.2.76  CTSET2_CFG_CTGNBL0 Register
          77. 14.11.1.2.77  CTSET2_CFG_CTGNBL1 Register
          78. 14.11.1.2.78  CTSET2_CFG_CTGRST0 Register
          79. 14.11.1.2.79  CTSET2_CFG_CTGRST1 Register
          80. 14.11.1.2.80  CTSET2_CFG_CTCR0 Register
          81. 14.11.1.2.81  CTSET2_CFG_CTCR1 Register
          82. 14.11.1.2.82  CTSET2_CFG_CTCR2 Register
          83. 14.11.1.2.83  CTSET2_CFG_CTCR3 Register
          84. 14.11.1.2.84  CTSET2_CFG_CTCR4 Register
          85. 14.11.1.2.85  CTSET2_CFG_CTCR5 Register
          86. 14.11.1.2.86  CTSET2_CFG_CTCR6 Register
          87. 14.11.1.2.87  CTSET2_CFG_CTCR7 Register
          88. 14.11.1.2.88  CTSET2_CFG_CTCR8 Register
          89. 14.11.1.2.89  CTSET2_CFG_CTCR9 Register
          90. 14.11.1.2.90  CTSET2_CFG_CTCR10 Register
          91. 14.11.1.2.91  CTSET2_CFG_CTCR11 Register
          92. 14.11.1.2.92  CTSET2_CFG_CTCR12 Register
          93. 14.11.1.2.93  CTSET2_CFG_CTCR13 Register
          94. 14.11.1.2.94  CTSET2_CFG_CTCR14 Register
          95. 14.11.1.2.95  CTSET2_CFG_CTCR15 Register
          96. 14.11.1.2.96  CTSET2_CFG_CTCR16 Register
          97. 14.11.1.2.97  CTSET2_CFG_CTCR17 Register
          98. 14.11.1.2.98  CTSET2_CFG_CTCR18 Register
          99. 14.11.1.2.99  CTSET2_CFG_CTCR19 Register
          100. 14.11.1.2.100 CTSET2_CFG_CTCR20 Register
          101. 14.11.1.2.101 CTSET2_CFG_CTCR21 Register
          102. 14.11.1.2.102 CTSET2_CFG_CTCR22 Register
          103. 14.11.1.2.103 CTSET2_CFG_CTCR23 Register
          104. 14.11.1.2.104 CTSET2_CFG_CTCR24 Register
          105. 14.11.1.2.105 CTSET2_CFG_CTCR25 Register
          106. 14.11.1.2.106 CTSET2_CFG_CTCR26 Register
          107. 14.11.1.2.107 CTSET2_CFG_CTCR27 Register
          108. 14.11.1.2.108 CTSET2_CFG_CTCR28 Register
          109. 14.11.1.2.109 CTSET2_CFG_CTCR29 Register
          110. 14.11.1.2.110 CTSET2_CFG_CTCR30 Register
          111. 14.11.1.2.111 CTSET2_CFG_CTCR31 Register
          112. 14.11.1.2.112 CTSET2_CFG_CTOWN0 Register
          113. 14.11.1.2.113 CTSET2_CFG_CTOWN1 Register
          114. 14.11.1.2.114 CTSET2_CFG_CTOWN2 Register
          115. 14.11.1.2.115 CTSET2_CFG_CTOWN3 Register
          116. 14.11.1.2.116 CTSET2_CFG_CTOWN4 Register
          117. 14.11.1.2.117 CTSET2_CFG_CTOWN5 Register
          118. 14.11.1.2.118 CTSET2_CFG_CTOWN6 Register
          119. 14.11.1.2.119 CTSET2_CFG_CTOWN7 Register
          120. 14.11.1.2.120 CTSET2_CFG_CTOWN8 Register
          121. 14.11.1.2.121 CTSET2_CFG_CTOWN9 Register
          122. 14.11.1.2.122 CTSET2_CFG_CTOWN10 Register
          123. 14.11.1.2.123 CTSET2_CFG_CTOWN11 Register
          124. 14.11.1.2.124 CTSET2_CFG_CTOWN12 Register
          125. 14.11.1.2.125 CTSET2_CFG_CTOWN13 Register
          126. 14.11.1.2.126 CTSET2_CFG_CTOWN14 Register
          127. 14.11.1.2.127 CTSET2_CFG_CTOWN15 Register
          128. 14.11.1.2.128 CTSET2_CFG_CTOWN16 Register
          129. 14.11.1.2.129 CTSET2_CFG_CTOWN17 Register
          130. 14.11.1.2.130 CTSET2_CFG_CTOWN18 Register
          131. 14.11.1.2.131 CTSET2_CFG_CTOWN19 Register
          132. 14.11.1.2.132 CTSET2_CFG_CTOWN20 Register
          133. 14.11.1.2.133 CTSET2_CFG_CTOWN21 Register
          134. 14.11.1.2.134 CTSET2_CFG_CTOWN22 Register
          135. 14.11.1.2.135 CTSET2_CFG_CTOWN23 Register
          136. 14.11.1.2.136 CTSET2_CFG_CTOWN24 Register
          137. 14.11.1.2.137 CTSET2_CFG_CTOWN25 Register
          138. 14.11.1.2.138 CTSET2_CFG_CTOWN26 Register
          139. 14.11.1.2.139 CTSET2_CFG_CTOWN27 Register
          140. 14.11.1.2.140 CTSET2_CFG_CTOWN28 Register
          141. 14.11.1.2.141 CTSET2_CFG_CTOWN29 Register
          142. 14.11.1.2.142 CTSET2_CFG_CTOWN30 Register
          143. 14.11.1.2.143 CTSET2_CFG_CTOWN31 Register
          144. 14.11.1.2.144 CTSET2_CFG_CTFILT0 Register
          145. 14.11.1.2.145 CTSET2_CFG_CTFILT1 Register
          146. 14.11.1.2.146 CTSET2_CFG_CTFILT2 Register
          147. 14.11.1.2.147 CTSET2_CFG_CTFILT3 Register
          148. 14.11.1.2.148 CTSET2_CFG_CTFILT4 Register
          149. 14.11.1.2.149 CTSET2_CFG_CTFILT5 Register
          150. 14.11.1.2.150 CTSET2_CFG_CTFILT6 Register
          151. 14.11.1.2.151 CTSET2_CFG_CTFILT7 Register
          152. 14.11.1.2.152 CTSET2_CFG_CTFILT8 Register
          153. 14.11.1.2.153 CTSET2_CFG_CTFILT9 Register
          154. 14.11.1.2.154 CTSET2_CFG_CTFILT10 Register
          155. 14.11.1.2.155 CTSET2_CFG_CTFILT11 Register
          156. 14.11.1.2.156 CTSET2_CFG_CTFILT12 Register
          157. 14.11.1.2.157 CTSET2_CFG_CTFILT13 Register
          158. 14.11.1.2.158 CTSET2_CFG_CTFILT14 Register
          159. 14.11.1.2.159 CTSET2_CFG_CTFILT15 Register
          160. 14.11.1.2.160 CTSET2_CFG_CTFILT16 Register
          161. 14.11.1.2.161 CTSET2_CFG_CTFILT17 Register
          162. 14.11.1.2.162 CTSET2_CFG_CTFILT18 Register
          163. 14.11.1.2.163 CTSET2_CFG_CTFILT19 Register
          164. 14.11.1.2.164 CTSET2_CFG_CTFILT20 Register
          165. 14.11.1.2.165 CTSET2_CFG_CTFILT21 Register
          166. 14.11.1.2.166 CTSET2_CFG_CTFILT22 Register
          167. 14.11.1.2.167 CTSET2_CFG_CTFILT23 Register
          168. 14.11.1.2.168 CTSET2_CFG_CTFILT24 Register
          169. 14.11.1.2.169 CTSET2_CFG_CTFILT25 Register
          170. 14.11.1.2.170 CTSET2_CFG_CTFILT26 Register
          171. 14.11.1.2.171 CTSET2_CFG_CTFILT27 Register
          172. 14.11.1.2.172 CTSET2_CFG_CTFILT28 Register
          173. 14.11.1.2.173 CTSET2_CFG_CTFILT29 Register
          174. 14.11.1.2.174 CTSET2_CFG_CTFILT30 Register
          175. 14.11.1.2.175 CTSET2_CFG_CTFILT31 Register
          176. 14.11.1.2.176 CTSET2_CFG_CTCNTR0 Register
          177. 14.11.1.2.177 CTSET2_CFG_CTCNTR1 Register
          178. 14.11.1.2.178 CTSET2_CFG_CTCNTR2 Register
          179. 14.11.1.2.179 CTSET2_CFG_CTCNTR3 Register
          180. 14.11.1.2.180 CTSET2_CFG_CTCNTR4 Register
          181. 14.11.1.2.181 CTSET2_CFG_CTCNTR5 Register
          182. 14.11.1.2.182 CTSET2_CFG_CTCNTR6 Register
          183. 14.11.1.2.183 CTSET2_CFG_CTCNTR7 Register
          184. 14.11.1.2.184 CTSET2_CFG_CTCNTR8 Register
          185. 14.11.1.2.185 CTSET2_CFG_CTCNTR9 Register
          186. 14.11.1.2.186 CTSET2_CFG_CTCNTR10 Register
          187. 14.11.1.2.187 CTSET2_CFG_CTCNTR11 Register
          188. 14.11.1.2.188 CTSET2_CFG_CTCNTR12 Register
          189. 14.11.1.2.189 CTSET2_CFG_CTCNTR13 Register
          190. 14.11.1.2.190 CTSET2_CFG_CTCNTR14 Register
          191. 14.11.1.2.191 CTSET2_CFG_CTCNTR15 Register
          192. 14.11.1.2.192 CTSET2_CFG_CTCNTR16 Register
          193. 14.11.1.2.193 CTSET2_CFG_CTCNTR17 Register
          194. 14.11.1.2.194 CTSET2_CFG_CTCNTR18 Register
          195. 14.11.1.2.195 CTSET2_CFG_CTCNTR19 Register
          196. 14.11.1.2.196 CTSET2_CFG_CTCNTR20 Register
          197. 14.11.1.2.197 CTSET2_CFG_CTCNTR21 Register
          198. 14.11.1.2.198 CTSET2_CFG_CTCNTR22 Register
          199. 14.11.1.2.199 CTSET2_CFG_CTCNTR23 Register
          200. 14.11.1.2.200 CTSET2_CFG_CTCNTR24 Register
          201. 14.11.1.2.201 CTSET2_CFG_CTCNTR25 Register
          202. 14.11.1.2.202 CTSET2_CFG_CTCNTR26 Register
          203. 14.11.1.2.203 CTSET2_CFG_CTCNTR27 Register
          204. 14.11.1.2.204 CTSET2_CFG_CTCNTR28 Register
          205. 14.11.1.2.205 CTSET2_CFG_CTCNTR29 Register
          206. 14.11.1.2.206 CTSET2_CFG_CTCNTR30 Register
          207. 14.11.1.2.207 CTSET2_CFG_CTCNTR31 Register
          208. 14.11.1.2.208 CTSET2_CFG_CT_EOI Register
          209. 14.11.1.2.209 CTSET2_CFG_CTIRQSTAT_RAW Register
          210. 14.11.1.2.210 CTSET2_CFG_CTIRQSTAT Register
          211. 14.11.1.2.211 CTSET2_CFG_CTIRQENABLE_SET Register
          212. 14.11.1.2.212 CTSET2_CFG_CTIRQENABLE_CLR Register
          213. 14.11.1.2.213 CTSET2_CFG_STPTCR Register
          214. 14.11.1.2.214 CTSET2_CFG_STPTID Register
          215. 14.11.1.2.215 CTSET2_CFG_STPASYNC Register
          216. 14.11.1.2.216 CTSET2_CFG_STPFFCR Register
          217. 14.11.1.2.217 CTSET2_CFG_STPFEAT1 Register
          218. 14.11.1.2.218 CXATBREPLICATOR_CFG_IDFILTER0 Register
          219. 14.11.1.2.219 CXATBREPLICATOR_CFG_IDFILTER1 Register
          220. 14.11.1.2.220 CXATBREPLICATOR_CFG_ITATBCTR1 Register
          221. 14.11.1.2.221 CXATBREPLICATOR_CFG_ITATBCTR0 Register
          222. 14.11.1.2.222 CXATBREPLICATOR_CFG_ITCTRL Register
          223. 14.11.1.2.223 CXATBREPLICATOR_CFG_CLAIMSET Register
          224. 14.11.1.2.224 CXATBREPLICATOR_CFG_CLAIMCLR Register
          225. 14.11.1.2.225 CXATBREPLICATOR_CFG_LAR Register
          226. 14.11.1.2.226 CXATBREPLICATOR_CFG_LSR Register
          227. 14.11.1.2.227 CXATBREPLICATOR_CFG_AUTHSTATUS Register
          228. 14.11.1.2.228 CXATBREPLICATOR_CFG_DEVID Register
          229. 14.11.1.2.229 CXATBREPLICATOR_CFG_DEVTYPE Register
          230. 14.11.1.2.230 CXATBREPLICATOR_CFG_PIDR4 Register
          231. 14.11.1.2.231 CXATBREPLICATOR_CFG_PIDR0 Register
          232. 14.11.1.2.232 CXATBREPLICATOR_CFG_PIDR1 Register
          233. 14.11.1.2.233 CXATBREPLICATOR_CFG_PIDR2 Register
          234. 14.11.1.2.234 CXATBREPLICATOR_CFG_PIDR3 Register
          235. 14.11.1.2.235 CXATBREPLICATOR_CFG_CIDR0 Register
          236. 14.11.1.2.236 CXATBREPLICATOR_CFG_CIDR1 Register
          237. 14.11.1.2.237 CXATBREPLICATOR_CFG_CIDR2 Register
          238. 14.11.1.2.238 CXATBREPLICATOR_CFG_CIDR3 Register
          239. 14.11.1.2.239 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_CT_TBR_RAMSZ Register
          240. 14.11.1.2.240 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_FIFOSZ Register
          241. 14.11.1.2.241 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_STAT Register
          242. 14.11.1.2.242 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_RAMRDAT Register
          243. 14.11.1.2.243 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_RAMRPTR Register
          244. 14.11.1.2.244 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_RAMWPTR Register
          245. 14.11.1.2.245 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_TRGCNT Register
          246. 14.11.1.2.246 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_TBR_CTRL Register
          247. 14.11.1.2.247 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_RAMWDAT Register
          248. 14.11.1.2.248 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_OUTLVL Register
          249. 14.11.1.2.249 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_SICTRL Register
          250. 14.11.1.2.250 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_IDPERIOD Register
          251. 14.11.1.2.251 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_CT_TBR_SEQCNTL Register
          252. 14.11.1.2.252 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_EOI Register
          253. 14.11.1.2.253 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_IRQSTATUS_RAW Register
          254. 14.11.1.2.254 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_IRQSTATUS Register
          255. 14.11.1.2.255 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_IRQENABLE_SET Register
          256. 14.11.1.2.256 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_IRQENABLE_CLR Register
          257. 14.11.1.2.257 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_OPSTAT Register
          258. 14.11.1.2.258 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_OPCTRL Register
          259. 14.11.1.2.259 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_CLAIMSET Register
          260. 14.11.1.2.260 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_CLAIMCLR Register
          261. 14.11.1.2.261 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_LOCKACC Register
          262. 14.11.1.2.262 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_LOCKSTAT Register
          263. 14.11.1.2.263 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_AUTHSTAT Register
          264. 14.11.1.2.264 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_DEVID Register
          265. 14.11.1.2.265 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_DEVTYPE Register
          266. 14.11.1.2.266 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_PERIPHID4 Register
          267. 14.11.1.2.267 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_PERIPHID5 Register
          268. 14.11.1.2.268 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_PERIPHID6 Register
          269. 14.11.1.2.269 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_PERIPHID7 Register
          270. 14.11.1.2.270 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_PERIPHID0 Register
          271. 14.11.1.2.271 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_PERIPHID1 Register
          272. 14.11.1.2.272 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_PERIPHID2 Register
          273. 14.11.1.2.273 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_PERIPHID3 Register
          274. 14.11.1.2.274 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_COMPID0 Register
          275. 14.11.1.2.275 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_COMPID1 Register
          276. 14.11.1.2.276 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_COMPID2 Register
          277. 14.11.1.2.277 DEBUGSS_TBR_VBUSP_WRAP_TBR_CFG_TBR_CFG_COMPID3 Register
          278. 14.11.1.2.278 CSCTI_CTICONTROL Register
          279. 14.11.1.2.279 CSCTI_CTIINTACK Register
          280. 14.11.1.2.280 CSCTI_CTIAPPSET Register
          281. 14.11.1.2.281 CSCTI_CTIAPPCLEAR Register
          282. 14.11.1.2.282 CSCTI_CTIAPPPULSE Register
          283. 14.11.1.2.283 CSCTI_CTIINEN0 Register
          284. 14.11.1.2.284 CSCTI_CTIINEN1 Register
          285. 14.11.1.2.285 CSCTI_CTIINEN2 Register
          286. 14.11.1.2.286 CSCTI_CTIINEN3 Register
          287. 14.11.1.2.287 CSCTI_CTIINEN4 Register
          288. 14.11.1.2.288 CSCTI_CTIINEN5 Register
          289. 14.11.1.2.289 CSCTI_CTIINEN6 Register
          290. 14.11.1.2.290 CSCTI_CTIINEN7 Register
          291. 14.11.1.2.291 CSCTI_CTIOUTEN0 Register
          292. 14.11.1.2.292 CSCTI_CTIOUTEN1 Register
          293. 14.11.1.2.293 CSCTI_CTIOUTEN2 Register
          294. 14.11.1.2.294 CSCTI_CTIOUTEN3 Register
          295. 14.11.1.2.295 CSCTI_CTIOUTEN4 Register
          296. 14.11.1.2.296 CSCTI_CTIOUTEN5 Register
          297. 14.11.1.2.297 CSCTI_CTIOUTEN6 Register
          298. 14.11.1.2.298 CSCTI_CTIOUTEN7 Register
          299. 14.11.1.2.299 CSCTI_CTITRIGINSTATUS Register
          300. 14.11.1.2.300 CSCTI_CTITRIGOUTSTATUS Register
          301. 14.11.1.2.301 CSCTI_CTICHINSTATUS Register
          302. 14.11.1.2.302 CSCTI_CTICHOUTSTATUS Register
          303. 14.11.1.2.303 CSCTI_CTIGATE Register
          304. 14.11.1.2.304 CSCTI_ASICCTL Register
          305. 14.11.1.2.305 CSCTI_ITCHINACK Register
          306. 14.11.1.2.306 CSCTI_ITTRIGINACK Register
          307. 14.11.1.2.307 CSCTI_ITCHOUT Register
          308. 14.11.1.2.308 CSCTI_ITTRIGOUT Register
          309. 14.11.1.2.309 CSCTI_ITCHOUTACK Register
          310. 14.11.1.2.310 CSCTI_ITTRIGOUTACK Register
          311. 14.11.1.2.311 CSCTI_ITCHIN Register
          312. 14.11.1.2.312 CSCTI_ITTRIGIN Register
          313. 14.11.1.2.313 CSCTI_ITCTRL Register
          314. 14.11.1.2.314 CSCTI_CLAIMSET Register
          315. 14.11.1.2.315 CSCTI_CLAIMCLR Register
          316. 14.11.1.2.316 CSCTI_LAR Register
          317. 14.11.1.2.317 CSCTI_LSR Register
          318. 14.11.1.2.318 CSCTI_AUTHSTATUS Register
          319. 14.11.1.2.319 CSCTI_DEVID Register
          320. 14.11.1.2.320 CSCTI_DEVTYPE Register
          321. 14.11.1.2.321 CSCTI_PERIPHID4 Register
          322. 14.11.1.2.322 CSCTI_PERIPHID0 Register
          323. 14.11.1.2.323 CSCTI_PERIPHID1 Register
          324. 14.11.1.2.324 CSCTI_PERIPHID2 Register
          325. 14.11.1.2.325 CSCTI_PERIPHID3 Register
          326. 14.11.1.2.326 CSCTI_COMPID0 Register
          327. 14.11.1.2.327 CSCTI_COMPID1 Register
          328. 14.11.1.2.328 CSCTI_COMPID2 Register
          329. 14.11.1.2.329 CSCTI_COMPID3 Register
          330. 14.11.1.2.330 CSCTI_CTICONTROL Register
          331. 14.11.1.2.331 CSCTI_CTIINTACK Register
          332. 14.11.1.2.332 CSCTI_CTIAPPSET Register
          333. 14.11.1.2.333 CSCTI_CTIAPPCLEAR Register
          334. 14.11.1.2.334 CSCTI_CTIAPPPULSE Register
          335. 14.11.1.2.335 CSCTI_CTIINEN0 Register
          336. 14.11.1.2.336 CSCTI_CTIINEN1 Register
          337. 14.11.1.2.337 CSCTI_CTIINEN2 Register
          338. 14.11.1.2.338 CSCTI_CTIINEN3 Register
          339. 14.11.1.2.339 CSCTI_CTIINEN4 Register
          340. 14.11.1.2.340 CSCTI_CTIINEN5 Register
          341. 14.11.1.2.341 CSCTI_CTIINEN6 Register
          342. 14.11.1.2.342 CSCTI_CTIINEN7 Register
          343. 14.11.1.2.343 CSCTI_CTIOUTEN0 Register
          344. 14.11.1.2.344 CSCTI_CTIOUTEN1 Register
          345. 14.11.1.2.345 CSCTI_CTIOUTEN2 Register
          346. 14.11.1.2.346 CSCTI_CTIOUTEN3 Register
          347. 14.11.1.2.347 CSCTI_CTIOUTEN4 Register
          348. 14.11.1.2.348 CSCTI_CTIOUTEN5 Register
          349. 14.11.1.2.349 CSCTI_CTIOUTEN6 Register
          350. 14.11.1.2.350 CSCTI_CTIOUTEN7 Register
          351. 14.11.1.2.351 CSCTI_CTITRIGINSTATUS Register
          352. 14.11.1.2.352 CSCTI_CTITRIGOUTSTATUS Register
          353. 14.11.1.2.353 CSCTI_CTICHINSTATUS Register
          354. 14.11.1.2.354 CSCTI_CTICHOUTSTATUS Register
          355. 14.11.1.2.355 CSCTI_CTIGATE Register
          356. 14.11.1.2.356 CSCTI_ASICCTL Register
          357. 14.11.1.2.357 CSCTI_ITCHINACK Register
          358. 14.11.1.2.358 CSCTI_ITTRIGINACK Register
          359. 14.11.1.2.359 CSCTI_ITCHOUT Register
          360. 14.11.1.2.360 CSCTI_ITTRIGOUT Register
          361. 14.11.1.2.361 CSCTI_ITCHOUTACK Register
          362. 14.11.1.2.362 CSCTI_ITTRIGOUTACK Register
          363. 14.11.1.2.363 CSCTI_ITCHIN Register
          364. 14.11.1.2.364 CSCTI_ITTRIGIN Register
          365. 14.11.1.2.365 CSCTI_ITCTRL Register
          366. 14.11.1.2.366 CSCTI_CLAIMSET Register
          367. 14.11.1.2.367 CSCTI_CLAIMCLR Register
          368. 14.11.1.2.368 CSCTI_LAR Register
          369. 14.11.1.2.369 CSCTI_LSR Register
          370. 14.11.1.2.370 CSCTI_AUTHSTATUS Register
          371. 14.11.1.2.371 CSCTI_DEVID Register
          372. 14.11.1.2.372 CSCTI_DEVTYPE Register
          373. 14.11.1.2.373 CSCTI_PERIPHID4 Register
          374. 14.11.1.2.374 CSCTI_PERIPHID0 Register
          375. 14.11.1.2.375 CSCTI_PERIPHID1 Register
          376. 14.11.1.2.376 CSCTI_PERIPHID2 Register
          377. 14.11.1.2.377 CSCTI_PERIPHID3 Register
          378. 14.11.1.2.378 CSCTI_COMPID0 Register
          379. 14.11.1.2.379 CSCTI_COMPID1 Register
          380. 14.11.1.2.380 CSCTI_COMPID2 Register
          381. 14.11.1.2.381 CSCTI_COMPID3 Register
          382. 14.11.1.2.382 CSCTI_CTICONTROL Register
          383. 14.11.1.2.383 CSCTI_CTIINTACK Register
          384. 14.11.1.2.384 CSCTI_CTIAPPSET Register
          385. 14.11.1.2.385 CSCTI_CTIAPPCLEAR Register
          386. 14.11.1.2.386 CSCTI_CTIAPPPULSE Register
          387. 14.11.1.2.387 CSCTI_CTIINEN0 Register
          388. 14.11.1.2.388 CSCTI_CTIINEN1 Register
          389. 14.11.1.2.389 CSCTI_CTIINEN2 Register
          390. 14.11.1.2.390 CSCTI_CTIINEN3 Register
          391. 14.11.1.2.391 CSCTI_CTIINEN4 Register
          392. 14.11.1.2.392 CSCTI_CTIINEN5 Register
          393. 14.11.1.2.393 CSCTI_CTIINEN6 Register
          394. 14.11.1.2.394 CSCTI_CTIINEN7 Register
          395. 14.11.1.2.395 CSCTI_CTIOUTEN0 Register
          396. 14.11.1.2.396 CSCTI_CTIOUTEN1 Register
          397. 14.11.1.2.397 CSCTI_CTIOUTEN2 Register
          398. 14.11.1.2.398 CSCTI_CTIOUTEN3 Register
          399. 14.11.1.2.399 CSCTI_CTIOUTEN4 Register
          400. 14.11.1.2.400 CSCTI_CTIOUTEN5 Register
          401. 14.11.1.2.401 CSCTI_CTIOUTEN6 Register
          402. 14.11.1.2.402 CSCTI_CTIOUTEN7 Register
          403. 14.11.1.2.403 CSCTI_CTITRIGINSTATUS Register
          404. 14.11.1.2.404 CSCTI_CTITRIGOUTSTATUS Register
          405. 14.11.1.2.405 CSCTI_CTICHINSTATUS Register
          406. 14.11.1.2.406 CSCTI_CTICHOUTSTATUS Register
          407. 14.11.1.2.407 CSCTI_CTIGATE Register
          408. 14.11.1.2.408 CSCTI_ASICCTL Register
          409. 14.11.1.2.409 CSCTI_ITCHINACK Register
          410. 14.11.1.2.410 CSCTI_ITTRIGINACK Register
          411. 14.11.1.2.411 CSCTI_ITCHOUT Register
          412. 14.11.1.2.412 CSCTI_ITTRIGOUT Register
          413. 14.11.1.2.413 CSCTI_ITCHOUTACK Register
          414. 14.11.1.2.414 CSCTI_ITTRIGOUTACK Register
          415. 14.11.1.2.415 CSCTI_ITCHIN Register
          416. 14.11.1.2.416 CSCTI_ITTRIGIN Register
          417. 14.11.1.2.417 CSCTI_ITCTRL Register
          418. 14.11.1.2.418 CSCTI_CLAIMSET Register
          419. 14.11.1.2.419 CSCTI_CLAIMCLR Register
          420. 14.11.1.2.420 CSCTI_LAR Register
          421. 14.11.1.2.421 CSCTI_LSR Register
          422. 14.11.1.2.422 CSCTI_AUTHSTATUS Register
          423. 14.11.1.2.423 CSCTI_DEVID Register
          424. 14.11.1.2.424 CSCTI_DEVTYPE Register
          425. 14.11.1.2.425 CSCTI_PERIPHID4 Register
          426. 14.11.1.2.426 CSCTI_PERIPHID0 Register
          427. 14.11.1.2.427 CSCTI_PERIPHID1 Register
          428. 14.11.1.2.428 CSCTI_PERIPHID2 Register
          429. 14.11.1.2.429 CSCTI_PERIPHID3 Register
          430. 14.11.1.2.430 CSCTI_COMPID0 Register
          431. 14.11.1.2.431 CSCTI_COMPID1 Register
          432. 14.11.1.2.432 CSCTI_COMPID2 Register
          433. 14.11.1.2.433 CSCTI_COMPID3 Register
          434. 14.11.1.2.434 CSCTI_CTICONTROL Register
          435. 14.11.1.2.435 CSCTI_CTIINTACK Register
          436. 14.11.1.2.436 CSCTI_CTIAPPSET Register
          437. 14.11.1.2.437 CSCTI_CTIAPPCLEAR Register
          438. 14.11.1.2.438 CSCTI_CTIAPPPULSE Register
          439. 14.11.1.2.439 CSCTI_CTIINEN0 Register
          440. 14.11.1.2.440 CSCTI_CTIINEN1 Register
          441. 14.11.1.2.441 CSCTI_CTIINEN2 Register
          442. 14.11.1.2.442 CSCTI_CTIINEN3 Register
          443. 14.11.1.2.443 CSCTI_CTIINEN4 Register
          444. 14.11.1.2.444 CSCTI_CTIINEN5 Register
          445. 14.11.1.2.445 CSCTI_CTIINEN6 Register
          446. 14.11.1.2.446 CSCTI_CTIINEN7 Register
          447. 14.11.1.2.447 CSCTI_CTIOUTEN0 Register
          448. 14.11.1.2.448 CSCTI_CTIOUTEN1 Register
          449. 14.11.1.2.449 CSCTI_CTIOUTEN2 Register
          450. 14.11.1.2.450 CSCTI_CTIOUTEN3 Register
          451. 14.11.1.2.451 CSCTI_CTIOUTEN4 Register
          452. 14.11.1.2.452 CSCTI_CTIOUTEN5 Register
          453. 14.11.1.2.453 CSCTI_CTIOUTEN6 Register
          454. 14.11.1.2.454 CSCTI_CTIOUTEN7 Register
          455. 14.11.1.2.455 CSCTI_CTITRIGINSTATUS Register
          456. 14.11.1.2.456 CSCTI_CTITRIGOUTSTATUS Register
          457. 14.11.1.2.457 CSCTI_CTICHINSTATUS Register
          458. 14.11.1.2.458 CSCTI_CTICHOUTSTATUS Register
          459. 14.11.1.2.459 CSCTI_CTIGATE Register
          460. 14.11.1.2.460 CSCTI_ASICCTL Register
          461. 14.11.1.2.461 CSCTI_ITCHINACK Register
          462. 14.11.1.2.462 CSCTI_ITTRIGINACK Register
          463. 14.11.1.2.463 CSCTI_ITCHOUT Register
          464. 14.11.1.2.464 CSCTI_ITTRIGOUT Register
          465. 14.11.1.2.465 CSCTI_ITCHOUTACK Register
          466. 14.11.1.2.466 CSCTI_ITTRIGOUTACK Register
          467. 14.11.1.2.467 CSCTI_ITCHIN Register
          468. 14.11.1.2.468 CSCTI_ITTRIGIN Register
          469. 14.11.1.2.469 CSCTI_ITCTRL Register
          470. 14.11.1.2.470 CSCTI_CLAIMSET Register
          471. 14.11.1.2.471 CSCTI_CLAIMCLR Register
          472. 14.11.1.2.472 CSCTI_LAR Register
          473. 14.11.1.2.473 CSCTI_LSR Register
          474. 14.11.1.2.474 CSCTI_AUTHSTATUS Register
          475. 14.11.1.2.475 CSCTI_DEVID Register
          476. 14.11.1.2.476 CSCTI_DEVTYPE Register
          477. 14.11.1.2.477 CSCTI_PERIPHID4 Register
          478. 14.11.1.2.478 CSCTI_PERIPHID0 Register
          479. 14.11.1.2.479 CSCTI_PERIPHID1 Register
          480. 14.11.1.2.480 CSCTI_PERIPHID2 Register
          481. 14.11.1.2.481 CSCTI_PERIPHID3 Register
          482. 14.11.1.2.482 CSCTI_COMPID0 Register
          483. 14.11.1.2.483 CSCTI_COMPID1 Register
          484. 14.11.1.2.484 CSCTI_COMPID2 Register
          485. 14.11.1.2.485 CSCTI_COMPID3 Register
          486. 14.11.1.2.486 CSCTI_CTICONTROL Register
          487. 14.11.1.2.487 CSCTI_CTIINTACK Register
          488. 14.11.1.2.488 CSCTI_CTIAPPSET Register
          489. 14.11.1.2.489 CSCTI_CTIAPPCLEAR Register
          490. 14.11.1.2.490 CSCTI_CTIAPPPULSE Register
          491. 14.11.1.2.491 CSCTI_CTIINEN0 Register
          492. 14.11.1.2.492 CSCTI_CTIINEN1 Register
          493. 14.11.1.2.493 CSCTI_CTIINEN2 Register
          494. 14.11.1.2.494 CSCTI_CTIINEN3 Register
          495. 14.11.1.2.495 CSCTI_CTIINEN4 Register
          496. 14.11.1.2.496 CSCTI_CTIINEN5 Register
          497. 14.11.1.2.497 CSCTI_CTIINEN6 Register
          498. 14.11.1.2.498 CSCTI_CTIINEN7 Register
          499. 14.11.1.2.499 CSCTI_CTIOUTEN0 Register
          500. 14.11.1.2.500 CSCTI_CTIOUTEN1 Register
          501. 14.11.1.2.501 CSCTI_CTIOUTEN2 Register
          502. 14.11.1.2.502 CSCTI_CTIOUTEN3 Register
          503. 14.11.1.2.503 CSCTI_CTIOUTEN4 Register
          504. 14.11.1.2.504 CSCTI_CTIOUTEN5 Register
          505. 14.11.1.2.505 CSCTI_CTIOUTEN6 Register
          506. 14.11.1.2.506 CSCTI_CTIOUTEN7 Register
          507. 14.11.1.2.507 CSCTI_CTITRIGINSTATUS Register
          508. 14.11.1.2.508 CSCTI_CTITRIGOUTSTATUS Register
          509. 14.11.1.2.509 CSCTI_CTICHINSTATUS Register
          510. 14.11.1.2.510 CSCTI_CTICHOUTSTATUS Register
          511. 14.11.1.2.511 CSCTI_CTIGATE Register
          512. 14.11.1.2.512 CSCTI_ASICCTL Register
          513. 14.11.1.2.513 CSCTI_ITCHINACK Register
          514. 14.11.1.2.514 CSCTI_ITTRIGINACK Register
          515. 14.11.1.2.515 CSCTI_ITCHOUT Register
          516. 14.11.1.2.516 CSCTI_ITTRIGOUT Register
          517. 14.11.1.2.517 CSCTI_ITCHOUTACK Register
          518. 14.11.1.2.518 CSCTI_ITTRIGOUTACK Register
          519. 14.11.1.2.519 CSCTI_ITCHIN Register
          520. 14.11.1.2.520 CSCTI_ITTRIGIN Register
          521. 14.11.1.2.521 CSCTI_ITCTRL Register
          522. 14.11.1.2.522 CSCTI_CLAIMSET Register
          523. 14.11.1.2.523 CSCTI_CLAIMCLR Register
          524. 14.11.1.2.524 CSCTI_LAR Register
          525. 14.11.1.2.525 CSCTI_LSR Register
          526. 14.11.1.2.526 CSCTI_AUTHSTATUS Register
          527. 14.11.1.2.527 CSCTI_DEVID Register
          528. 14.11.1.2.528 CSCTI_DEVTYPE Register
          529. 14.11.1.2.529 CSCTI_PERIPHID4 Register
          530. 14.11.1.2.530 CSCTI_PERIPHID0 Register
          531. 14.11.1.2.531 CSCTI_PERIPHID1 Register
          532. 14.11.1.2.532 CSCTI_PERIPHID2 Register
          533. 14.11.1.2.533 CSCTI_PERIPHID3 Register
          534. 14.11.1.2.534 CSCTI_COMPID0 Register
          535. 14.11.1.2.535 CSCTI_COMPID1 Register
          536. 14.11.1.2.536 CSCTI_COMPID2 Register
          537. 14.11.1.2.537 CSCTI_COMPID3 Register
          538. 14.11.1.2.538 CSCTI_CTICONTROL Register
          539. 14.11.1.2.539 CSCTI_CTIINTACK Register
          540. 14.11.1.2.540 CSCTI_CTIAPPSET Register
          541. 14.11.1.2.541 CSCTI_CTIAPPCLEAR Register
          542. 14.11.1.2.542 CSCTI_CTIAPPPULSE Register
          543. 14.11.1.2.543 CSCTI_CTIINEN0 Register
          544. 14.11.1.2.544 CSCTI_CTIINEN1 Register
          545. 14.11.1.2.545 CSCTI_CTIINEN2 Register
          546. 14.11.1.2.546 CSCTI_CTIINEN3 Register
          547. 14.11.1.2.547 CSCTI_CTIINEN4 Register
          548. 14.11.1.2.548 CSCTI_CTIINEN5 Register
          549. 14.11.1.2.549 CSCTI_CTIINEN6 Register
          550. 14.11.1.2.550 CSCTI_CTIINEN7 Register
          551. 14.11.1.2.551 CSCTI_CTIOUTEN0 Register
          552. 14.11.1.2.552 CSCTI_CTIOUTEN1 Register
          553. 14.11.1.2.553 CSCTI_CTIOUTEN2 Register
          554. 14.11.1.2.554 CSCTI_CTIOUTEN3 Register
          555. 14.11.1.2.555 CSCTI_CTIOUTEN4 Register
          556. 14.11.1.2.556 CSCTI_CTIOUTEN5 Register
          557. 14.11.1.2.557 CSCTI_CTIOUTEN6 Register
          558. 14.11.1.2.558 CSCTI_CTIOUTEN7 Register
          559. 14.11.1.2.559 CSCTI_CTITRIGINSTATUS Register
          560. 14.11.1.2.560 CSCTI_CTITRIGOUTSTATUS Register
          561. 14.11.1.2.561 CSCTI_CTICHINSTATUS Register
          562. 14.11.1.2.562 CSCTI_CTICHOUTSTATUS Register
          563. 14.11.1.2.563 CSCTI_CTIGATE Register
          564. 14.11.1.2.564 CSCTI_ASICCTL Register
          565. 14.11.1.2.565 CSCTI_ITCHINACK Register
          566. 14.11.1.2.566 CSCTI_ITTRIGINACK Register
          567. 14.11.1.2.567 CSCTI_ITCHOUT Register
          568. 14.11.1.2.568 CSCTI_ITTRIGOUT Register
          569. 14.11.1.2.569 CSCTI_ITCHOUTACK Register
          570. 14.11.1.2.570 CSCTI_ITTRIGOUTACK Register
          571. 14.11.1.2.571 CSCTI_ITCHIN Register
          572. 14.11.1.2.572 CSCTI_ITTRIGIN Register
          573. 14.11.1.2.573 CSCTI_ITCTRL Register
          574. 14.11.1.2.574 CSCTI_CLAIMSET Register
          575. 14.11.1.2.575 CSCTI_CLAIMCLR Register
          576. 14.11.1.2.576 CSCTI_LAR Register
          577. 14.11.1.2.577 CSCTI_LSR Register
          578. 14.11.1.2.578 CSCTI_AUTHSTATUS Register
          579. 14.11.1.2.579 CSCTI_DEVID Register
          580. 14.11.1.2.580 CSCTI_DEVTYPE Register
          581. 14.11.1.2.581 CSCTI_PERIPHID4 Register
          582. 14.11.1.2.582 CSCTI_PERIPHID0 Register
          583. 14.11.1.2.583 CSCTI_PERIPHID1 Register
          584. 14.11.1.2.584 CSCTI_PERIPHID2 Register
          585. 14.11.1.2.585 CSCTI_PERIPHID3 Register
          586. 14.11.1.2.586 CSCTI_COMPID0 Register
          587. 14.11.1.2.587 CSCTI_COMPID1 Register
          588. 14.11.1.2.588 CSCTI_COMPID2 Register
          589. 14.11.1.2.589 CSCTI_COMPID3 Register
          590. 14.11.1.2.590 CSCTI_CTICONTROL Register
          591. 14.11.1.2.591 CSCTI_CTIINTACK Register
          592. 14.11.1.2.592 CSCTI_CTIAPPSET Register
          593. 14.11.1.2.593 CSCTI_CTIAPPCLEAR Register
          594. 14.11.1.2.594 CSCTI_CTIAPPPULSE Register
          595. 14.11.1.2.595 CSCTI_CTIINEN0 Register
          596. 14.11.1.2.596 CSCTI_CTIINEN1 Register
          597. 14.11.1.2.597 CSCTI_CTIINEN2 Register
          598. 14.11.1.2.598 CSCTI_CTIINEN3 Register
          599. 14.11.1.2.599 CSCTI_CTIINEN4 Register
          600. 14.11.1.2.600 CSCTI_CTIINEN5 Register
          601. 14.11.1.2.601 CSCTI_CTIINEN6 Register
          602. 14.11.1.2.602 CSCTI_CTIINEN7 Register
          603. 14.11.1.2.603 CSCTI_CTIOUTEN0 Register
          604. 14.11.1.2.604 CSCTI_CTIOUTEN1 Register
          605. 14.11.1.2.605 CSCTI_CTIOUTEN2 Register
          606. 14.11.1.2.606 CSCTI_CTIOUTEN3 Register
          607. 14.11.1.2.607 CSCTI_CTIOUTEN4 Register
          608. 14.11.1.2.608 CSCTI_CTIOUTEN5 Register
          609. 14.11.1.2.609 CSCTI_CTIOUTEN6 Register
          610. 14.11.1.2.610 CSCTI_CTIOUTEN7 Register
          611. 14.11.1.2.611 CSCTI_CTITRIGINSTATUS Register
          612. 14.11.1.2.612 CSCTI_CTITRIGOUTSTATUS Register
          613. 14.11.1.2.613 CSCTI_CTICHINSTATUS Register
          614. 14.11.1.2.614 CSCTI_CTICHOUTSTATUS Register
          615. 14.11.1.2.615 CSCTI_CTIGATE Register
          616. 14.11.1.2.616 CSCTI_ASICCTL Register
          617. 14.11.1.2.617 CSCTI_ITCHINACK Register
          618. 14.11.1.2.618 CSCTI_ITTRIGINACK Register
          619. 14.11.1.2.619 CSCTI_ITCHOUT Register
          620. 14.11.1.2.620 CSCTI_ITTRIGOUT Register
          621. 14.11.1.2.621 CSCTI_ITCHOUTACK Register
          622. 14.11.1.2.622 CSCTI_ITTRIGOUTACK Register
          623. 14.11.1.2.623 CSCTI_ITCHIN Register
          624. 14.11.1.2.624 CSCTI_ITTRIGIN Register
          625. 14.11.1.2.625 CSCTI_ITCTRL Register
          626. 14.11.1.2.626 CSCTI_CLAIMSET Register
          627. 14.11.1.2.627 CSCTI_CLAIMCLR Register
          628. 14.11.1.2.628 CSCTI_LAR Register
          629. 14.11.1.2.629 CSCTI_LSR Register
          630. 14.11.1.2.630 CSCTI_AUTHSTATUS Register
          631. 14.11.1.2.631 CSCTI_DEVID Register
          632. 14.11.1.2.632 CSCTI_DEVTYPE Register
          633. 14.11.1.2.633 CSCTI_PERIPHID4 Register
          634. 14.11.1.2.634 CSCTI_PERIPHID0 Register
          635. 14.11.1.2.635 CSCTI_PERIPHID1 Register
          636. 14.11.1.2.636 CSCTI_PERIPHID2 Register
          637. 14.11.1.2.637 CSCTI_PERIPHID3 Register
          638. 14.11.1.2.638 CSCTI_COMPID0 Register
          639. 14.11.1.2.639 CSCTI_COMPID1 Register
          640. 14.11.1.2.640 CSCTI_COMPID2 Register
          641. 14.11.1.2.641 CSCTI_COMPID3 Register
          642. 14.11.1.2.642 CSCTI_CTICONTROL Register
          643. 14.11.1.2.643 CSCTI_CTIINTACK Register
          644. 14.11.1.2.644 CSCTI_CTIAPPSET Register
          645. 14.11.1.2.645 CSCTI_CTIAPPCLEAR Register
          646. 14.11.1.2.646 CSCTI_CTIAPPPULSE Register
          647. 14.11.1.2.647 CSCTI_CTIINEN0 Register
          648. 14.11.1.2.648 CSCTI_CTIINEN1 Register
          649. 14.11.1.2.649 CSCTI_CTIINEN2 Register
          650. 14.11.1.2.650 CSCTI_CTIINEN3 Register
          651. 14.11.1.2.651 CSCTI_CTIINEN4 Register
          652. 14.11.1.2.652 CSCTI_CTIINEN5 Register
          653. 14.11.1.2.653 CSCTI_CTIINEN6 Register
          654. 14.11.1.2.654 CSCTI_CTIINEN7 Register
          655. 14.11.1.2.655 CSCTI_CTIOUTEN0 Register
          656. 14.11.1.2.656 CSCTI_CTIOUTEN1 Register
          657. 14.11.1.2.657 CSCTI_CTIOUTEN2 Register
          658. 14.11.1.2.658 CSCTI_CTIOUTEN3 Register
          659. 14.11.1.2.659 CSCTI_CTIOUTEN4 Register
          660. 14.11.1.2.660 CSCTI_CTIOUTEN5 Register
          661. 14.11.1.2.661 CSCTI_CTIOUTEN6 Register
          662. 14.11.1.2.662 CSCTI_CTIOUTEN7 Register
          663. 14.11.1.2.663 CSCTI_CTITRIGINSTATUS Register
          664. 14.11.1.2.664 CSCTI_CTITRIGOUTSTATUS Register
          665. 14.11.1.2.665 CSCTI_CTICHINSTATUS Register
          666. 14.11.1.2.666 CSCTI_CTICHOUTSTATUS Register
          667. 14.11.1.2.667 CSCTI_CTIGATE Register
          668. 14.11.1.2.668 CSCTI_ASICCTL Register
          669. 14.11.1.2.669 CSCTI_ITCHINACK Register
          670. 14.11.1.2.670 CSCTI_ITTRIGINACK Register
          671. 14.11.1.2.671 CSCTI_ITCHOUT Register
          672. 14.11.1.2.672 CSCTI_ITTRIGOUT Register
          673. 14.11.1.2.673 CSCTI_ITCHOUTACK Register
          674. 14.11.1.2.674 CSCTI_ITTRIGOUTACK Register
          675. 14.11.1.2.675 CSCTI_ITCHIN Register
          676. 14.11.1.2.676 CSCTI_ITTRIGIN Register
          677. 14.11.1.2.677 CSCTI_ITCTRL Register
          678. 14.11.1.2.678 CSCTI_CLAIMSET Register
          679. 14.11.1.2.679 CSCTI_CLAIMCLR Register
          680. 14.11.1.2.680 CSCTI_LAR Register
          681. 14.11.1.2.681 CSCTI_LSR Register
          682. 14.11.1.2.682 CSCTI_AUTHSTATUS Register
          683. 14.11.1.2.683 CSCTI_DEVID Register
          684. 14.11.1.2.684 CSCTI_DEVTYPE Register
          685. 14.11.1.2.685 CSCTI_PERIPHID4 Register
          686. 14.11.1.2.686 CSCTI_PERIPHID0 Register
          687. 14.11.1.2.687 CSCTI_PERIPHID1 Register
          688. 14.11.1.2.688 CSCTI_PERIPHID2 Register
          689. 14.11.1.2.689 CSCTI_PERIPHID3 Register
          690. 14.11.1.2.690 CSCTI_COMPID0 Register
          691. 14.11.1.2.691 CSCTI_COMPID1 Register
          692. 14.11.1.2.692 CSCTI_COMPID2 Register
          693. 14.11.1.2.693 CSCTI_COMPID3 Register
          694. 14.11.1.2.694 CSCTI_CTICONTROL Register
          695. 14.11.1.2.695 CSCTI_CTIINTACK Register
          696. 14.11.1.2.696 CSCTI_CTIAPPSET Register
          697. 14.11.1.2.697 CSCTI_CTIAPPCLEAR Register
          698. 14.11.1.2.698 CSCTI_CTIAPPPULSE Register
          699. 14.11.1.2.699 CSCTI_CTIINEN0 Register
          700. 14.11.1.2.700 CSCTI_CTIINEN1 Register
          701. 14.11.1.2.701 CSCTI_CTIINEN2 Register
          702. 14.11.1.2.702 CSCTI_CTIINEN3 Register
          703. 14.11.1.2.703 CSCTI_CTIINEN4 Register
          704. 14.11.1.2.704 CSCTI_CTIINEN5 Register
          705. 14.11.1.2.705 CSCTI_CTIINEN6 Register
          706. 14.11.1.2.706 CSCTI_CTIINEN7 Register
          707. 14.11.1.2.707 CSCTI_CTIOUTEN0 Register
          708. 14.11.1.2.708 CSCTI_CTIOUTEN1 Register
          709. 14.11.1.2.709 CSCTI_CTIOUTEN2 Register
          710. 14.11.1.2.710 CSCTI_CTIOUTEN3 Register
          711. 14.11.1.2.711 CSCTI_CTIOUTEN4 Register
          712. 14.11.1.2.712 CSCTI_CTIOUTEN5 Register
          713. 14.11.1.2.713 CSCTI_CTIOUTEN6 Register
          714. 14.11.1.2.714 CSCTI_CTIOUTEN7 Register
          715. 14.11.1.2.715 CSCTI_CTITRIGINSTATUS Register
          716. 14.11.1.2.716 CSCTI_CTITRIGOUTSTATUS Register
          717. 14.11.1.2.717 CSCTI_CTICHINSTATUS Register
          718. 14.11.1.2.718 CSCTI_CTICHOUTSTATUS Register
          719. 14.11.1.2.719 CSCTI_CTIGATE Register
          720. 14.11.1.2.720 CSCTI_ASICCTL Register
          721. 14.11.1.2.721 CSCTI_ITCHINACK Register
          722. 14.11.1.2.722 CSCTI_ITTRIGINACK Register
          723. 14.11.1.2.723 CSCTI_ITCHOUT Register
          724. 14.11.1.2.724 CSCTI_ITTRIGOUT Register
          725. 14.11.1.2.725 CSCTI_ITCHOUTACK Register
          726. 14.11.1.2.726 CSCTI_ITTRIGOUTACK Register
          727. 14.11.1.2.727 CSCTI_ITCHIN Register
          728. 14.11.1.2.728 CSCTI_ITTRIGIN Register
          729. 14.11.1.2.729 CSCTI_ITCTRL Register
          730. 14.11.1.2.730 CSCTI_CLAIMSET Register
          731. 14.11.1.2.731 CSCTI_CLAIMCLR Register
          732. 14.11.1.2.732 CSCTI_LAR Register
          733. 14.11.1.2.733 CSCTI_LSR Register
          734. 14.11.1.2.734 CSCTI_AUTHSTATUS Register
          735. 14.11.1.2.735 CSCTI_DEVID Register
          736. 14.11.1.2.736 CSCTI_DEVTYPE Register
          737. 14.11.1.2.737 CSCTI_PERIPHID4 Register
          738. 14.11.1.2.738 CSCTI_PERIPHID0 Register
          739. 14.11.1.2.739 CSCTI_PERIPHID1 Register
          740. 14.11.1.2.740 CSCTI_PERIPHID2 Register
          741. 14.11.1.2.741 CSCTI_PERIPHID3 Register
          742. 14.11.1.2.742 CSCTI_COMPID0 Register
          743. 14.11.1.2.743 CSCTI_COMPID1 Register
          744. 14.11.1.2.744 CSCTI_COMPID2 Register
          745. 14.11.1.2.745 CSCTI_COMPID3 Register
      2. 14.11.2 DEBUGSS_WRAP Registers
        1. 14.11.2.1   DEBUGSS_WRAP Summary Table
        2. 14.11.2.2   ROM_TABLE_0_0_ROM_ENTRY0 Register
        3. 14.11.2.3   ROM_TABLE_0_0_ROM_ENTRY1 Register
        4. 14.11.2.4   ROM_TABLE_0_0_ROM_ENTRY2 Register
        5. 14.11.2.5   ROM_TABLE_0_0_ROM_MANUAL_ENTRY0 Register
        6. 14.11.2.6   ROM_TABLE_0_0_ROM_MANUAL_ENTRY1 Register
        7. 14.11.2.7   ROM_TABLE_0_0_ROM_MANUAL_ENTRY2 Register
        8. 14.11.2.8   ROM_TABLE_0_0_ROM_MANUAL_ENTRY3 Register
        9. 14.11.2.9   ROM_TABLE_0_0_ROM_MANUAL_ENTRY4 Register
        10. 14.11.2.10  ROM_TABLE_0_0_ROM_MANUAL_ENTRY5 Register
        11. 14.11.2.11  ROM_TABLE_0_0_ROM_MANUAL_ENTRY6 Register
        12. 14.11.2.12  ROM_TABLE_0_0_ROM_MANUAL_ENTRY7 Register
        13. 14.11.2.13  ROM_TABLE_0_0_ROM_MANUAL_ENTRY8 Register
        14. 14.11.2.14  ROM_TABLE_0_0_ROM_MANUAL_ENTRY9 Register
        15. 14.11.2.15  ROM_TABLE_0_0_ROM_MANUAL_ENTRY10 Register
        16. 14.11.2.16  ROM_TABLE_0_0_ROM_MANUAL_ENTRY11 Register
        17. 14.11.2.17  ROM_TABLE_0_0_ROM_MANUAL_ENTRY12 Register
        18. 14.11.2.18  ROM_TABLE_0_0_ROM_MANUAL_ENTRY13 Register
        19. 14.11.2.19  ROM_TABLE_0_0_ROM_MANUAL_ENTRY14 Register
        20. 14.11.2.20  ROM_TABLE_0_0_ROM_MANUAL_ENTRY15 Register
        21. 14.11.2.21  ROM_TABLE_0_0_ROM_MANUAL_ENTRY16 Register
        22. 14.11.2.22  ROM_TABLE_0_0_ROM_MANUAL_ENTRY17 Register
        23. 14.11.2.23  ROM_TABLE_0_0_ROM_MANUAL_ENTRY18 Register
        24. 14.11.2.24  ROM_TABLE_0_0_ROM_MANUAL_ENTRY19 Register
        25. 14.11.2.25  ROM_TABLE_0_0_ROM_MANUAL_ENTRY20 Register
        26. 14.11.2.26  ROM_TABLE_0_0_ROM_MANUAL_ENTRY21 Register
        27. 14.11.2.27  ROM_TABLE_0_0_ROM_MANUAL_ENTRY22 Register
        28. 14.11.2.28  ROM_TABLE_0_0_ROM_MANUAL_ENTRY23 Register
        29. 14.11.2.29  ROM_TABLE_0_0_ROM_MANUAL_ENTRY24 Register
        30. 14.11.2.30  ROM_TABLE_0_0_ROM_MANUAL_ENTRY25 Register
        31. 14.11.2.31  ROM_TABLE_0_0_ROM_MANUAL_ENTRY26 Register
        32. 14.11.2.32  ROM_TABLE_0_0_ROM_MANUAL_ENTRY27 Register
        33. 14.11.2.33  ROM_TABLE_0_0_ROM_MANUAL_ENTRY28 Register
        34. 14.11.2.34  ROM_TABLE_0_0_ROM_MANUAL_ENTRY29 Register
        35. 14.11.2.35  ROM_TABLE_0_0_ROM_MANUAL_ENTRY30 Register
        36. 14.11.2.36  ROM_TABLE_0_0_ROM_MANUAL_ENTRY31 Register
        37. 14.11.2.37  ROM_TABLE_0_0_ROM_MANUAL_ENTRY32 Register
        38. 14.11.2.38  ROM_TABLE_0_0_ROM_MANUAL_ENTRY33 Register
        39. 14.11.2.39  ROM_TABLE_0_0_ROM_MANUAL_ENTRY34 Register
        40. 14.11.2.40  ROM_TABLE_0_0_ROM_MANUAL_ENTRY35 Register
        41. 14.11.2.41  ROM_TABLE_0_0_ROM_MANUAL_ENTRY36 Register
        42. 14.11.2.42  ROM_TABLE_0_0_ROM_MANUAL_ENTRY37 Register
        43. 14.11.2.43  ROM_TABLE_0_0_ROM_MANUAL_ENTRY38 Register
        44. 14.11.2.44  ROM_TABLE_0_0_ROM_MANUAL_ENTRY39 Register
        45. 14.11.2.45  ROM_TABLE_0_0_ROM_MANUAL_ENTRY40 Register
        46. 14.11.2.46  ROM_TABLE_0_0_ROM_MANUAL_ENTRY41 Register
        47. 14.11.2.47  ROM_TABLE_0_0_ROM_MANUAL_ENTRY42 Register
        48. 14.11.2.48  ROM_TABLE_0_0_ROM_MANUAL_ENTRY43 Register
        49. 14.11.2.49  ROM_TABLE_0_0_ROM_MANUAL_ENTRY44 Register
        50. 14.11.2.50  ROM_TABLE_0_0_ROM_MANUAL_ENTRY45 Register
        51. 14.11.2.51  ROM_TABLE_0_0_ROM_MANUAL_ENTRY46 Register
        52. 14.11.2.52  ROM_TABLE_0_0_ROM_MANUAL_ENTRY47 Register
        53. 14.11.2.53  ROM_TABLE_0_0_ROM_MANUAL_ENTRY48 Register
        54. 14.11.2.54  ROM_TABLE_0_0_ROM_MANUAL_ENTRY49 Register
        55. 14.11.2.55  ROM_TABLE_0_0_ROM_MANUAL_ENTRY50 Register
        56. 14.11.2.56  ROM_TABLE_0_0_ROM_MANUAL_ENTRY51 Register
        57. 14.11.2.57  ROM_TABLE_0_0_ROM_MANUAL_ENTRY52 Register
        58. 14.11.2.58  ROM_TABLE_0_0_ROM_MANUAL_ENTRY53 Register
        59. 14.11.2.59  ROM_TABLE_0_0_ROM_MANUAL_ENTRY54 Register
        60. 14.11.2.60  ROM_TABLE_0_0_ROM_MANUAL_ENTRY55 Register
        61. 14.11.2.61  ROM_TABLE_0_0_ROM_MANUAL_ENTRY56 Register
        62. 14.11.2.62  ROM_TABLE_0_0_ROM_MANUAL_ENTRY57 Register
        63. 14.11.2.63  ROM_TABLE_0_0_ROM_MANUAL_ENTRY58 Register
        64. 14.11.2.64  ROM_TABLE_0_0_ROM_MANUAL_ENTRY59 Register
        65. 14.11.2.65  ROM_TABLE_0_0_ROM_MANUAL_ENTRY60 Register
        66. 14.11.2.66  ROM_TABLE_0_0_ROM_MANUAL_ENTRY61 Register
        67. 14.11.2.67  ROM_TABLE_0_0_ROM_MANUAL_ENTRY62 Register
        68. 14.11.2.68  ROM_TABLE_0_0_ROM_MANUAL_ENTRY63 Register
        69. 14.11.2.69  ROM_TABLE_0_0_PERIPHID0 Register
        70. 14.11.2.70  ROM_TABLE_0_0_PERIPHID1 Register
        71. 14.11.2.71  ROM_TABLE_0_0_PERIPHID2 Register
        72. 14.11.2.72  ROM_TABLE_0_0_PERIPHID3 Register
        73. 14.11.2.73  ROM_TABLE_0_0_PERIPHID4 Register
        74. 14.11.2.74  ROM_TABLE_0_0_COMPID0 Register
        75. 14.11.2.75  ROM_TABLE_0_0_COMPID1 Register
        76. 14.11.2.76  ROM_TABLE_0_0_COMPID2 Register
        77. 14.11.2.77  ROM_TABLE_0_0_COMPID3 Register
        78. 14.11.2.78  CFGAP_CFG_0_JTAGID_REG Register
        79. 14.11.2.79  CFGAP_CFG_0_USERID_REG Register
        80. 14.11.2.80  CFGAP_CFG_0_VERSION_REG Register
        81. 14.11.2.81  CFGAP_CFG_0_SYSTEMSTATUS Register
        82. 14.11.2.82  CFGAP_CFG_0_APID_REGISTER Register
        83. 14.11.2.83  APBAP_CFG_0_CSWREG Register
        84. 14.11.2.84  APBAP_CFG_0_TAREG Register
        85. 14.11.2.85  APBAP_CFG_0_DRWREG Register
        86. 14.11.2.86  APBAP_CFG_0_BD0REG Register
        87. 14.11.2.87  APBAP_CFG_0_BD1REG Register
        88. 14.11.2.88  APBAP_CFG_0_BD2REG Register
        89. 14.11.2.89  APBAP_CFG_0_BD3REG Register
        90. 14.11.2.90  APBAP_CFG_0_ROM_REGISTER Register
        91. 14.11.2.91  APBAP_CFG_0_ID_REGISTER Register
        92. 14.11.2.92  AXIAP_CFG_0_CSWREG Register
        93. 14.11.2.93  AXIAP_CFG_0_TAREGL Register
        94. 14.11.2.94  AXIAP_CFG_0_TAREGH Register
        95. 14.11.2.95  AXIAP_CFG_0_DRWREG Register
        96. 14.11.2.96  AXIAP_CFG_0_BD0REG Register
        97. 14.11.2.97  AXIAP_CFG_0_BD1REG Register
        98. 14.11.2.98  AXIAP_CFG_0_BD2REG Register
        99. 14.11.2.99  AXIAP_CFG_0_BD3REG Register
        100. 14.11.2.100 AXIAP_CFG_0_MBT_REGISTER Register
        101. 14.11.2.101 AXIAP_CFG_0_ROM_HI_REGISTER Register
        102. 14.11.2.102 AXIAP_CFG_0_CFG_REGISTER Register
        103. 14.11.2.103 AXIAP_CFG_0_ROM_LO_REGISTER Register
        104. 14.11.2.104 AXIAP_CFG_0_ID_REGISTER Register
        105. 14.11.2.105 PWRAP_CFG_0_CORE_PRECREG0 Register
        106. 14.11.2.106 PWRAP_CFG_0_CORE_PRECREG1 Register
        107. 14.11.2.107 PWRAP_CFG_0_CORE_PRECREG2 Register
        108. 14.11.2.108 PWRAP_CFG_0_CORE_PRECREG3 Register
        109. 14.11.2.109 PWRAP_CFG_0_CORE_PRECREG4 Register
        110. 14.11.2.110 PWRAP_CFG_0_CORE_PRECREG5 Register
        111. 14.11.2.111 PWRAP_CFG_0_CORE_PRECREG6 Register
        112. 14.11.2.112 PWRAP_CFG_0_CORE_PRECREG7 Register
        113. 14.11.2.113 PWRAP_CFG_0_CORE_PRECREG8 Register
        114. 14.11.2.114 PWRAP_CFG_0_CORE_PRECREG9 Register
        115. 14.11.2.115 PWRAP_CFG_0_CORE_PRECREG10 Register
        116. 14.11.2.116 PWRAP_CFG_0_CORE_PRECREG11 Register
        117. 14.11.2.117 PWRAP_CFG_0_CORE_PRECREG12 Register
        118. 14.11.2.118 PWRAP_CFG_0_CORE_PRECREG13 Register
        119. 14.11.2.119 PWRAP_CFG_0_CORE_PRECREG14 Register
        120. 14.11.2.120 PWRAP_CFG_0_CORE_PRECREG15 Register
        121. 14.11.2.121 PWRAP_CFG_0_CORE_PRECREG16 Register
        122. 14.11.2.122 PWRAP_CFG_0_CORE_PRECREG17 Register
        123. 14.11.2.123 PWRAP_CFG_0_CORE_PRECREG18 Register
        124. 14.11.2.124 PWRAP_CFG_0_CORE_PRECREG19 Register
        125. 14.11.2.125 PWRAP_CFG_0_CORE_PRECREG20 Register
        126. 14.11.2.126 PWRAP_CFG_0_CORE_PRECREG21 Register
        127. 14.11.2.127 PWRAP_CFG_0_CORE_PRECREG22 Register
        128. 14.11.2.128 PWRAP_CFG_0_CORE_PRECREG23 Register
        129. 14.11.2.129 PWRAP_CFG_0_CORE_PRECREG24 Register
        130. 14.11.2.130 PWRAP_CFG_0_CORE_PRECREG25 Register
        131. 14.11.2.131 PWRAP_CFG_0_CORE_PRECREG26 Register
        132. 14.11.2.132 PWRAP_CFG_0_CORE_PRECREG27 Register
        133. 14.11.2.133 PWRAP_CFG_0_CORE_PRECREG28 Register
        134. 14.11.2.134 PWRAP_CFG_0_CORE_PRECREG29 Register
        135. 14.11.2.135 PWRAP_CFG_0_CORE_PRECREG30 Register
        136. 14.11.2.136 PWRAP_CFG_0_CORE_PRECREG31 Register
        137. 14.11.2.137 PWRAP_CFG_0_SYS_PRECREG Register
        138. 14.11.2.138 PWRAP_CFG_0_ID_REGISTER Register
        139. 14.11.2.139 PVIEW_CFG_0_PVIEW_STATE0 Register
        140. 14.11.2.140 PVIEW_CFG_0_PVIEW_CAPABILITY Register
        141. 14.11.2.141 PVIEW_CFG_0_ID_REGISTER Register
        142. 14.11.2.142 JTAGAP_CFG_0_CSW Register
        143. 14.11.2.143 JTAGAP_CFG_0_PSEL_REG Register
        144. 14.11.2.144 JTAGAP_CFG_0_PSTA_REG Register
        145. 14.11.2.145 JTAGAP_CFG_0_BYTEFIFO1 Register
        146. 14.11.2.146 JTAGAP_CFG_0_BYTEFIFO2 Register
        147. 14.11.2.147 JTAGAP_CFG_0_BYTEFIFO3 Register
        148. 14.11.2.148 JTAGAP_CFG_0_BYTEFIFO4 Register
        149. 14.11.2.149 JTAGAP_CFG_0_ID_REGISTER Register
        150. 14.11.2.150 SECAP_CFG_0_TXDATA Register
        151. 14.11.2.151 SECAP_CFG_0_TXCTRL Register
        152. 14.11.2.152 SECAP_CFG_0_RXDATA Register
        153. 14.11.2.153 SECAP_CFG_0_RXCTRL Register
        154. 14.11.2.154 CORTEX0_CFG_0_CSWREG Register
        155. 14.11.2.155 CORTEX0_CFG_0_TAREG Register
        156. 14.11.2.156 CORTEX0_CFG_0_DRWREG Register
        157. 14.11.2.157 CORTEX0_CFG_0_BD0REG Register
        158. 14.11.2.158 CORTEX0_CFG_0_BD1REG Register
        159. 14.11.2.159 CORTEX0_CFG_0_BD2REG Register
        160. 14.11.2.160 CORTEX0_CFG_0_BD3REG Register
        161. 14.11.2.161 CORTEX0_CFG_0_ROM_REGISTER Register
        162. 14.11.2.162 CORTEX0_CFG_0_ID_REGISTER Register
        163. 14.11.2.163 CORTEX1_CFG_0_CSWREG Register
        164. 14.11.2.164 CORTEX1_CFG_0_TAREG Register
        165. 14.11.2.165 CORTEX1_CFG_0_DRWREG Register
        166. 14.11.2.166 CORTEX1_CFG_0_BD0REG Register
        167. 14.11.2.167 CORTEX1_CFG_0_BD1REG Register
        168. 14.11.2.168 CORTEX1_CFG_0_BD2REG Register
        169. 14.11.2.169 CORTEX1_CFG_0_BD3REG Register
        170. 14.11.2.170 CORTEX1_CFG_0_ROM_REGISTER Register
        171. 14.11.2.171 CORTEX1_CFG_0_ID_REGISTER Register
        172. 14.11.2.172 CORTEX2_CFG_0_CSWREG Register
        173. 14.11.2.173 CORTEX2_CFG_0_TAREG Register
        174. 14.11.2.174 CORTEX2_CFG_0_DRWREG Register
        175. 14.11.2.175 CORTEX2_CFG_0_BD0REG Register
        176. 14.11.2.176 CORTEX2_CFG_0_BD1REG Register
        177. 14.11.2.177 CORTEX2_CFG_0_BD2REG Register
        178. 14.11.2.178 CORTEX2_CFG_0_BD3REG Register
        179. 14.11.2.179 CORTEX2_CFG_0_ROM_REGISTER Register
        180. 14.11.2.180 CORTEX2_CFG_0_ID_REGISTER Register
        181. 14.11.2.181 CORTEX3_CFG_0_CSWREG Register
        182. 14.11.2.182 CORTEX3_CFG_0_TAREG Register
        183. 14.11.2.183 CORTEX3_CFG_0_DRWREG Register
        184. 14.11.2.184 CORTEX3_CFG_0_BD0REG Register
        185. 14.11.2.185 CORTEX3_CFG_0_BD1REG Register
        186. 14.11.2.186 CORTEX3_CFG_0_BD2REG Register
        187. 14.11.2.187 CORTEX3_CFG_0_BD3REG Register
        188. 14.11.2.188 CORTEX3_CFG_0_ROM_REGISTER Register
        189. 14.11.2.189 CORTEX3_CFG_0_ID_REGISTER Register
        190. 14.11.2.190 CORTEX4_CFG_0_CSWREG Register
        191. 14.11.2.191 CORTEX4_CFG_0_TAREG Register
        192. 14.11.2.192 CORTEX4_CFG_0_DRWREG Register
        193. 14.11.2.193 CORTEX4_CFG_0_BD0REG Register
        194. 14.11.2.194 CORTEX4_CFG_0_BD1REG Register
        195. 14.11.2.195 CORTEX4_CFG_0_BD2REG Register
        196. 14.11.2.196 CORTEX4_CFG_0_BD3REG Register
        197. 14.11.2.197 CORTEX4_CFG_0_ROM_REGISTER Register
        198. 14.11.2.198 CORTEX4_CFG_0_ID_REGISTER Register
        199. 14.11.2.199 CORTEX5_CFG_0_CSWREG Register
        200. 14.11.2.200 CORTEX5_CFG_0_TAREG Register
        201. 14.11.2.201 CORTEX5_CFG_0_DRWREG Register
        202. 14.11.2.202 CORTEX5_CFG_0_BD0REG Register
        203. 14.11.2.203 CORTEX5_CFG_0_BD1REG Register
        204. 14.11.2.204 CORTEX5_CFG_0_BD2REG Register
        205. 14.11.2.205 CORTEX5_CFG_0_BD3REG Register
        206. 14.11.2.206 CORTEX5_CFG_0_ROM_REGISTER Register
        207. 14.11.2.207 CORTEX5_CFG_0_ID_REGISTER Register
        208. 14.11.2.208 CORTEX6_CFG_0_CSWREG Register
        209. 14.11.2.209 CORTEX6_CFG_0_TAREG Register
        210. 14.11.2.210 CORTEX6_CFG_0_DRWREG Register
        211. 14.11.2.211 CORTEX6_CFG_0_BD0REG Register
        212. 14.11.2.212 CORTEX6_CFG_0_BD1REG Register
        213. 14.11.2.213 CORTEX6_CFG_0_BD2REG Register
        214. 14.11.2.214 CORTEX6_CFG_0_BD3REG Register
        215. 14.11.2.215 CORTEX6_CFG_0_ROM_REGISTER Register
        216. 14.11.2.216 CORTEX6_CFG_0_ID_REGISTER Register
        217. 14.11.2.217 CORTEX7_CFG_0_CSWREG Register
        218. 14.11.2.218 CORTEX7_CFG_0_TAREG Register
        219. 14.11.2.219 CORTEX7_CFG_0_DRWREG Register
        220. 14.11.2.220 CORTEX7_CFG_0_BD0REG Register
        221. 14.11.2.221 CORTEX7_CFG_0_BD1REG Register
        222. 14.11.2.222 CORTEX7_CFG_0_BD2REG Register
        223. 14.11.2.223 CORTEX7_CFG_0_BD3REG Register
        224. 14.11.2.224 CORTEX7_CFG_0_ROM_REGISTER Register
        225. 14.11.2.225 CORTEX7_CFG_0_ID_REGISTER Register
        226. 14.11.2.226 CORTEX8_CFG_0_CSWREG Register
        227. 14.11.2.227 CORTEX8_CFG_0_TAREG Register
        228. 14.11.2.228 CORTEX8_CFG_0_DRWREG Register
        229. 14.11.2.229 CORTEX8_CFG_0_BD0REG Register
        230. 14.11.2.230 CORTEX8_CFG_0_BD1REG Register
        231. 14.11.2.231 CORTEX8_CFG_0_BD2REG Register
        232. 14.11.2.232 CORTEX8_CFG_0_BD3REG Register
        233. 14.11.2.233 CORTEX8_CFG_0_ROM_REGISTER Register
        234. 14.11.2.234 CORTEX8_CFG_0_ID_REGISTER Register
        235. 14.11.2.235 ROM_TABLE_1_0_ROM_ENTRY0 Register
        236. 14.11.2.236 ROM_TABLE_1_0_ROM_ENTRY1 Register
        237. 14.11.2.237 ROM_TABLE_1_0_ROM_ENTRY2 Register
        238. 14.11.2.238 ROM_TABLE_1_0_ROM_ENTRY3 Register
        239. 14.11.2.239 ROM_TABLE_1_0_ROM_ENTRY4 Register
        240. 14.11.2.240 ROM_TABLE_1_0_ROM_ENTRY5 Register
        241. 14.11.2.241 ROM_TABLE_1_0_COMPUTE_CLUSTER0 Register
        242. 14.11.2.242 ROM_TABLE_1_0_COMPUTE_CLUSTER1 Register
        243. 14.11.2.243 ROM_TABLE_1_0_COMPUTE_CLUSTER2 Register
        244. 14.11.2.244 ROM_TABLE_1_0_DEBUG_CELL0 Register
        245. 14.11.2.245 ROM_TABLE_1_0_DEBUG_CELL1 Register
        246. 14.11.2.246 ROM_TABLE_1_0_DEBUG_CELL2 Register
        247. 14.11.2.247 ROM_TABLE_1_0_DEBUG_CELL3 Register
        248. 14.11.2.248 ROM_TABLE_1_0_DEBUG_CELL4 Register
        249. 14.11.2.249 ROM_TABLE_1_0_DEBUG_CELL5 Register
        250. 14.11.2.250 ROM_TABLE_1_0_DEBUG_CELL6 Register
        251. 14.11.2.251 ROM_TABLE_1_0_DEBUG_CELL7 Register
        252. 14.11.2.252 ROM_TABLE_1_0_DEBUG_CELL8 Register
        253. 14.11.2.253 ROM_TABLE_1_0_DEBUG_CELL9 Register
        254. 14.11.2.254 ROM_TABLE_1_0_DEBUG_CELL10 Register
        255. 14.11.2.255 ROM_TABLE_1_0_DEBUG_CELL11 Register
        256. 14.11.2.256 ROM_TABLE_1_0_EXTCSCOMP0 Register
        257. 14.11.2.257 ROM_TABLE_1_0_EXTCSCOMP1 Register
        258. 14.11.2.258 ROM_TABLE_1_0_EXTCSCOMP2 Register
        259. 14.11.2.259 ROM_TABLE_1_0_EXTCSCOMP3 Register
        260. 14.11.2.260 ROM_TABLE_1_0_EXTCSCOMP4 Register
        261. 14.11.2.261 ROM_TABLE_1_0_EXTCSCOMP5 Register
        262. 14.11.2.262 ROM_TABLE_1_0_EXTCSCOMP6 Register
        263. 14.11.2.263 ROM_TABLE_1_0_EXTCSCOMP7 Register
        264. 14.11.2.264 ROM_TABLE_1_0_EXTCSCOMP8 Register
        265. 14.11.2.265 ROM_TABLE_1_0_EXTCSCOMP9 Register
        266. 14.11.2.266 ROM_TABLE_1_0_EXTCSCOMP10 Register
        267. 14.11.2.267 ROM_TABLE_1_0_EXTCSCOMP11 Register
        268. 14.11.2.268 CSCTI_CTICONTROL Register
        269. 14.11.2.269 CSCTI_CTIINTACK Register
        270. 14.11.2.270 CSCTI_CTIAPPSET Register
        271. 14.11.2.271 CSCTI_CTIAPPCLR Register
        272. 14.11.2.272 CSCTI_CTIAPPPULSE Register
        273. 14.11.2.273 CSCTI_CTIINEN0 Register
        274. 14.11.2.274 CSCTI_CTIINEN1 Register
        275. 14.11.2.275 CSCTI_CTIINEN2 Register
        276. 14.11.2.276 CSCTI_CTIINEN3 Register
        277. 14.11.2.277 CSCTI_CTIINEN4 Register
        278. 14.11.2.278 CSCTI_CTIINEN5 Register
        279. 14.11.2.279 CSCTI_CTIINEN6 Register
        280. 14.11.2.280 CSCTI_CTIINEN7 Register
        281. 14.11.2.281 CSCTI_CTIOUTEN0 Register
        282. 14.11.2.282 CSCTI_CTIOUTEN1 Register
        283. 14.11.2.283 CSCTI_CTIOUTEN2 Register
        284. 14.11.2.284 CSCTI_CTIOUTEN3 Register
        285. 14.11.2.285 CSCTI_CTIOUTEN4 Register
        286. 14.11.2.286 CSCTI_CTIOUTEN5 Register
        287. 14.11.2.287 CSCTI_CTIOUTEN6 Register
        288. 14.11.2.288 CSCTI_CTIOUTEN7 Register
        289. 14.11.2.289 CSCTI_CTITRIGINSTATUS Register
        290. 14.11.2.290 CSCTI_CTITRIGOUTSTATUS Register
        291. 14.11.2.291 CSCTI_CTICHINSTATUS Register
        292. 14.11.2.292 CSCTI_CTICHOUTSTATUS Register
        293. 14.11.2.293 CSCTI_CTIGATE Register
        294. 14.11.2.294 CSCTI_ASICCTL Register
        295. 14.11.2.295 CSCTI_ITCHINACK Register
        296. 14.11.2.296 CSCTI_ITTRIGINACK Register
        297. 14.11.2.297 CSCTI_ITCHOUT Register
        298. 14.11.2.298 CSCTI_ITTRIGOUT Register
        299. 14.11.2.299 CSCTI_ITCHOUTACK Register
        300. 14.11.2.300 CSCTI_ITTRIGOUTACK Register
        301. 14.11.2.301 CSCTI_ITCHIN Register
        302. 14.11.2.302 CSCTI_ITTRIGIN Register
        303. 14.11.2.303 CSCTI_ITCTRL Register
        304. 14.11.2.304 CSCTI_CLAIMSET Register
        305. 14.11.2.305 CSCTI_CLAIMCLR Register
        306. 14.11.2.306 CSCTI_LOCKACCESS Register
        307. 14.11.2.307 CSCTI_LOCKSTATUS Register
        308. 14.11.2.308 CSCTI_AUTHSTATUS Register
        309. 14.11.2.309 CSCTI_DEVID Register
        310. 14.11.2.310 CSCTI_DEVTYPE Register
        311. 14.11.2.311 CSCTI_PERIPHID4 Register
        312. 14.11.2.312 CSCTI_PERIPHID0 Register
        313. 14.11.2.313 CSCTI_PERIPHID1 Register
        314. 14.11.2.314 CSCTI_PERIPHID2 Register
        315. 14.11.2.315 CSCTI_PERIPHID3 Register
        316. 14.11.2.316 CSCTI_COMPONID0 Register
        317. 14.11.2.317 CSCTI_COMPONID1 Register
        318. 14.11.2.318 CSCTI_COMPONID2 Register
        319. 14.11.2.319 CSCTI_COMPONID3 Register
        320. 14.11.2.320 DRM_CFG_0_PERIPH_ID Register
        321. 14.11.2.321 DRM_CFG_0_VERSION Register
        322. 14.11.2.322 DRM_CFG_0_CAPABILITY Register
        323. 14.11.2.323 DRM_CFG_0_TRACE_CTRL Register
        324. 14.11.2.324 DRM_CFG_0_VBUSM_CTRL Register
        325. 14.11.2.325 DRM_CFG_0_DAP_TIMEOUT Register
        326. 14.11.2.326 DRM_CFG_0_CONFIG Register
        327. 14.11.2.327 DRM_CFG_0_EMUTRIGEN Register
        328. 14.11.2.328 DRM_CFG_0_BINVALLO Register
        329. 14.11.2.329 DRM_CFG_0_BINVALHI Register
        330. 14.11.2.330 DRM_CFG_0_SUSPEND_REG0 Register
        331. 14.11.2.331 DRM_CFG_0_SUSPEND_REG1 Register
        332. 14.11.2.332 DRM_CFG_0_SUSPEND_REG2 Register
        333. 14.11.2.333 DRM_CFG_0_SUSPEND_REG3 Register
        334. 14.11.2.334 DRM_CFG_0_SUSPEND_REG4 Register
        335. 14.11.2.335 DRM_CFG_0_SUSPEND_REG5 Register
        336. 14.11.2.336 DRM_CFG_0_SUSPEND_REG6 Register
        337. 14.11.2.337 DRM_CFG_0_SUSPEND_REG7 Register
        338. 14.11.2.338 DRM_CFG_0_SUSPEND_REG8 Register
        339. 14.11.2.339 DRM_CFG_0_SUSPEND_REG9 Register
        340. 14.11.2.340 DRM_CFG_0_SUSPEND_REG10 Register
        341. 14.11.2.341 DRM_CFG_0_SUSPEND_REG11 Register
        342. 14.11.2.342 DRM_CFG_0_SUSPEND_REG12 Register
        343. 14.11.2.343 DRM_CFG_0_SUSPEND_REG13 Register
        344. 14.11.2.344 DRM_CFG_0_SUSPEND_REG14 Register
        345. 14.11.2.345 DRM_CFG_0_SUSPEND_REG15 Register
        346. 14.11.2.346 DRM_CFG_0_SUSPEND_REG16 Register
        347. 14.11.2.347 DRM_CFG_0_SUSPEND_REG17 Register
        348. 14.11.2.348 DRM_CFG_0_SUSPEND_REG18 Register
        349. 14.11.2.349 DRM_CFG_0_SUSPEND_REG19 Register
        350. 14.11.2.350 DRM_CFG_0_SUSPEND_REG20 Register
        351. 14.11.2.351 DRM_CFG_0_SUSPEND_REG21 Register
        352. 14.11.2.352 DRM_CFG_0_SUSPEND_REG22 Register
        353. 14.11.2.353 DRM_CFG_0_SUSPEND_REG23 Register
        354. 14.11.2.354 DRM_CFG_0_SUSPEND_REG24 Register
        355. 14.11.2.355 DRM_CFG_0_SUSPEND_REG25 Register
        356. 14.11.2.356 DRM_CFG_0_SUSPEND_REG26 Register
        357. 14.11.2.357 DRM_CFG_0_SUSPEND_REG27 Register
        358. 14.11.2.358 DRM_CFG_0_SUSPEND_REG28 Register
        359. 14.11.2.359 DRM_CFG_0_SUSPEND_REG29 Register
        360. 14.11.2.360 DRM_CFG_0_SUSPEND_REG30 Register
        361. 14.11.2.361 DRM_CFG_0_SUSPEND_REG31 Register
        362. 14.11.2.362 CSTPIU_CFG_0_SUPPORTSIZE Register
        363. 14.11.2.363 CSTPIU_CFG_0_CURPORTSIZE Register
        364. 14.11.2.364 CSTPIU_CFG_0_TRIGMODEREG Register
        365. 14.11.2.365 CSTPIU_CFG_0_TRIGCTRREG Register
        366. 14.11.2.366 CSTPIU_CFG_0_TRIGMPYREG Register
        367. 14.11.2.367 CSTPIU_CFG_0_SUPTESTPAT Register
        368. 14.11.2.368 CSTPIU_CFG_0_CURTESTPAT Register
        369. 14.11.2.369 CSTPIU_CFG_0_TESTPATCNT Register
        370. 14.11.2.370 CSTPIU_CFG_0_FORMFLUSHSTAT Register
        371. 14.11.2.371 CSTPIU_CFG_0_FORMFLUSHCTL Register
        372. 14.11.2.372 CSTPIU_CFG_0_FORMSYNCCTR Register
        373. 14.11.2.373 CSTPIU_CFG_0_EXTCTLIN Register
        374. 14.11.2.374 CSTPIU_CFG_0_EXTCTLOUT Register
        375. 14.11.2.375 CSTPIU_CFG_0_ITTRFLINACK Register
        376. 14.11.2.376 CSTPIU_CFG_0_ITTRFLIN Register
        377. 14.11.2.377 CSTPIU_CFG_0_ITATBDATA0 Register
        378. 14.11.2.378 CSTPIU_CFG_0_ITATBCTR2 Register
        379. 14.11.2.379 CSTPIU_CFG_0_ITATBCTR1 Register
        380. 14.11.2.380 CSTPIU_CFG_0_ITATBCTR0 Register
        381. 14.11.2.381 CSTPIU_CFG_0_INTCTRL Register
        382. 14.11.2.382 CSTPIU_CFG_0_CTSET Register
        383. 14.11.2.383 CSTPIU_CFG_0_CTCLR Register
        384. 14.11.2.384 CSTPIU_CFG_0_LAREG Register
        385. 14.11.2.385 CSTPIU_CFG_0_LSREG Register
        386. 14.11.2.386 CSTPIU_CFG_0_AUTHST Register
        387. 14.11.2.387 CSTPIU_CFG_0_DEVID Register
        388. 14.11.2.388 CSTPIU_CFG_0_DEVTYPEID Register
        389. 14.11.2.389 CSTPIU_CFG_0_PERID4 Register
        390. 14.11.2.390 CSTPIU_CFG_0_PERID0 Register
        391. 14.11.2.391 CSTPIU_CFG_0_PERID1 Register
        392. 14.11.2.392 CSTPIU_CFG_0_PERID2 Register
        393. 14.11.2.393 CSTPIU_CFG_0_PERID3 Register
        394. 14.11.2.394 CSTPIU_CFG_0_COMPID0 Register
        395. 14.11.2.395 CSTPIU_CFG_0_COMPID1 Register
        396. 14.11.2.396 CSTPIU_CFG_0_COMPID2 Register
        397. 14.11.2.397 CSTPIU_CFG_0_COMPID3 Register
        398. 14.11.2.398 CTF_CFG_0_CSTFCTLREG Register
        399. 14.11.2.399 CTF_CFG_0_PRIORCTLREG Register
        400. 14.11.2.400 CTF_CFG_0_ITATBDATA0 Register
        401. 14.11.2.401 CTF_CFG_0_ITATBCTR2 Register
        402. 14.11.2.402 CTF_CFG_0_ITATBCTR1 Register
        403. 14.11.2.403 CTF_CFG_0_ITATBCTR0 Register
        404. 14.11.2.404 CTF_CFG_0_INTCTRL Register
        405. 14.11.2.405 CTF_CFG_0_CTSET Register
        406. 14.11.2.406 CTF_CFG_0_CTCLR Register
        407. 14.11.2.407 CTF_CFG_0_LAREG Register
        408. 14.11.2.408 CTF_CFG_0_LSREG Register
        409. 14.11.2.409 CTF_CFG_0_AUTHST Register
        410. 14.11.2.410 CTF_CFG_0_DEVID Register
        411. 14.11.2.411 CTF_CFG_0_DEVTYPEID Register
        412. 14.11.2.412 CTF_CFG_0_PERID4 Register
        413. 14.11.2.413 CTF_CFG_0_PERID5 Register
        414. 14.11.2.414 CTF_CFG_0_PERID6 Register
        415. 14.11.2.415 CTF_CFG_0_PERID7 Register
        416. 14.11.2.416 CTF_CFG_0_PERID0 Register
        417. 14.11.2.417 CTF_CFG_0_PERID1 Register
        418. 14.11.2.418 CTF_CFG_0_PERID2 Register
        419. 14.11.2.419 CTF_CFG_0_PERID3 Register
        420. 14.11.2.420 CTF_CFG_0_COMPID0 Register
        421. 14.11.2.421 CTF_CFG_0_COMPID1 Register
        422. 14.11.2.422 CTF_CFG_0_COMPID2 Register
        423. 14.11.2.423 CTF_CFG_0_COMPID3 Register
        424. 14.11.2.424 ROM_TABLE_0_1_ROM_ENTRY0 Register
        425. 14.11.2.425 ROM_TABLE_0_1_ROM_ENTRY1 Register
        426. 14.11.2.426 ROM_TABLE_0_1_ROM_ENTRY2 Register
        427. 14.11.2.427 ROM_TABLE_0_1_ROM_MANUAL_ENTRY0 Register
        428. 14.11.2.428 ROM_TABLE_0_1_ROM_MANUAL_ENTRY1 Register
        429. 14.11.2.429 ROM_TABLE_0_1_ROM_MANUAL_ENTRY2 Register
        430. 14.11.2.430 ROM_TABLE_0_1_ROM_MANUAL_ENTRY3 Register
        431. 14.11.2.431 ROM_TABLE_0_1_ROM_MANUAL_ENTRY4 Register
        432. 14.11.2.432 ROM_TABLE_0_1_ROM_MANUAL_ENTRY5 Register
        433. 14.11.2.433 ROM_TABLE_0_1_ROM_MANUAL_ENTRY6 Register
        434. 14.11.2.434 ROM_TABLE_0_1_ROM_MANUAL_ENTRY7 Register
        435. 14.11.2.435 ROM_TABLE_0_1_ROM_MANUAL_ENTRY8 Register
        436. 14.11.2.436 ROM_TABLE_0_1_ROM_MANUAL_ENTRY9 Register
        437. 14.11.2.437 ROM_TABLE_0_1_ROM_MANUAL_ENTRY10 Register
        438. 14.11.2.438 ROM_TABLE_0_1_ROM_MANUAL_ENTRY11 Register
        439. 14.11.2.439 ROM_TABLE_0_1_ROM_MANUAL_ENTRY12 Register
        440. 14.11.2.440 ROM_TABLE_0_1_ROM_MANUAL_ENTRY13 Register
        441. 14.11.2.441 ROM_TABLE_0_1_ROM_MANUAL_ENTRY14 Register
        442. 14.11.2.442 ROM_TABLE_0_1_ROM_MANUAL_ENTRY15 Register
        443. 14.11.2.443 ROM_TABLE_0_1_ROM_MANUAL_ENTRY16 Register
        444. 14.11.2.444 ROM_TABLE_0_1_ROM_MANUAL_ENTRY17 Register
        445. 14.11.2.445 ROM_TABLE_0_1_ROM_MANUAL_ENTRY18 Register
        446. 14.11.2.446 ROM_TABLE_0_1_ROM_MANUAL_ENTRY19 Register
        447. 14.11.2.447 ROM_TABLE_0_1_ROM_MANUAL_ENTRY20 Register
        448. 14.11.2.448 ROM_TABLE_0_1_ROM_MANUAL_ENTRY21 Register
        449. 14.11.2.449 ROM_TABLE_0_1_ROM_MANUAL_ENTRY22 Register
        450. 14.11.2.450 ROM_TABLE_0_1_ROM_MANUAL_ENTRY23 Register
        451. 14.11.2.451 ROM_TABLE_0_1_ROM_MANUAL_ENTRY24 Register
        452. 14.11.2.452 ROM_TABLE_0_1_ROM_MANUAL_ENTRY25 Register
        453. 14.11.2.453 ROM_TABLE_0_1_ROM_MANUAL_ENTRY26 Register
        454. 14.11.2.454 ROM_TABLE_0_1_ROM_MANUAL_ENTRY27 Register
        455. 14.11.2.455 ROM_TABLE_0_1_ROM_MANUAL_ENTRY28 Register
        456. 14.11.2.456 ROM_TABLE_0_1_ROM_MANUAL_ENTRY29 Register
        457. 14.11.2.457 ROM_TABLE_0_1_ROM_MANUAL_ENTRY30 Register
        458. 14.11.2.458 ROM_TABLE_0_1_ROM_MANUAL_ENTRY31 Register
        459. 14.11.2.459 ROM_TABLE_0_1_ROM_MANUAL_ENTRY32 Register
        460. 14.11.2.460 ROM_TABLE_0_1_ROM_MANUAL_ENTRY33 Register
        461. 14.11.2.461 ROM_TABLE_0_1_ROM_MANUAL_ENTRY34 Register
        462. 14.11.2.462 ROM_TABLE_0_1_ROM_MANUAL_ENTRY35 Register
        463. 14.11.2.463 ROM_TABLE_0_1_ROM_MANUAL_ENTRY36 Register
        464. 14.11.2.464 ROM_TABLE_0_1_ROM_MANUAL_ENTRY37 Register
        465. 14.11.2.465 ROM_TABLE_0_1_ROM_MANUAL_ENTRY38 Register
        466. 14.11.2.466 ROM_TABLE_0_1_ROM_MANUAL_ENTRY39 Register
        467. 14.11.2.467 ROM_TABLE_0_1_ROM_MANUAL_ENTRY40 Register
        468. 14.11.2.468 ROM_TABLE_0_1_ROM_MANUAL_ENTRY41 Register
        469. 14.11.2.469 ROM_TABLE_0_1_ROM_MANUAL_ENTRY42 Register
        470. 14.11.2.470 ROM_TABLE_0_1_ROM_MANUAL_ENTRY43 Register
        471. 14.11.2.471 ROM_TABLE_0_1_ROM_MANUAL_ENTRY44 Register
        472. 14.11.2.472 ROM_TABLE_0_1_ROM_MANUAL_ENTRY45 Register
        473. 14.11.2.473 ROM_TABLE_0_1_ROM_MANUAL_ENTRY46 Register
        474. 14.11.2.474 ROM_TABLE_0_1_ROM_MANUAL_ENTRY47 Register
        475. 14.11.2.475 ROM_TABLE_0_1_ROM_MANUAL_ENTRY48 Register
        476. 14.11.2.476 ROM_TABLE_0_1_ROM_MANUAL_ENTRY49 Register
        477. 14.11.2.477 ROM_TABLE_0_1_ROM_MANUAL_ENTRY50 Register
        478. 14.11.2.478 ROM_TABLE_0_1_ROM_MANUAL_ENTRY51 Register
        479. 14.11.2.479 ROM_TABLE_0_1_ROM_MANUAL_ENTRY52 Register
        480. 14.11.2.480 ROM_TABLE_0_1_ROM_MANUAL_ENTRY53 Register
        481. 14.11.2.481 ROM_TABLE_0_1_ROM_MANUAL_ENTRY54 Register
        482. 14.11.2.482 ROM_TABLE_0_1_ROM_MANUAL_ENTRY55 Register
        483. 14.11.2.483 ROM_TABLE_0_1_ROM_MANUAL_ENTRY56 Register
        484. 14.11.2.484 ROM_TABLE_0_1_ROM_MANUAL_ENTRY57 Register
        485. 14.11.2.485 ROM_TABLE_0_1_ROM_MANUAL_ENTRY58 Register
        486. 14.11.2.486 ROM_TABLE_0_1_ROM_MANUAL_ENTRY59 Register
        487. 14.11.2.487 ROM_TABLE_0_1_ROM_MANUAL_ENTRY60 Register
        488. 14.11.2.488 ROM_TABLE_0_1_ROM_MANUAL_ENTRY61 Register
        489. 14.11.2.489 ROM_TABLE_0_1_ROM_MANUAL_ENTRY62 Register
        490. 14.11.2.490 ROM_TABLE_0_1_ROM_MANUAL_ENTRY63 Register
        491. 14.11.2.491 ROM_TABLE_0_1_PERIPHID0 Register
        492. 14.11.2.492 ROM_TABLE_0_1_PERIPHID1 Register
        493. 14.11.2.493 ROM_TABLE_0_1_PERIPHID2 Register
        494. 14.11.2.494 ROM_TABLE_0_1_PERIPHID3 Register
        495. 14.11.2.495 ROM_TABLE_0_1_PERIPHID4 Register
        496. 14.11.2.496 ROM_TABLE_0_1_COMPID0 Register
        497. 14.11.2.497 ROM_TABLE_0_1_COMPID1 Register
        498. 14.11.2.498 ROM_TABLE_0_1_COMPID2 Register
        499. 14.11.2.499 ROM_TABLE_0_1_COMPID3 Register
        500. 14.11.2.500 CFGAP_CFG_1_JTAGID_REG Register
        501. 14.11.2.501 CFGAP_CFG_1_USERID_REG Register
        502. 14.11.2.502 CFGAP_CFG_1_VERSION_REG Register
        503. 14.11.2.503 CFGAP_CFG_1_SYSTEMSTATUS Register
        504. 14.11.2.504 CFGAP_CFG_1_APID_REGISTER Register
        505. 14.11.2.505 APBAP_CFG_1_CSWREG Register
        506. 14.11.2.506 APBAP_CFG_1_TAREG Register
        507. 14.11.2.507 APBAP_CFG_1_DRWREG Register
        508. 14.11.2.508 APBAP_CFG_1_BD0REG Register
        509. 14.11.2.509 APBAP_CFG_1_BD1REG Register
        510. 14.11.2.510 APBAP_CFG_1_BD2REG Register
        511. 14.11.2.511 APBAP_CFG_1_BD3REG Register
        512. 14.11.2.512 APBAP_CFG_1_ROM_REGISTER Register
        513. 14.11.2.513 APBAP_CFG_1_ID_REGISTER Register
        514. 14.11.2.514 AXIAP_CFG_1_CSWREG Register
        515. 14.11.2.515 AXIAP_CFG_1_TAREGL Register
        516. 14.11.2.516 AXIAP_CFG_1_TAREGH Register
        517. 14.11.2.517 AXIAP_CFG_1_DRWREG Register
        518. 14.11.2.518 AXIAP_CFG_1_BD0REG Register
        519. 14.11.2.519 AXIAP_CFG_1_BD1REG Register
        520. 14.11.2.520 AXIAP_CFG_1_BD2REG Register
        521. 14.11.2.521 AXIAP_CFG_1_BD3REG Register
        522. 14.11.2.522 AXIAP_CFG_1_MBT_REGISTER Register
        523. 14.11.2.523 AXIAP_CFG_1_ROM_HI_REGISTER Register
        524. 14.11.2.524 AXIAP_CFG_1_CFG_REGISTER Register
        525. 14.11.2.525 AXIAP_CFG_1_ROM_LO_REGISTER Register
        526. 14.11.2.526 AXIAP_CFG_1_ID_REGISTER Register
        527. 14.11.2.527 PWRAP_CFG_1_CORE_PRECREG0 Register
        528. 14.11.2.528 PWRAP_CFG_1_CORE_PRECREG1 Register
        529. 14.11.2.529 PWRAP_CFG_1_CORE_PRECREG2 Register
        530. 14.11.2.530 PWRAP_CFG_1_CORE_PRECREG3 Register
        531. 14.11.2.531 PWRAP_CFG_1_CORE_PRECREG4 Register
        532. 14.11.2.532 PWRAP_CFG_1_CORE_PRECREG5 Register
        533. 14.11.2.533 PWRAP_CFG_1_CORE_PRECREG6 Register
        534. 14.11.2.534 PWRAP_CFG_1_CORE_PRECREG7 Register
        535. 14.11.2.535 PWRAP_CFG_1_CORE_PRECREG8 Register
        536. 14.11.2.536 PWRAP_CFG_1_CORE_PRECREG9 Register
        537. 14.11.2.537 PWRAP_CFG_1_CORE_PRECREG10 Register
        538. 14.11.2.538 PWRAP_CFG_1_CORE_PRECREG11 Register
        539. 14.11.2.539 PWRAP_CFG_1_CORE_PRECREG12 Register
        540. 14.11.2.540 PWRAP_CFG_1_CORE_PRECREG13 Register
        541. 14.11.2.541 PWRAP_CFG_1_CORE_PRECREG14 Register
        542. 14.11.2.542 PWRAP_CFG_1_CORE_PRECREG15 Register
        543. 14.11.2.543 PWRAP_CFG_1_CORE_PRECREG16 Register
        544. 14.11.2.544 PWRAP_CFG_1_CORE_PRECREG17 Register
        545. 14.11.2.545 PWRAP_CFG_1_CORE_PRECREG18 Register
        546. 14.11.2.546 PWRAP_CFG_1_CORE_PRECREG19 Register
        547. 14.11.2.547 PWRAP_CFG_1_CORE_PRECREG20 Register
        548. 14.11.2.548 PWRAP_CFG_1_CORE_PRECREG21 Register
        549. 14.11.2.549 PWRAP_CFG_1_CORE_PRECREG22 Register
        550. 14.11.2.550 PWRAP_CFG_1_CORE_PRECREG23 Register
        551. 14.11.2.551 PWRAP_CFG_1_CORE_PRECREG24 Register
        552. 14.11.2.552 PWRAP_CFG_1_CORE_PRECREG25 Register
        553. 14.11.2.553 PWRAP_CFG_1_CORE_PRECREG26 Register
        554. 14.11.2.554 PWRAP_CFG_1_CORE_PRECREG27 Register
        555. 14.11.2.555 PWRAP_CFG_1_CORE_PRECREG28 Register
        556. 14.11.2.556 PWRAP_CFG_1_CORE_PRECREG29 Register
        557. 14.11.2.557 PWRAP_CFG_1_CORE_PRECREG30 Register
        558. 14.11.2.558 PWRAP_CFG_1_CORE_PRECREG31 Register
        559. 14.11.2.559 PWRAP_CFG_1_SYS_PRECREG Register
        560. 14.11.2.560 PWRAP_CFG_1_ID_REGISTER Register
        561. 14.11.2.561 PVIEW_CFG_1_PVIEW_STATE0 Register
        562. 14.11.2.562 PVIEW_CFG_1_PVIEW_CAPABILITY Register
        563. 14.11.2.563 PVIEW_CFG_1_ID_REGISTER Register
        564. 14.11.2.564 JTAGAP_CFG_1_CSW Register
        565. 14.11.2.565 JTAGAP_CFG_1_PSEL_REG Register
        566. 14.11.2.566 JTAGAP_CFG_1_PSTA_REG Register
        567. 14.11.2.567 JTAGAP_CFG_1_BYTEFIFO1 Register
        568. 14.11.2.568 JTAGAP_CFG_1_BYTEFIFO2 Register
        569. 14.11.2.569 JTAGAP_CFG_1_BYTEFIFO3 Register
        570. 14.11.2.570 JTAGAP_CFG_1_BYTEFIFO4 Register
        571. 14.11.2.571 JTAGAP_CFG_1_ID_REGISTER Register
        572. 14.11.2.572 SECAP_CFG_1_TXDATA Register
        573. 14.11.2.573 SECAP_CFG_1_TXCTRL Register
        574. 14.11.2.574 SECAP_CFG_1_RXDATA Register
        575. 14.11.2.575 SECAP_CFG_1_RXCTRL Register
        576. 14.11.2.576 CORTEX0_CFG_1_CSWREG Register
        577. 14.11.2.577 CORTEX0_CFG_1_TAREG Register
        578. 14.11.2.578 CORTEX0_CFG_1_DRWREG Register
        579. 14.11.2.579 CORTEX0_CFG_1_BD0REG Register
        580. 14.11.2.580 CORTEX0_CFG_1_BD1REG Register
        581. 14.11.2.581 CORTEX0_CFG_1_BD2REG Register
        582. 14.11.2.582 CORTEX0_CFG_1_BD3REG Register
        583. 14.11.2.583 CORTEX0_CFG_1_ROM_REGISTER Register
        584. 14.11.2.584 CORTEX0_CFG_1_ID_REGISTER Register
        585. 14.11.2.585 CORTEX1_CFG_1_CSWREG Register
        586. 14.11.2.586 CORTEX1_CFG_1_TAREG Register
        587. 14.11.2.587 CORTEX1_CFG_1_DRWREG Register
        588. 14.11.2.588 CORTEX1_CFG_1_BD0REG Register
        589. 14.11.2.589 CORTEX1_CFG_1_BD1REG Register
        590. 14.11.2.590 CORTEX1_CFG_1_BD2REG Register
        591. 14.11.2.591 CORTEX1_CFG_1_BD3REG Register
        592. 14.11.2.592 CORTEX1_CFG_1_ROM_REGISTER Register
        593. 14.11.2.593 CORTEX1_CFG_1_ID_REGISTER Register
        594. 14.11.2.594 CORTEX2_CFG_1_CSWREG Register
        595. 14.11.2.595 CORTEX2_CFG_1_TAREG Register
        596. 14.11.2.596 CORTEX2_CFG_1_DRWREG Register
        597. 14.11.2.597 CORTEX2_CFG_1_BD0REG Register
        598. 14.11.2.598 CORTEX2_CFG_1_BD1REG Register
        599. 14.11.2.599 CORTEX2_CFG_1_BD2REG Register
        600. 14.11.2.600 CORTEX2_CFG_1_BD3REG Register
        601. 14.11.2.601 CORTEX2_CFG_1_ROM_REGISTER Register
        602. 14.11.2.602 CORTEX2_CFG_1_ID_REGISTER Register
        603. 14.11.2.603 CORTEX3_CFG_1_CSWREG Register
        604. 14.11.2.604 CORTEX3_CFG_1_TAREG Register
        605. 14.11.2.605 CORTEX3_CFG_1_DRWREG Register
        606. 14.11.2.606 CORTEX3_CFG_1_BD0REG Register
        607. 14.11.2.607 CORTEX3_CFG_1_BD1REG Register
        608. 14.11.2.608 CORTEX3_CFG_1_BD2REG Register
        609. 14.11.2.609 CORTEX3_CFG_1_BD3REG Register
        610. 14.11.2.610 CORTEX3_CFG_1_ROM_REGISTER Register
        611. 14.11.2.611 CORTEX3_CFG_1_ID_REGISTER Register
        612. 14.11.2.612 CORTEX4_CFG_1_CSWREG Register
        613. 14.11.2.613 CORTEX4_CFG_1_TAREG Register
        614. 14.11.2.614 CORTEX4_CFG_1_DRWREG Register
        615. 14.11.2.615 CORTEX4_CFG_1_BD0REG Register
        616. 14.11.2.616 CORTEX4_CFG_1_BD1REG Register
        617. 14.11.2.617 CORTEX4_CFG_1_BD2REG Register
        618. 14.11.2.618 CORTEX4_CFG_1_BD3REG Register
        619. 14.11.2.619 CORTEX4_CFG_1_ROM_REGISTER Register
        620. 14.11.2.620 CORTEX4_CFG_1_ID_REGISTER Register
        621. 14.11.2.621 CORTEX5_CFG_1_CSWREG Register
        622. 14.11.2.622 CORTEX5_CFG_1_TAREG Register
        623. 14.11.2.623 CORTEX5_CFG_1_DRWREG Register
        624. 14.11.2.624 CORTEX5_CFG_1_BD0REG Register
        625. 14.11.2.625 CORTEX5_CFG_1_BD1REG Register
        626. 14.11.2.626 CORTEX5_CFG_1_BD2REG Register
        627. 14.11.2.627 CORTEX5_CFG_1_BD3REG Register
        628. 14.11.2.628 CORTEX5_CFG_1_ROM_REGISTER Register
        629. 14.11.2.629 CORTEX5_CFG_1_ID_REGISTER Register
        630. 14.11.2.630 CORTEX6_CFG_1_CSWREG Register
        631. 14.11.2.631 CORTEX6_CFG_1_TAREG Register
        632. 14.11.2.632 CORTEX6_CFG_1_DRWREG Register
        633. 14.11.2.633 CORTEX6_CFG_1_BD0REG Register
        634. 14.11.2.634 CORTEX6_CFG_1_BD1REG Register
        635. 14.11.2.635 CORTEX6_CFG_1_BD2REG Register
        636. 14.11.2.636 CORTEX6_CFG_1_BD3REG Register
        637. 14.11.2.637 CORTEX6_CFG_1_ROM_REGISTER Register
        638. 14.11.2.638 CORTEX6_CFG_1_ID_REGISTER Register
        639. 14.11.2.639 CORTEX7_CFG_1_CSWREG Register
        640. 14.11.2.640 CORTEX7_CFG_1_TAREG Register
        641. 14.11.2.641 CORTEX7_CFG_1_DRWREG Register
        642. 14.11.2.642 CORTEX7_CFG_1_BD0REG Register
        643. 14.11.2.643 CORTEX7_CFG_1_BD1REG Register
        644. 14.11.2.644 CORTEX7_CFG_1_BD2REG Register
        645. 14.11.2.645 CORTEX7_CFG_1_BD3REG Register
        646. 14.11.2.646 CORTEX7_CFG_1_ROM_REGISTER Register
        647. 14.11.2.647 CORTEX7_CFG_1_ID_REGISTER Register
        648. 14.11.2.648 CORTEX8_CFG_1_CSWREG Register
        649. 14.11.2.649 CORTEX8_CFG_1_TAREG Register
        650. 14.11.2.650 CORTEX8_CFG_1_DRWREG Register
        651. 14.11.2.651 CORTEX8_CFG_1_BD0REG Register
        652. 14.11.2.652 CORTEX8_CFG_1_BD1REG Register
        653. 14.11.2.653 CORTEX8_CFG_1_BD2REG Register
        654. 14.11.2.654 CORTEX8_CFG_1_BD3REG Register
        655. 14.11.2.655 CORTEX8_CFG_1_ROM_REGISTER Register
        656. 14.11.2.656 CORTEX8_CFG_1_ID_REGISTER Register
        657. 14.11.2.657 ROM_TABLE_1_1_ROM_ENTRY0 Register
        658. 14.11.2.658 ROM_TABLE_1_1_ROM_ENTRY1 Register
        659. 14.11.2.659 ROM_TABLE_1_1_ROM_ENTRY2 Register
        660. 14.11.2.660 ROM_TABLE_1_1_ROM_ENTRY3 Register
        661. 14.11.2.661 ROM_TABLE_1_1_ROM_ENTRY4 Register
        662. 14.11.2.662 ROM_TABLE_1_1_ROM_ENTRY5 Register
        663. 14.11.2.663 ROM_TABLE_1_1_COMPUTE_CLUSTER0 Register
        664. 14.11.2.664 ROM_TABLE_1_1_COMPUTE_CLUSTER1 Register
        665. 14.11.2.665 ROM_TABLE_1_1_COMPUTE_CLUSTER2 Register
        666. 14.11.2.666 ROM_TABLE_1_1_DEBUG_CELL0 Register
        667. 14.11.2.667 ROM_TABLE_1_1_DEBUG_CELL1 Register
        668. 14.11.2.668 ROM_TABLE_1_1_DEBUG_CELL2 Register
        669. 14.11.2.669 ROM_TABLE_1_1_DEBUG_CELL3 Register
        670. 14.11.2.670 ROM_TABLE_1_1_DEBUG_CELL4 Register
        671. 14.11.2.671 ROM_TABLE_1_1_DEBUG_CELL5 Register
        672. 14.11.2.672 ROM_TABLE_1_1_DEBUG_CELL6 Register
        673. 14.11.2.673 ROM_TABLE_1_1_DEBUG_CELL7 Register
        674. 14.11.2.674 ROM_TABLE_1_1_DEBUG_CELL8 Register
        675. 14.11.2.675 ROM_TABLE_1_1_DEBUG_CELL9 Register
        676. 14.11.2.676 ROM_TABLE_1_1_DEBUG_CELL10 Register
        677. 14.11.2.677 ROM_TABLE_1_1_DEBUG_CELL11 Register
        678. 14.11.2.678 ROM_TABLE_1_1_EXTCSCOMP0 Register
        679. 14.11.2.679 ROM_TABLE_1_1_EXTCSCOMP1 Register
        680. 14.11.2.680 ROM_TABLE_1_1_EXTCSCOMP2 Register
        681. 14.11.2.681 ROM_TABLE_1_1_EXTCSCOMP3 Register
        682. 14.11.2.682 ROM_TABLE_1_1_EXTCSCOMP4 Register
        683. 14.11.2.683 ROM_TABLE_1_1_EXTCSCOMP5 Register
        684. 14.11.2.684 ROM_TABLE_1_1_EXTCSCOMP6 Register
        685. 14.11.2.685 ROM_TABLE_1_1_EXTCSCOMP7 Register
        686. 14.11.2.686 ROM_TABLE_1_1_EXTCSCOMP8 Register
        687. 14.11.2.687 ROM_TABLE_1_1_EXTCSCOMP9 Register
        688. 14.11.2.688 ROM_TABLE_1_1_EXTCSCOMP10 Register
        689. 14.11.2.689 ROM_TABLE_1_1_EXTCSCOMP11 Register
        690. 14.11.2.690 DRM_CFG_1_PERIPH_ID Register
        691. 14.11.2.691 DRM_CFG_1_VERSION Register
        692. 14.11.2.692 DRM_CFG_1_CAPABILITY Register
        693. 14.11.2.693 DRM_CFG_1_TRACE_CTRL Register
        694. 14.11.2.694 DRM_CFG_1_VBUSM_CTRL Register
        695. 14.11.2.695 DRM_CFG_1_DAP_TIMEOUT Register
        696. 14.11.2.696 DRM_CFG_1_CONFIG Register
        697. 14.11.2.697 DRM_CFG_1_EMUTRIGEN Register
        698. 14.11.2.698 DRM_CFG_1_BINVALLO Register
        699. 14.11.2.699 DRM_CFG_1_BINVALHI Register
        700. 14.11.2.700 DRM_CFG_1_SUSPEND_REG0 Register
        701. 14.11.2.701 DRM_CFG_1_SUSPEND_REG1 Register
        702. 14.11.2.702 DRM_CFG_1_SUSPEND_REG2 Register
        703. 14.11.2.703 DRM_CFG_1_SUSPEND_REG3 Register
        704. 14.11.2.704 DRM_CFG_1_SUSPEND_REG4 Register
        705. 14.11.2.705 DRM_CFG_1_SUSPEND_REG5 Register
        706. 14.11.2.706 DRM_CFG_1_SUSPEND_REG6 Register
        707. 14.11.2.707 DRM_CFG_1_SUSPEND_REG7 Register
        708. 14.11.2.708 DRM_CFG_1_SUSPEND_REG8 Register
        709. 14.11.2.709 DRM_CFG_1_SUSPEND_REG9 Register
        710. 14.11.2.710 DRM_CFG_1_SUSPEND_REG10 Register
        711. 14.11.2.711 DRM_CFG_1_SUSPEND_REG11 Register
        712. 14.11.2.712 DRM_CFG_1_SUSPEND_REG12 Register
        713. 14.11.2.713 DRM_CFG_1_SUSPEND_REG13 Register
        714. 14.11.2.714 DRM_CFG_1_SUSPEND_REG14 Register
        715. 14.11.2.715 DRM_CFG_1_SUSPEND_REG15 Register
        716. 14.11.2.716 DRM_CFG_1_SUSPEND_REG16 Register
        717. 14.11.2.717 DRM_CFG_1_SUSPEND_REG17 Register
        718. 14.11.2.718 DRM_CFG_1_SUSPEND_REG18 Register
        719. 14.11.2.719 DRM_CFG_1_SUSPEND_REG19 Register
        720. 14.11.2.720 DRM_CFG_1_SUSPEND_REG20 Register
        721. 14.11.2.721 DRM_CFG_1_SUSPEND_REG21 Register
        722. 14.11.2.722 DRM_CFG_1_SUSPEND_REG22 Register
        723. 14.11.2.723 DRM_CFG_1_SUSPEND_REG23 Register
        724. 14.11.2.724 DRM_CFG_1_SUSPEND_REG24 Register
        725. 14.11.2.725 DRM_CFG_1_SUSPEND_REG25 Register
        726. 14.11.2.726 DRM_CFG_1_SUSPEND_REG26 Register
        727. 14.11.2.727 DRM_CFG_1_SUSPEND_REG27 Register
        728. 14.11.2.728 DRM_CFG_1_SUSPEND_REG28 Register
        729. 14.11.2.729 DRM_CFG_1_SUSPEND_REG29 Register
        730. 14.11.2.730 DRM_CFG_1_SUSPEND_REG30 Register
        731. 14.11.2.731 DRM_CFG_1_SUSPEND_REG31 Register
        732. 14.11.2.732 CSTPIU_CFG_1_SUPPORTSIZE Register
        733. 14.11.2.733 CSTPIU_CFG_1_CURPORTSIZE Register
        734. 14.11.2.734 CSTPIU_CFG_1_TRIGMODEREG Register
        735. 14.11.2.735 CSTPIU_CFG_1_TRIGCTRREG Register
        736. 14.11.2.736 CSTPIU_CFG_1_TRIGMPYREG Register
        737. 14.11.2.737 CSTPIU_CFG_1_SUPTESTPAT Register
        738. 14.11.2.738 CSTPIU_CFG_1_CURTESTPAT Register
        739. 14.11.2.739 CSTPIU_CFG_1_TESTPATCNT Register
        740. 14.11.2.740 CSTPIU_CFG_1_FORMFLUSHSTAT Register
        741. 14.11.2.741 CSTPIU_CFG_1_FORMFLUSHCTL Register
        742. 14.11.2.742 CSTPIU_CFG_1_FORMSYNCCTR Register
        743. 14.11.2.743 CSTPIU_CFG_1_EXTCTLIN Register
        744. 14.11.2.744 CSTPIU_CFG_1_EXTCTLOUT Register
        745. 14.11.2.745 CSTPIU_CFG_1_ITTRFLINACK Register
        746. 14.11.2.746 CSTPIU_CFG_1_ITTRFLIN Register
        747. 14.11.2.747 CSTPIU_CFG_1_ITATBDATA0 Register
        748. 14.11.2.748 CSTPIU_CFG_1_ITATBCTR2 Register
        749. 14.11.2.749 CSTPIU_CFG_1_ITATBCTR1 Register
        750. 14.11.2.750 CSTPIU_CFG_1_ITATBCTR0 Register
        751. 14.11.2.751 CSTPIU_CFG_1_INTCTRL Register
        752. 14.11.2.752 CSTPIU_CFG_1_CTSET Register
        753. 14.11.2.753 CSTPIU_CFG_1_CTCLR Register
        754. 14.11.2.754 CSTPIU_CFG_1_LAREG Register
        755. 14.11.2.755 CSTPIU_CFG_1_LSREG Register
        756. 14.11.2.756 CSTPIU_CFG_1_AUTHST Register
        757. 14.11.2.757 CSTPIU_CFG_1_DEVID Register
        758. 14.11.2.758 CSTPIU_CFG_1_DEVTYPEID Register
        759. 14.11.2.759 CSTPIU_CFG_1_PERID4 Register
        760. 14.11.2.760 CSTPIU_CFG_1_PERID0 Register
        761. 14.11.2.761 CSTPIU_CFG_1_PERID1 Register
        762. 14.11.2.762 CSTPIU_CFG_1_PERID2 Register
        763. 14.11.2.763 CSTPIU_CFG_1_PERID3 Register
        764. 14.11.2.764 CSTPIU_CFG_1_COMPID0 Register
        765. 14.11.2.765 CSTPIU_CFG_1_COMPID1 Register
        766. 14.11.2.766 CSTPIU_CFG_1_COMPID2 Register
        767. 14.11.2.767 CSTPIU_CFG_1_COMPID3 Register
        768. 14.11.2.768 CTF_CFG_1_CSTFCTLREG Register
        769. 14.11.2.769 CTF_CFG_1_PRIORCTLREG Register
        770. 14.11.2.770 CTF_CFG_1_ITATBDATA0 Register
        771. 14.11.2.771 CTF_CFG_1_ITATBCTR2 Register
        772. 14.11.2.772 CTF_CFG_1_ITATBCTR1 Register
        773. 14.11.2.773 CTF_CFG_1_ITATBCTR0 Register
        774. 14.11.2.774 CTF_CFG_1_INTCTRL Register
        775. 14.11.2.775 CTF_CFG_1_CTSET Register
        776. 14.11.2.776 CTF_CFG_1_CTCLR Register
        777. 14.11.2.777 CTF_CFG_1_LAREG Register
        778. 14.11.2.778 CTF_CFG_1_LSREG Register
        779. 14.11.2.779 CTF_CFG_1_AUTHST Register
        780. 14.11.2.780 CTF_CFG_1_DEVID Register
        781. 14.11.2.781 CTF_CFG_1_DEVTYPEID Register
        782. 14.11.2.782 CTF_CFG_1_PERID4 Register
        783. 14.11.2.783 CTF_CFG_1_PERID5 Register
        784. 14.11.2.784 CTF_CFG_1_PERID6 Register
        785. 14.11.2.785 CTF_CFG_1_PERID7 Register
        786. 14.11.2.786 CTF_CFG_1_PERID0 Register
        787. 14.11.2.787 CTF_CFG_1_PERID1 Register
        788. 14.11.2.788 CTF_CFG_1_PERID2 Register
        789. 14.11.2.789 CTF_CFG_1_PERID3 Register
        790. 14.11.2.790 CTF_CFG_1_COMPID0 Register
        791. 14.11.2.791 CTF_CFG_1_COMPID1 Register
        792. 14.11.2.792 CTF_CFG_1_COMPID2 Register
        793. 14.11.2.793 CTF_CFG_1_COMPID3 Register
  17. 15Revision History
14.9.3.6.8 MMCSD1 Host Controller Registers

Table 14-15065 lists the memory-mapped registers for the MMCSD1 Host Controller. All register offset addresses not listed in Table 14-15065 should be considered as reserved locations and the register contents should not be modified.

Note:

UHSII is not supported. For more information, see Not Supported Features.

Table 14-15064 MMCSD1 HOST CONTROLLER Instances
Instance Base Address
MMCSD1_CTL_CFG 0FA0 0000h
Table 14-15065 MMCSD1 Host Controller Registers
Offset Acronym Register Name MMCSD1_CTL_CFG
Physical Address
Host Controller Interface Register
0h MMCSD1_SDMA_SYS_ADDR_LO 32-bit Block Count/SDMA System Address Low Register 0FA0 0000h
2h MMCSD1_SDMA_SYS_ADDR_HI 32-bit Block Count/SDMA System Address High Register 0FA0 0002h
4h MMCSD1_BLOCK_SIZE 16-bit Block Size Register 0FA0 0004h
6h MMCSD1_BLOCK_COUNT 16-bit Block Count Register 0FA0 0006h
8h MMCSD1_ARGUMENT1_LO Argument1 Low Register 0FA0 0008h
Ah MMCSD1_ARGUMENT1_HI Argument1 High Register 0FA0 000Ah
Ch MMCSD1_TRANSFER_MODE Transfer Mode Register 0FA0 000Ch
Eh MMCSD1_COMMAND Command Register 0FA0 000Eh
10h to 1Eh MMCSD1_RESPONSE_0 to MMCSD1_RESPONSE_7 Response Register 0FA0 0010h to
0FA0 001Eh
20h MMCSD1_DATA_PORT Buffer Data Port Register 0FA0 0020h
24h MMCSD1_PRESENTSTATE Present State Register 0FA0 0024h
28h MMCSD1_HOST_CONTROL1 Host Control 1 Register 0FA0 0028h
29h MMCSD1_POWER_CONTROL Power Control Register 0FA0 0029h
2Ah MMCSD1_BLOCK_GAP_CONTROL Block Gap Control Register 0FA0 002Ah
2Bh MMCSD1_WAKEUP_CONTROL Wakeup Control Register 0FA0 002Bh
2Ch MMCSD1_CLOCK_CONTROL Clock Control Register 0FA0 002Ch
2Eh MMCSD1_TIMEOUT_CONTROL Timeout Control Register 0FA0 002Eh
2Fh MMCSD1_SOFTWARE_RESET Software Reset Register 0FA0 002Fh
30h MMCSD1_NORMAL_INTR_STS Normal Interrupt Status Register 0FA0 0030h
32h MMCSD1_ERROR_INTR_STS Error Interrupt Status Register 0FA0 0032h
34h MMCSD1_NORMAL_INTR_STS_ENA Normal Interrupt Status Enable Register 0FA0 0034h
36h MMCSD1_ERROR_INTR_STS_ENA Error Interrupt Status Enable Register 0FA0 0036h
38h MMCSD1_NORMAL_INTR_SIG_ENA Normal Interrupt Signal Enable Register 0FA0 0038h
3Ah MMCSD1_ERROR_INTR_SIG_ENA Error Interrupt Signal Enable Register 0FA0 003Ah
3Ch MMCSD1_AUTOCMD_ERR_STS Auto CMD Error Status Register 0FA0 003Ch
3Eh MMCSD1_HOST_CONTROL2 Host Control 2 Register 0FA0 003Eh
40h MMCSD1_CAPABILITIES Capabilities Register 0FA0 0040h
48h MMCSD1_MAX_CURRENT_CAP Maximum Current Capabilities Register 0FA0 0048h
50h MMCSD1_FORCE_EVNT_ACMD_ERR_STS Force Event Register for Auto CMD Error Status 0FA0 0050h
52h MMCSD1_FORCE_EVNT_ERR_INT_STS Force Event Register for Error Interrupt Status 0FA0 0052h
54h MMCSD1_ADMA_ERR_STATUS ADMA Error Status Register 0FA0 0054h
58h MMCSD1_ADMA_SYS_ADDRESS ADMA System Address Register 0FA0 0058h
60h MMCSD1_PRESET_VALUE0 Preset Values 0 Register 0FA0 0060h
62h MMCSD1_PRESET_VALUE1 Preset Values 1 Register 0FA0 0062h
64h MMCSD1_PRESET_VALUE2 Preset Values 2 Register 0FA0 0064h
66h MMCSD1_PRESET_VALUE3 Preset Values 3 Register 0FA0 0066h
68h MMCSD1_PRESET_VALUE4 Preset Values 4 Register 0FA0 0068h
6Ah MMCSD1_PRESET_VALUE5 Preset Values 5 Register 0FA0 006Ah
6Ch MMCSD1_PRESET_VALUE6 Preset Values 6 Register 0FA0 006Ch
6Eh MMCSD1_PRESET_VALUE7 Preset Values 7 Register 0FA0 006Eh
72h MMCSD1_PRESET_VALUE8 Preset Values 8 Register 0FA0 0072h
74h MMCSD1_PRESET_VALUE10 Preset Values 10 Register 0FA0 0074h
78h MMCSD1_ADMA3_DESC_ADDRESS ADMA3 Integrated Descriptor Address Register 0FA0 0078h
UHS-II Registers (1)
80h MMCSD1_UHS2_BLOCK_SIZE UHS-II Block Size Register 0FA0 0080h
84h MMCSD1_UHS2_BLOCK_COUNT UHS-II Block Count Register 0FA0 0084h
88h to 9Bh MMCSD1_UHS2_COMMAND_PKT_0 to MMCSD1_UHS2_COMMAND_PKT_19 UHS-II Command Packet Register 0FA0 0088h to
0FA0 009Bh
9Ch MMCSD1_UHS2_XFER_MODE UHS-II Transfer Mode Register 0FA0 009Ch
9Eh MMCSD1_UHS2_COMMAND UHS-II Command Register 0FA0 009Eh
A0h to B3h MMCSD1_UHS2_RESPONSE_0 to MMCSD1_UHS2_RESPONSE_19 UHS-II Response Register 0FA0 00A0h to
0FA0 00B3h
B4h MMCSD1_UHS2_MESSAGE_SELECT UHS-II Message Select Register 0FA0 00B4h
B8h MMCSD1_UHS2_MESSAGE UHS-II Message Register 0FA0 00B8h
BCh MMCSD1_UHS2_DEVICE_INTR_STATUS UHS-II Device Interrupt Status Register 0FA0 00BCh
BEh MMCSD1_UHS2_DEVICE_SELECT UHS-II Device Select Register 0FA0 00BEh
BFh MMCSD1_UHS2_DEVICE_INT_CODE UHS-II Device Interrupt Code Register 0FA0 00BFh
C0h MMCSD1_UHS2_SOFTWARE_RESET UHS-II Software Reset Register 0FA0 00C0h
C2h MMCSD1_UHS2_TIMER_CONTROL UHS-II Timeout Control Register 0FA0 00C2h
C4h MMCSD1_UHS2_ERR_INTR_STS UHS-II Error Interrupt Status Register 0FA0 00C4h
C8h MMCSD1_UHS2_ERR_INTR_STS_ENA UHS-II Error Interrupt Status Enable Register 0FA0 00C8h
CCh MMCSD1_UHS2_ERR_INTR_SIG_ENA UHS-II Error Interrupt Signal Enable Register 0FA0 00CCh
E0h MMCSD1_UHS2_SETTINGS_PTR Pointer for UHS-II Settings Register 0FA0 00E0h
E2h MMCSD1_UHS2_CAPABILITIES_PTR Pointer for UHS-II Host Capabilities Register 0FA0 00E2h
E4h MMCSD1_UHS2_TEST_PTR Pointer for UHS-II Test Register 0FA0 00E4h
E6h MMCSD1_SHARED_BUS_CTRL_PTR Pointer for Embedded Control Register 0FA0 00E6h
E8h MMCSD1_VENDOR_SPECFIC_PTR Pointer for Vendor Specific Area Register 0FA0 00E8h
F4h MMCSD1_BOOT_TIMEOUT_CONTROL Boot Timeout Control Register 0FA0 00F4h
F8h MMCSD1_VENDOR_REGISTER Vendor Register 0FA0 00F8h
FCh MMCSD1_SLOT_INT_STS Slot Interrupt Status Register 0FA0 00FCh
FEh MMCSD1_HOST_CONTROLLER_VER Host Controller Version Register 0FA0 00FEh
100h MMCSD1_UHS2_GEN_SETTINGS UHS-II General Settings Register 0FA0 0100h
104h MMCSD1_UHS2_PHY_SETTINGS UHS-II PHY Settings Register 0FA0 0104h
108h MMCSD1_UHS2_LNK_TRN_SETTINGS UHS-II LINK/TRAN Settings Register 0FA0 0108h
110h MMCSD1_UHS2_GEN_CAP UHS-II General Capabilities Register 0FA0 0110h
114h MMCSD1_UHS2_PHY_CAP UHS-II PHY Capabilities Register 0FA0 0114h
118h MMCSD1_UHS2_LNK_TRN_CAP UHS-II LINK/TRAN Capabilities Register 0FA0 0118h
120h MMCSD1_FORCE_UHSII_ERR_INT_STS Force Event for UHS-II Error Interrupt Status Register 0FA0 0120h
Command Queue Registers
200h MMCSD1_CQ_VERSION Command Queueing Version Register 0FA0 0200h
204h MMCSD1_CQ_CAPABILITIES Command Queueing Capabilities Register 0FA0 0204h
208h MMCSD1_CQ_CONFIG Command Queueing Configuration Register 0FA0 0208h
20Ch MMCSD1_CQ_CONTROL Command Queueing Control Register 0FA0 020Ch
210h MMCSD1_CQ_INTR_STS Command Queueing Interrupt Status Register 0FA0 0210h
214h MMCSD1_CQ_INTR_STS_ENA Command Queueing Interrupt Status Enabled Register 0FA0 0214h
218h MMCSD1_CQ_INTR_SIG_ENA Command Queueing Interrupt Signal Enable Register 0FA0 0218h
21Ch MMCSD1_CQ_INTR_COALESCING Interrupt Coalescing Register 0FA0 021Ch
220h MMCSD1_CQ_TDL_BASE_ADDR Command Queueing Task Descriptor List Base Address Low Register 0FA0 0220h
224h MMCSD1_CQ_TDL_BASE_ADDR_UPBITS Command Queueing Task Descriptor List Base Address High Register 0FA0 0224h
228h MMCSD1_CQ_TASK_DOOR_BELL Command Queueing Task Doorbell Register 0FA0 0228h
22Ch MMCSD1_CQ_TASK_COMP_NOTIF Command Queueing Task Doorbell Notification Register 0FA0 022Ch
230h MMCSD1_CQ_DEV_QUEUE_STATUS Command Queueing Device Queue Status Register 0FA0 0230h
234h MMCSD1_CQ_DEV_PENDING_TASKS Command Queueing Device Pending Tasks Register 0FA0 0234h
238h MMCSD1_CQ_TASK_CLEAR Command Queueing Task Clear Register 0FA0 0238h
240h MMCSD1_CQ_SEND_STS_CONFIG1 Send Status Timer Configuration 1 Register 0FA0 0240h
244h MMCSD1_CQ_SEND_STS_CONFIG2 Send Status Configuration 2 Register 0FA0 0244h
248h MMCSD1_CQ_DCMD_RESPONSE Command Response Register for Direct Command Task 0FA0 0248h
250h MMCSD1_CQ_RESP_ERR_MASK Response Mode Error Mask Register 0FA0 0250h
254h MMCSD1_CQ_TASK_ERR_INFO Task Error Information Register 0FA0 0254h
258h MMCSD1_CQ_CMD_RESP_INDEX Command Response Index Register 0FA0 0258h
25Ch MMCSD1_CQ_CMD_RESP_ARG Command Response Argument Register 0FA0 025Ch
260h MMCSD1_CQ_ERROR_TASK_ID Command Queueing Error Task ID Register 0FA0 0260h
(1) UHSII is not supported. For more information, see Not Supported Features.

3.6.8.1 MMCSD1_SDMA_SYS_ADDR_LO Register (Offset = 0h) [reset = 0h]

MMCSD1_SDMA_SYS_ADDR_LO is shown in Figure 14-7423 and described in Table 14-15067.

Return to Summary Table.

This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10.

Table 14-15066 MMCSD1_SDMA_SYS_ADDR_LO Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0000h
Figure 14-7423 MMCSD1_SDMA_SYS_ADDR_LO Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMA_ADDRESS
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15067 MMCSD1_SDMA_SYS_ADDR_LO Register Field Descriptions
Bit Field Type Reset Description
15-0 SDMA_ADDRESS R/W 0h

32-bit Block Count (SDMA System Address) Low

When the MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 0h, DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA.

When the MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h, SDMA uses the MMCSD1_ADMA_SYS_ADDRESS register instead of using this register to support both 32-bit and 64-bit addressing. This register is re-assigned to 32-bit Block Count and then SDMA may use Auto CMD23.

(1) SDMA System Address (MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 0h)

This register contains the system memory address for a SDMA transfer in 32-bit addressing mode. When the Host Controller (HC) stops a SDMA transfer, this register shall point to the system address of the next contiguous data position.

It can be accessed only if no transaction is executing (after a transaction has stopped). Reading this register during SDMA transfers may return an invalid value. The Host Driver (HD) shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the MMCSD1_BLOCK_SIZE[14-12] SDMA_BUF_SIZE bit field. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (Offset = 3h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by setting the MMCSD1_BLOCK_GAP_CONTROL[1] CONTINUE bit, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI). ADMA does not use this register.

(2) 32-bit Block Count (MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 1h)

Host Controller Version 4.10 re-defines this register as 32-bit Block Count . In version 4.00, this register may be used as 32-bit block count only for Auto CMD23 to set the argument of the CMD23 while executing Auto CMD23.

The Host Controller would decrement the block count of this register every block transfer and data transfer stops when the count reaches zero.

FFFF FFFFh (4G - 1 Block)

....

0000 0002h (2 Blocks)

0000 0001h (1 Block)

0000 0000h (Stop Count)

Note: This register should be accessed only when no transaction is executing. Reading this register during data transfers may return invalid value.

3.6.8.2 MMCSD1_SDMA_SYS_ADDR_HI Register (Offset = 2h) [reset = 0h]

MMCSD1_SDMA_SYS_ADDR_HI is shown in Figure 14-7424 and described in Table 14-15069.

Return to Summary Table.

This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10.

Table 14-15068 MMCSD1_SDMA_SYS_ADDR_HI Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0002h
Figure 14-7424 MMCSD1_SDMA_SYS_ADDR_HI Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMA_ADDRESS
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15069 MMCSD1_SDMA_SYS_ADDR_HI Register Field Descriptions
Bit Field Type Reset Description
15-0 SDMA_ADDRESS R/W 0h

32-bit Block Count (SDMA System Address) High

This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10.

3.6.8.3 MMCSD1_BLOCK_SIZE Register (Offset = 4h) [reset = 0h]

MMCSD1_BLOCK_SIZE is shown in Figure 14-7425 and described in Table 14-15071.

Return to Summary Table.

This register is used to configure the number of bytes in a data block.

Table 14-15070 MMCSD1_BLOCK_SIZE Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0004h
Figure 14-7425 MMCSD1_BLOCK_SIZE Register
15 14 13 12 11 10 9 8
RESERVED SDMA_BUF_SIZE XFER_BLK_SIZE
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
XFER_BLK_SIZE
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15071 MMCSD1_BLOCK_SIZE Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0h

Reserved
14-12 SDMA_BUF_SIZE R/W 0h

Host SDMA Buffer Size

To perform long DMA transfer, System Address register (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI) shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary specified by these fields and the Host Controller generates the DMA Interrupt to request the Host Driver to update the System Address register (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI).

These bits shall support when the MMCSD1_CAPABILITIES[22] SDMA_SUPPORT bit is set to 1h and this function is active when the MMCSD1_TRANSFER_MODE[0] DMA_ENA bit is set to 1h.

0h: 4KB (Detects A11 Carry out)

1h: 8KB (Detects A12 Carry out)

2h: 16KB (Detects A13 Carry out)

3h: 32KB (Detects A14 Carry out)

4h: 64KB (Detects A15 Carry out)

5h: 128KB (Detects A16 Carry out)

6h: 256KB (Detects A17 Carry out)

7h: 512KB (Detects A18 Carry out)
11-0 XFER_BLK_SIZE R/W 0h

Transfer Block Size

This field specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25 and CMD53. It can be accessed only if no transaction is executing (after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored.

0000h: No Data Transfer

0001h: 1 Byte

0002h: 2 Bytes

0003h: 3 Bytes

0004h: 4 Bytes

....

01FFh: 511 Bytes

0200h: 512 Bytes

....

0800h: 2048 Bytes

3.6.8.4 MMCSD1_BLOCK_COUNT Register (Offset = 6h) [reset = 0h]

MMCSD1_BLOCK_COUNT is shown in Figure 14-7426 and described in Table 14-15073.

Return to Summary Table.

This register is used to configure the number of data blocks.

Table 14-15072 MMCSD1_BLOCK_COUNT Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0006h
Figure 14-7426 MMCSD1_BLOCK_COUNT Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFER_BLK_CNT
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15073 MMCSD1_BLOCK_COUNT Register Field Descriptions
Bit Field Type Reset Description
15-0 XFER_BLK_CNT R/W 0h

16-bit Block Count

Host Controller Version 4.10 extends block count to 32-bit .

Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows:

(1) If the MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 0h or 16-bit Block Count register is set to non-zero, 16-bit Block Count register is selected.

(2) If the MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h and 16-bit Block Count register is set to zero, 32-bit Block Count register is selected.

Use of 16-bit/32-bit Block Count register is enabled when the MMCSD1_TRANSFER_MODE[1] BLK_CNT_ENA bit is set to 1h and is valid only for multiple block transfers.

The Host Driver shall set this register to a value between 1h and the maximum block count. The Host Controller decrements the block count after each block transfer and stops when the count reaches zero. Setting the block count to 0h results in no data blocks is transferred.

This register should be accessed only when no transaction is executing (after transactions are stopped).

During data transfer, read operations on this register may return an invalid value and write operations are ignored.

0000h: Stop Count

0001h: 1 Block

0002h: 2 Blocks

....

FFFFh: 65535 Blocks

3.6.8.5 MMCSD1_ARGUMENT1_LO Register (Offset = 8h) [reset = 0h]

MMCSD1_ARGUMENT1_LO is shown in Figure 14-7427 and described in Table 14-15075.

Return to Summary Table.

This register contains Lower bits of SD Command Argument.

Table 14-15074 MMCSD1_ARGUMENT1_LO Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0008h
Figure 14-7427 MMCSD1_ARGUMENT1_LO Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD_ARG1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15075 MMCSD1_ARGUMENT1_LO Register Field Descriptions
Bit Field Type Reset Description
15-0 CMD_ARG1 R/W 0h

Command Argument 1 Low

The SD Command Argument is specified as bit 23-8 of Command-Format.

3.6.8.6 MMCSD1_ARGUMENT1_HI Register (Offset = Ah) [reset = 0h]

MMCSD1_ARGUMENT1_HI is shown in Figure 14-7428 and described in Table 14-15077.

Return to Summary Table.

This register contains higher bits of SD Command Argument.

Table 14-15076 MMCSD1_ARGUMENT1_HI Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 000Ah
Figure 14-7428 MMCSD1_ARGUMENT1_HI Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD_ARG1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15077 MMCSD1_ARGUMENT1_HI Register Field Descriptions
Bit Field Type Reset Description
15-0 CMD_ARG1 R/W 0h

Command Argument 1 High

The SD Command Argument is specified as bit 39-24 of Command-Format.

3.6.8.7 MMCSD1_TRANSFER_MODE Register (Offset = Ch) [reset = 0h]

MMCSD1_TRANSFER_MODE is shown in Figure 14-7429 and described in Table 14-15079.

Return to Summary Table.

Table 14-15078 MMCSD1_TRANSFER_MODE Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 000Ch
Figure 14-7429 MMCSD1_TRANSFER_MODE Register
15 14 13 12 11 10 9 8
RESERVED RESP_INTR_DIS
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESP_ERR_CHK_ENA RESP_TYPE MULTI_BLK_SEL DATA_XFER_DIR AUTO_CMD_ENA BLK_CNT_ENA DMA_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15079 MMCSD1_TRANSFER_MODE Register Field Descriptions
Bit Field Type Reset Description
15-9 RESERVED R 0h

Reserved
8 RESP_INTR_DIS R/W 0h

Response Interrupt Disable

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, sets this bit to 0h and waits Command Complete Interrupt (MMCSD1_NORMAL_INTR_STS[0] CMD_COMPLETE) and then checks the Response register (MMCSD1_RESPONSE_0 to MMCSD1_RESPONSE_7).

If Host Controller checks response error, sets this bit to 1h and sets the MMCSD1_TRANSFER_MODE[7] RESP_ERR_CHK_ENA bit to 1h. Command Complete Interrupt (MMCSD1_NORMAL_INTR_STS[0] CMD_COMPLETE) is disabled by this bit regardless of Command Complete Signal Enable (MMCSD1_NORMAL_INTR_SIG_ENA[0] CMD_COMPLETE).

0h: Response Interrupt is enabled

1h: Response Interrupt is disabled
7 RESP_ERR_CHK_ENA R/W 0h

Response Error Check Enable

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.

If Host Driver checks response error, this bit is set to 0h and the MMCSD1_TRANSFER_MODE[8] RESP_INTR_DIS bit is set to 0h.

If Host Controller checks response error, sets this bit to 1h and sets the Response Interrupt Disable bit to 1h (MMCSD1_TRANSFER_MODE[8] RESP_INTR_DIS = 1h).

The MMCSD1_TRANSFER_MODE[6] RESP_TYPE bit selects either R1 or R5 response type. If an error is detected, Response Error Interrupt is generated in the MMCSD1_ERROR_INTR_STS register.

0h: Response Error Check is disabled

1h: Response Error Check is enabled
6 RESP_TYPE R/W 0h

Response Type R1/R5

When response error check is enabled (MMCSD1_TRANSFER_MODE[7] RESP_ERR_CHK_ENA = 1h), this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO.

Error Statuses Checked in R1:

Bit31 OUT_OF_RANGE

Bit30 ADDRESS_ERROR

Bit29 BLOCK_LEN_ERROR

Bit26 WP_VIOLATION

Bit25 CARD_IS_LOCKED

Bit23 COM_CRC_ERROR

Bit21 CARD_ECC_FAILED

Bit20 CC_ERROR

Bit19 ERROR

Response Flags Checked in R5:

Bit07 COM_CRC_ERROR

Bit03 ERROR

Bit01 FUNCTION_NUMBER

Bit00 OUT_OF_RANGE

0h: R1 (Memory)

1h: R5 (SDIO)
5 MULTI_BLK_SEL R/W 0h

Multi/Single Block Select

This bit enables multiple block data transfers.

0h: Single Block

1h: Multiple Block
4 DATA_XFER_DIR R/W 0h

Data Transfer Direction Select

This bit defines the direction of data transfers.

0h: Write (Host to Card)

1h: Read (Card to Host)
3-2 AUTO_CMD_ENA R/W 0h

Auto CMD Enable

This field determines use of auto command functions.

There are three methods to stop Multiple-block read and write operation by CMD23 or CMD12. In the other operations (for example single read/write operation), this field is set to 0h.

(1) Auto CMD12 Enable:

Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 1h, the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the MMCSD1_AUTOCMD_ERR_STS register. The Host Driver shall not set this bit if the command does not require CMD12.

When MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 0h, CMD12 is issued when 16-bit Block Count is expired.

When MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 1h, CMD12 is issued when 16-bit Block Count or 32-bit Block Count is expired.

(2) Auto CMD23 Enable:

When this bit field is set to 2h, the Host Controller issues a CMD23 automatically before issuing a command specified in the MMCSD1_COMMAND register. The Host Controller Version 3.00 and later shall support this function.

The following conditions are required to use the Auto CMD23:

Auto CMD23 Supported (Host Controller Version is 3.00 or later).

A memory card that supports CMD23 (SCR[33] = 1h).

If DMA is used, it shall be ADMA.

Only when CMD18 or CMD25 is issued. Auto CMD23 can be used with or without ADMA. By writing the MMCSD1_COMMAND register, the Host Controller issues a CMD23 first and then issues a command specified by the MMCSD1_COMMAND[13:8] CMD_INDEX bit field. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the MMCSD1_AUTOCMD_ERR_STS register.

32-bit block count value for CMD23 is set to 32-bit Block Count (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI) register.

(3) Auto CMD Auto Select (Version 4.10):

As CMD23 is optional for SD memory card except UHS 104 card, if card supports CMD23, Auto CMD 23 should be used instead of Auto CMD12. Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of the MMCSD1_HOST_CONTROL2[11] CMD23_ENA bit which indicates whether card supports CMD23. If MMCSD1_HOST_CONTROL2[11] CMD23_ENA = 1h, Auto CMD23 is used and if MMCSD1_HOST_CONTROL2[11] CMD23_ENA = 0h, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable.

0h: Auto Command Disabled

1h: Auto CMD12 Enable

2h: Auto CMD23 Enable

3h: Reserved
1 BLK_CNT_ENA R/W 0h

Block Count Enable

This bit is used to enable the MMCSD1_BLOCK_COUNT register, which is only relevant for multiple block transfers. When this bit is 0h, the MMCSD1_BLOCK_COUNT register is disabled, which is useful in executing an infinite transfer.

0h: Disable

1h: Enable
0 DMA_ENA R/W 0h

DMA Enable

DMA can be enabled only if the MMCSD1_CAPABILITIES[22] SDMA_SUPPORT bit is set. If this bit is set to 1h, a DMA operation shall begin when the HD writes to the upper byte of the MMCSD1_COMMAND register.

0h: Disable

1h: Enable

This register is used to control the operations of data transfers.

This register is used to control the operation of data transfers. The Host Driver shall set this register before issuing a command which transfers data (Refer to MMCSD1_COMMAND[5] DATA_PRESENT bit), or before issuing a Resume command. The Host Driver shall save the value of this register when the data transfer is suspended (as a result of a Suspend command) and restore it before issuing a Resume command. To prevent data loss, the Host Controller shall implement write protection for this register during data transactions. Writes to this register shall be ignored when the MMCSD1_PRESENTSTATE[1] INHIBIT_DAT bit is 1h.

Table 14-15080 shows the determination of transfer type.

Table 14-15080 Determination of Transfer Type
Multi/Single Block Select Block Count Enable Block Count Function
0 Don't Care Don't Care Single Transfer
1 0 Don't Care Infinite Transfer
1 1 Not Zero Multiple Transfer
1 1 Zero Stop Multiple Transfer

3.6.8.8 MMCSD1_COMMAND Register (Offset = Eh) [reset = 0h]

MMCSD1_COMMAND is shown in Figure 14-7430 and described in Table 14-15082.

Return to Summary Table.

This register is used to program the Command for host controller.

Table 14-15081 MMCSD1_COMMAND Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 000Eh
Figure 14-7430 MMCSD1_COMMAND Register
15 14 13 12 11 10 9 8
RESERVED CMD_INDEX
R-0h R/W-0h
7 6 5 4 3 2 1 0
CMD_TYPE DATA_PRESENT CMD_INDEX_CHK_ENA CMD_CRC_CHK_ENA SUB_CMD RESP_TYPE_SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15082 MMCSD1_COMMAND Register Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R 0h

Reserved
13-8 CMD_INDEX R/W 0h

Command Index

This bit shall be set to the command number (CMD0-63, ACMD0-63).
7-6 CMD_TYPE R/W 0h

Command Type

There are three types of special commands. Suspend, Resume and Abort. These bits shall be set to 0h for all other commands.

Suspend Command:

If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD shall restart the transfer by setting the MMCSD1_BLOCK_GAP_CONTROL[1] CONTINUE bit.

Resume Command:

The HD re-starts the data transfer by restoring the registers in the range of 04FB 0000h - 04FB 000Dh (04F9 8000h - 04F9 800Dh). The HC shall check for busy before starting write transfers.

Abort Command:

If this command is set when executing a read transfer, the HC shall stop reads to the buffer. If this command is set when executing a write transfer, the HC shall stop driving the DAT line. After issuing the Abort command, the HD should issue a software reset.

0h: Normal

1h: Suspend

2h: Resume

3h: Abort
5 DATA_PRESENT R/W 0h

Data Present Select

This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line. If is set to 0h for the following:

1. Commands using only CMD line (for example CMD52).

2. Commands with no data transferbut using busy signal on DAT[0]line (R1b or R5b for example CMD38).

3. Resume Command.

0h: No Data Present

1h: Data Present
4 CMD_INDEX_CHK_ENA R/W 0h

Command Index Check Enable

If this bit is set to 1h, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0h, the Index field is not checked.

0h: Disable

1h: Enable
3 CMD_CRC_CHK_ENA R/W 0h

Command CRC Check Enable

If this bit is set to 1h, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0h, the CRC field is not checked.

0h: Disable

1h: Enable
2 SUB_CMD R/W 0h

Sub Command Flag

This bit is added from Version 4.10 to distinguish a main command or sub command. When issuing a main command, this bit is set to 0h and when issuing a sub command, this bit is set to 1h. Setting of this bit is checked by the MMCSD1_PRESENTSTATE[28] SUB_COMMAND_STS bit.

Host Driver manages whether main or sub command. Host Controller does not refer to this bit to issue a command.

0h: Sub Command

1h: Main Command
1-0 RESP_TYPE_SEL R/W 0h

Response Type Select

0h: No Response

1h: Response length 136

2h: Response length 48

3h: Response length 48 check Busy after response

3.6.8.9 MMCSD1_RESPONSE_0 to MMCSD1_RESPONSE_7 Register (Offset = 10h to 1Eh) [reset = 0h]

MMCSD1_RESPONSE_0 to MMCSD1_RESPONSE_7 is shown in Figure 14-7431 and described in Table 14-15084.

Return to Summary Table.

This registers is used to store responses from SD Cards.

Table 14-15083 MMCSD1_RESPONSE_0 to MMCSD1_RESPONSE_7 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0010h to 0FA0 001Eh
Figure 14-7431 MMCSD1_RESPONSE_0 to MMCSD1_RESPONSE_7 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD_RESP
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15084 Register Field Descriptions
Bit Field Type Reset Description
15-0 CMD_RESP R 0h

Command Response

R[] refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit range within the Response register.

Table 14-15085 defines the relation between the parameter and name of response type.

Table 14-15085 Relation between Parameters and the Name of Response Type
Response Type Index Check Enable CRC Check Enable Name of Response Type
00 0 0 No Response
01 0 1 R2
10 0 0 R3, R4
10 1 1 R1, R6, R5, R7
11 1 1 R1b, R5b

The following table describes the mapping of command responses from the SD Bus to this register for each response type. In the table, R[] refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit range within the Response register.

Table 14-15086 shows response bit definition for each response type.

Table 14-15086 Response Bit Definition for each Response Type
Kind of Response Meaning of Response Response Field Response Register
R1, R1b (normal response) Card Status R[39:8] REP[31:0]
R1b (Auto CMD12 response) Card Status for Auto CMD12 R[39:8] REP[127:96]
R1 (Auto CMD23 response) Card Status for Auto CMD23 R[39:8] REP [127:96]
R2 (CID, CSD Register) CID or CSD register include R[127:8] REP[119:0]
R3 (OCR Register) OCR Register for memory R[39:8] REP[31:0]
R4 (OCR Register) OCR Register for I/O etc. R[39:8] REP[31:0]
R5, R5b SDIO Response R[39:8] REP[31:0]
R6 (Published RCA response) New published RCA[31:16] etc. R[39:8] REP[31:0]

The Response Field indicates bit positions of "Responses" defined in the Physical Layer Specification. The table shows most responses with a length of 48 (R[47:0]) have 32 bits of the response data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b (Auto CMD12 responses) and R1 (Auto CMD23 response) have response data bits R[39:8] stored in the Response register at REP[127:96]. Responses with length 136 (R[135:0]) have 120 bits of the response data (R[127:8]) stored in the Response register at REP[119:0].

To read the response status efficiently, the Host Controller only stores part of the response data in the Response register. This enables the Host Driver to read 32 bits of response data efficiently in one read cycle on a 32-bit bus system. Parts of the response, the Index field and the CRC, are checked by the Host Controller (as specified by the MMCSD1_COMMAND[4] CMD_INDEX_CHK_ENA and MMCSD1_COMMAND[3] CMD_CRC_CHK_ENA bits) and generate an error interrupt if an error is detected. The bit range for the CRC check depends on the response length. If the response length is 48, the Host Controller shall check R[47:1], and if the response length is 136 the Host Controller shall check R[119:1].

Since the Host Controller may have a multiple block data DAT line transfer executing concurrently with a CMD_wo_DAT command, the Host Controller stores the Auto CMD12 response in the upper bits (REP[127:96]) of the Response register. The CMD_wo_DAT response is stored in REP[31:0]. This allows the Host Controller to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT and vice versa.

While executing Auto CMD23, the response of CMD23 is saved to REP [127:96] and the response of multiple-block read and write command is save to REP [31:0]. The response error of CMD23 is indicated in the MMCSD1_AUTOCMD_ERR_STS register. When the Host Controller modifies part of the Response register, as shown in the table, it shall preserve the unmodified bits.

3.6.8.10 MMCSD1_DATA_PORT Register (Offset = 20h) [reset = 0h]

MMCSD1_DATA_PORT is shown in Figure 14-7432 and described in Table 14-15088.

Return to Summary Table.

This register is used to access internal buffer.

Table 14-15087 MMCSD1_DATA_PORT Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0020h
Figure 14-7432 MMCSD1_DATA_PORT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUF_RD_DATA
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15088 MMCSD1_DATA_PORT Register Field Descriptions
Bit Field Type Reset Description
31-0 BUF_RD_DATA R/W 0h

Buffer Data

The Host Controller Buffer can be accessed through this 32-bit Data Port Register.

3.6.8.11 MMCSD1_PRESENTSTATE Register (Offset = 24h) [reset = 1F00000h]

MMCSD1_PRESENTSTATE is shown in Figure 14-7433 and described in Table 14-15090.

Return to Summary Table.

The Host Driver can get status of the Host Controller from this 32-bit read-only register.

Table 14-15089 MMCSD1_PRESENTSTATE Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0024h
Figure 14-7433 MMCSD1_PRESENTSTATE Register
31 30 29 28 27 26 25 24
UHS2_IF_DETECTION UHS2_IF_LANE_SYNC UHS2_DORMANT SUB_COMMAND_STS CMD_NOT_ISS_BY_ERR RESERVED SDIF_CMDIN
R-0h R-0h R-0h R-0h R-0h R-0h R-1h
23 22 21 20 19 18 17 16
SDIF_DAT3IN SDIF_DAT2IN SDIF_DAT1IN SDIF_DAT0IN WRITE_PROTECT CARD_DETECT CARD_STATE_STABLE CARD_INSERTED
R-1h R-1h R-1h R-1h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED BUF_RD_ENA BUF_WR_ENA RD_XFER_ACTIVE WR_XFER_ACTIVE
R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
SDIF_DAT7IN SDIF_DAT6IN SDIF_DAT5IN SDIF_DAT4IN RETUNING_REQ DATA_LINE_ACTIVE INHIBIT_DAT INHIBIT_CMD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15090 MMCSD1_PRESENTSTATE Register Field Descriptions
Bit Field Type Reset Description
31 UHS2_IF_DETECTION R 0h

UHS-II IF Detection (UHS-II Only)

This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register (MMCSD1_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 1h). UHS-II interface initialization is activated by setting the MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA bit. Host Controller drives STB.L on D0 lane from EIDL state and waits for receiving STB.L on D1 lane. This bit is set to 1h if STB.L is detected on D1 lane. Host Controller shall compensate latency from setting SD Clock Enable to output STB.L on D0 lane when reading this status. This bit may be read any time after setting SD Clock Enable for faster UHS-II IF detection but Host Driver shall check this status at least 200µs period from setting SD Clock Enable (MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA) until detecting UHS-II IF.

After UHS-II IF is detected, this bit is cleared by when EIDL is detected on D0 lane, UHS-II Interface Enable is set to 0h (MMCSD1_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 0h) or Host full reset is executed.

1h: UHS-II IF is detected

0h: UHS-II IF is not detected
30 UHS2_IF_LANE_SYNC R 0h

Lane Synchronization (UHS-II Only)

This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register (MMCSD1_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 1h). On detecting UHS-II Interface (D31 = 1h), Host Controller provides SYN LSS on D0 lane and waits for receiving SYN LSS on D1 lane. If SYN LSS is detected on D1 lane, Host Controller provides LIDL LSS on D0 lane and waits for receiving LIDL LSS on D1 lane.

In case of Version 4.00, this bit indicates completion of Device PHY Initialization by detecting LIDL LSS on D1 lane.

From Version 4.10, Host Controller may implement a specific PHY verification method and PHY Initialization Failure can be indicated by keeping this bit to 0h even LIDL LSS is detected on D1 lane. Host Driver detects PHY Initialization Failure by timeout.

This bit is cleared by when D0 lane is set to EIDL, UHS-II Interface Enable is set to 0h (MMCSD1_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 0h) or executes Host full reset.

1h: UHS-II PHY is initialized

0h: UHS-II PHY is not initialized
29 UHS2_DORMANT R 0h

In Dormant State (UHS-II Only)

This status indicates whether UHS-II lanes enter Dormant state. This function is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register (MMCSD1_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 1h). On issuing GO_DORMAT_STATE command, "Go Dormant Command (7h)" is set to Command type in the UHS-II Command register (MMCSD1_UHS2_COMMAND[7:6] CMD_TYPE). This command type acts as a trigger to enter lanes into dormant state. Host Controller provides STB.H and EIDL on D0 lane and waits for receiving STB.H and EIDL on D1 lane. This bit is set to 1h after the time of T_DMT_ENTRY (750 RCLK cycle) or more from detecting EIDL on D1 lane.

RCLK may be stopped in dormant state, by setting SD Clock Enable to 0h in the Clock Control register (MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA = 0h) while In Dormant State bit is set to 1h. On writing Clock Control register with setting SD Clock Enable to 1h (MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA = 1h), Host Controller wakes lanes to exit Dormant State and In Dormant State is set to 0h.

In case of the card enters Hibernate Mode (RCLK is stopped), Host Driver may turn off VDD1 by clearing SD Bus Power for VDD1 bit in the MMCSD1_POWER_CONTROL register. Host Controller shall turn off VDD1 after stopping RCLK. This bit is cleared by when Host Controller drives STB.L on D0 lane, UHS-II Interface Enable is set to 0h (MMCSD1_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 0h) or executes Host full reset.

1h: In DORMANT state

0h: Not in DORMANT state
28 SUB_COMMAND_STS R 0h

Sub Command Status

The MMCSD1_COMMAND register and Response register (MMCSD1_RESPONSE_0 to MMCSD1_RESPONSE_7) are commonly used for main command and sub command. This status is used to distinguish which response error statuses, main command or sub command, indicated in the MMCSD1_ERROR_INTR_STS register or in the MMCSD1_UHS2_ERR_INTR_STS register. Just before reading of this register, the MMCSD1_COMMAND[2] SUB_CMD bit or the MMCSD1_UHS2_COMMAND register is copied to this status. This status is effective not only when Response Error interrupt is generated but also when data error interrupt is generated with Command Not Issued by Error (D27 of this register) or Auto CMD Error interrupt is generated with Command Not Issued by Error by Auto CMD12 in the MMCSD1_AUTOCMD_ERR_STS register.

1h: Sub Command Status

0h: Main Command Status
27 CMD_NOT_ISS_BY_ERR R 0h

Command Not Issued by Error

Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the MMCSD1_AUTOCMD_ERR_STS register). This status is set to 1h when Host Controller cannot issue a command after setting MMCSD1_COMMAND register or MMCSD1_UHS2_COMMAND register. Sub Command Status (D28) indicates which command is not issued (main or sub).

1h: Command cannot be issued

0h: No error for issuing a command
26-25 RESERVED R 0h

Reserved
24 SDIF_CMDIN R 1h

CMD Line Signal Level (SD Mode Only)

This status is used to check CMD line level to recover from errors, and for debugging.
23 SDIF_DAT3IN R 1h

DAT[3] Line Signal Level (SD Mode Only)

This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[3].

D23 - DAT[3]
22 SDIF_DAT2IN R 1h

DAT[2] Line Signal Level (SD Mode Only)

This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[2].

D22 - DAT[2]
21 SDIF_DAT1IN R 1h

DAT[1] Line Signal Level (SD Mode Only)

This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[1].

D21 - DAT[1]
20 SDIF_DAT0IN R 1h

DAT[0] Line Signal Level (SD Mode Only)

This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0].

D20 - DAT[0]
19 WRITE_PROTECT R 0h

Write Protect Switch Pin Level

The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin.

0h: Write protected (SDWP# = 1)

1h: Write enabled (SDWP# = 0)
18 CARD_DETECT R 0h

Card Detect Pin Level

This bit reflects the inverse value of the SDCD# pin.

0h: No Card present (SDCD# = 1)

1h: Card present (SDCD# = 0)
17 CARD_STATE_STABLE R 0h

Card State Stable

This bit is used for testing. If it is 0h, the Card Detect Pin Level is not stable. If this bit is set to 1h, it means the Card Detect Pin Level is stable. The MMCSD1_SOFTWARE_RESET[0] SWRST_FOR_ALL bit shall not affect this bit.

0h: Reset of Debouncing

1h: No Card or Inserted
16 CARD_INSERTED R 0h

Card Inserted

This bit indicates whether a card has been inserted. Changing from 0h to 1h generates a Card Insertion interrupt in the MMCSD1_NORMAL_INTR_STS register and changing from 1h to 0h generates a Card Removal Interrupt in the MMCSD1_NORMAL_INTR_STS register. The MMCSD1_SOFTWARE_RESET[0] SWRST_FOR_ALL bit shall not affect this bit.

If a Card is removed while its power is on and its clock is oscillating, the HC shall clear the MMCSD1_POWER_CONTROL[0] SD_BUS_POWER bit and the MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA bit. In addition the HD should clear the HC by the MMCSD1_SOFTWARE_RESET[0] SWRST_FOR_ALL bit. The card detect is active regardless of the SD Bus Power.

0h: Reset or Debouncing or No Card

1h: Card Inserted
15-12 RESERVED R 0h

Reserved
11 BUF_RD_ENA R 0h

Buffer Read Enable

This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1h, readable data exists in the buffer. A change of this bit from 1h to 0h occurs when all the block data is read from the buffer. A change of this bit from 0h to 1h occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt.

0h: Read Disable

1h: Read Enable
10 BUF_WR_ENA R 0h

Buffer Write Enable

This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1h, data can be written to the buffer. A change of this bit from 1h to 0h occurs when all the block data is written to the buffer. A change of this bit from 0h to 1h occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt.

0h: Write Disable

1h: Write Enable
9 RD_XFER_ACTIVE R 0h

Read Transfer Active (SD Mode Only)

This status is used for detecting completion of a read transfer.

This bit is set to 1h for either of the following conditions:

After the end bit of the read command.

When writing a 1h to continue Request in the MMCSD1_BLOCK_GAP_CONTROL register to restart a read transfer.

This bit is cleared to 0h for either of the following conditions:

When the last data block as specified by block length is transferred to the system.

When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1h (MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP = 1h). A transfer complete interrupt is generated when this bit changes to 0h.

1h: Transferring data

0h: No valid data
8 WR_XFER_ACTIVE R 0h

Write Transfer Active (SD Mode Only)

This status indicates a write transfer is active. If this bit is 0h, it means no valid write data exists in the HC. This bit is set in either of the following cases:

After the end bit of the write command.

When writing a 1h to the MMCSD1_BLOCK_GAP_CONTROL[1] CONTINUE bit to restart a write transfer.

This bit is cleared in either of the following cases:

After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple).

After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0h, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy.

1h: Transferring data

0h: No valid data
7 SDIF_DAT7IN R 0h

DAT[7] Line Signal Level (Embedded Only)

This status is used to check DAT line level to recover from errors, and for debugging.

D07 - DAT[7]
6 SDIF_DAT6IN R 0h

DAT[6] Line Signal Level (Embedded Only)

This status is used to check DAT line level to recover from errors, and for debugging.

D06 - DAT[6]
5 SDIF_DAT5IN R 0h

DAT[5] Line Signal Level (Embedded Only)

This status is used to check DAT line level to recover from errors, and for debugging.

D05 - DAT[5]
4 SDIF_DAT4IN R 0h

DAT[4] Line Signal Level (Embedded Only)

This status is used to check DAT line level to recover from errors, and for debugging.

D04 - DAT[4]
3 RETUNING_REQ R 0h

Re-Tuning Request (UHS-I Only)

Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data.

This bit is cleared when a command is issued with setting the MMCSD1_HOST_CONTROL2[6] EXECUTE_TUNING bit.

Changing of this bit from 0h to 1h generates Re-Tuning Event.

This bit isn't set to 1h if the MMCSD1_HOST_CONTROL2[7] SAMPLING_CLK_SELECT bit is set to 0h (using fixed sampling clock).

1h: Sampling clock needs re-tuning

0h: Fixed or well tuned sampling clock
2 DATA_LINE_ACTIVE R 0h

DAT Line Active (SD Mode Only)

This bit indicates whether one of the DAT line on SD bus is in use.

1h: DAT line active

0h: DAT line inactive
1 INHIBIT_DAT R 0h

Command Inhibit (DAT) (SD Mode Only)

This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h. If this bit is 0h, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (for example R1b, R5b type). Changing from 1h to 0h generates a Transfer Complete interrupt in the MMCSD1_NORMAL_INTR_STS register.

Note: The SD Host Driver can save registers in the range of 04FB 0000h - 04FB 000Dh (04F9 8000h - 04F9 800Dh) for a suspend transaction after this bit has changed from 1h to 0h.

1h: Cannot issue command which uses the DAT line

0h: Can issue command which uses the DAT line
0 INHIBIT_CMD R 0h

Command Inhibit (CMD)

SD Mode:

If this bit is 0h, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the MMCSD1_COMMAND register is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1h.

Commands using only the CMD line can be issued if this bit is 0h. Changing from 1h to 0h generates a Command complete interrupt in the MMCSD1_NORMAL_INTR_STS register. If the HC cannot issuethe command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1h and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, Host Controller shall manage to issue two commands: CMD12 and a command set by the MMCSD1_COMMAND register.

UHS-II Mode:

This bit is 0h means that a command packet can be issued by the Host Controller. While this bit is set to 1h, which means the Host Controller is not ready to issue a next command, Host Driver shall not write the registers from the MMCSD1_UHS2_BLOCK_SIZE to the MMCSD1_UHS2_COMMAND. Changing from 1h to 0h generates a Command Complete Interrupt in the MMCSD1_NORMAL_INTR_STS register.

1h: Host Controller is not ready to issue a command

0h: Host Controller is ready to issue a command

Version 4.10 adds a new control to prevent error statuses from overwriting by receipt of a next command. This status keeps indicating 1h while any of response error statuses is set to 1h, Command Not Issued by Error in this register is set to 1h or the MMCSD1_AUTOCMD_ERR_STS[7] CMD_NOT_ISSUED bit is set to 1h. Software Reset For CMD Lineis used to clear the error statuses above and this status (MMCSD1_SOFTWARE_RESET[1] SWRST_FOR_CMD).

Note: DAT line active indicates whether one of the DAT line is on SD bus is in use.

(a) In the case of read transactions

This status indicates whether a read transfer is executing on the SD Bus. Changing this value from 1h to 0h generates a Block Gap Event interrupt in the MMCSD1_NORMAL_INTR_STS register, as the result of the Stop At Block Gap Request being set.

This bit shall be set in either of the following cases:

(1) After the end bit of the read command.

(2) When writing a 1h to the MMCSD1_BLOCK_GAP_CONTROL[1] CONTINUE bit to restart a read transfer.

This bit shall be cleared in either of the following cases:

(1) When the end bit of the last data block is sent from the SD Bus to the Host Controller. In case of ADMA2, the last block is designated by the last transfer of Descriptor Table.

(2) When a read transfer is stopped at the block gap initiated by a Stop At Block Gap Request (MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP).

The Host Controller shall stop read operation at the start of the interrupt cycle of the next block gap by driving Read Wait or stopping SD clock. If the Read Wait signal is already driven (due to data buffer cannot receive data), the Host Controller can continue to stop read operation by driving the Read Wait signal. It is necessary to support Read Wait in order to use suspend/resume function.

(b) In the case of write transactions

This status indicates that a write transfer is executing on the SD Bus. Changing this value from 1h to 0h generate a Transfer Complete interrupt in the MMCSD1_NORMAL_INTR_STS register.

This bit shall be set in either of the following cases:

(1) After the end bit of the write command.

(2) When writing to 1h to the MMCSD1_BLOCK_GAP_CONTROL[1] CONTINUE bit to continue a write transfer.

This bit shall be cleared in either of the following cases:

(1) When the SD card releases write busy of the last data block. If SD card does not drive busy signal for 8 SD Clocks, the Host Controller shall consider the card drive "Not Busy". In case of ADMA2, the last block is designated by the last transfer of Descriptor Table.

(2) When the SD card releases write busy prior to waiting for write transfer as a result of a Stop At Block Gap Request (MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP).

(c) Command with busy

This status indicates whether a command indicates busy (for example erase command for memory) is executing on the SD Bus. This bit is set after the end bit of the command with busy and cleared when busy is de-asserted. Changing this bit from 1h to 0h generate a Transfer Complete interrupt in the MMCSD1_NORMAL_INTR_STS register.

Note:

The HD can issue cmd0, cmd12, cmd13 (for memory) and cmd52 (for SDIO) when the DAT lines are busy during data transfer. These commands can be issued when Command Inhibit (CMD) is set to zero (MMCSD1_PRESENTSTATE[0] INHIBIT_CMD = 0h). Other commands shall be issued when Command Inhibit (DAT) is set to zero (MMCSD1_PRESENTSTATE[1] INHIBIT_DAT = 0h).

3.6.8.12 MMCSD1_HOST_CONTROL1 Register (Offset = 28h) [reset = 0h]

MMCSD1_HOST_CONTROL1 is shown in Figure 14-7434 and described in Table 14-15092.

Return to Summary Table.

This register is used to program DMA modes, LED control, data transfer width, High Speed enable, card detect test level and signal selection.

Table 14-15091 MMCSD1_HOST_CONTROL1 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0028h
Figure 14-7434 MMCSD1_HOST_CONTROL1 Register
7 6 5 4 3 2 1 0
CD_SIG_SEL CD_TEST_LEVEL EXT_DATA_WIDTH DMA_SELECT HIGH_SPEED_ENA DATA_WIDTH LED_CONTROL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15092 MMCSD1_HOST_CONTROL1 Register Field Descriptions
Bit Field Type Reset Description
7 CD_SIG_SEL R/W 0h

Card Detect Signal Detection

This bit selects source for card detection.

1h: The card detect test level is selected

0h: SDCD# is selected (for normal use)
6 CD_TEST_LEVEL R/W 0h

Card Detect Test Level

This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not.

Generates (card ins or card removal) interrupt when the normal interrupt status enable bit is set.

1h: Card Inserted

0h: No Card
5 EXT_DATA_WIDTH R/W 0h

Extended Data Transfer Width (Embedded and SD Mode Only)

This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the MMCSD1_CAPABILITIES register. If a device supports 8-bit bus mode, this bit may be set to 1h. If this bit is 0h, bus width is controlled by the MMCSD1_HOST_CONTROL1[1] DATA_WIDTH bit.

This bit is not effective when multiple devices are installed on a bus slot (Slot Type is set to 2h in the MMCSD1_CAPABILITIES register). In this case, each device bus width is controlled by Bus Width Preset field in the Shared Bus register (MMCSD1_SHARED_BUS_CTRL_PTR).

1h: 8-bit Bus Width

0h: Bus Width is Selected by Data Transfer Width
4-3 DMA_SELECT R/W 0h

DMA Select

This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the MMCSD1_CAPABILITIES register. Selected DMA is enabled by the MMCSD1_TRANSFER_MODE[0] DMA_ENA bit in SD mode and the MMCSD1_UHS2_XFER_MODE[0] DMA_ENA bit in UHS-II mode.

(1) Up to Version 3.00:

When MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 0h, setting of this field is compatible to Host Controller Version 3.00.

SDMA is initiated by writing to the MMCSD1_COMMAND register when this field is set to 0h and the SDMA System Address register (32-bit) is used (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI). SDMA does not support 64-bit addressing.

ADMA2 is initiated by writing to the MMCSD1_COMMAND register when this field is set to 2h or 3h. Lower 32-bit of the ADMA System Address register (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI) is used when this field is set to 2h and 64-bit of the ADMA System Address register is used when this field is set to 3h. Support of 64-bit System Addressing is indicated by the MMCSD1_CAPABILITIES[28] ADDR_64BIT_SUPPORT_V3 bit. 64-bit AMDA2 uses 96-bit Descriptor.

0h: SDMA is selected

1h: 32-bit Address ADMA1 is selected

2h: 32-bit Address ADMA2 is selected

3h: 64-bit Address ADMA2 is selected (Optional)

(2) Version 4.00 or later:

When the MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h, setting of this field is changed as follows.

SDMA is initiated by Host Driver writes to the MMCSD1_COMMAND register when this field is set to 0h.

ADMA2 is initiated by Host Driver writes to the MMCSD1_COMMAND register when this field is set to 2h or 3h and by ADMA3 sets to the ADMA System Address register (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI) when this field is set to 3h.

ADMA3 is initiated by Host Driver writes to the MMCSD1_ADMA3_DESC_ADDRESS register when this field is set to 3h.

0h: SDMA is selected

1h: Not Used (New assignment is not allowed)

2h: ADMA2 is selected (AMDA3 is not supported or disabled)

3h: ADMA2 or ADMA3 is selected

Support of 64-bit DMA and 128-bit Descriptor is indicated by the MMCSD1_CAPABILITIES[27] ADDR_64BIT_SUPPORT_V4 bit. If the support bit is set to 1h, all supported DMAs (depends on Support, ADMA2 Support and ADMA3 Support) shall support 64-bit addressing. The MMCSD1_HOST_CONTROL2[13] BIT64_ADDRESSING bit selects either 32-bit or 64-bit system addressing of DMAs.
2 HIGH_SPEED_ENA R/W 0h

High Speed Enable (SD Mode Only)

This bit is optional. Before setting this bit, the HD shall check the MMCSD1_CAPABILITIES[21] HIGH_SPEED_SUPPORT bit. If this bit is set to 0h (default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/20 MHz for MMC). If this bit is set to 1h, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52 MHz for MMC)/208 MHz (for SD3.0).

If the MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA bit is set to 1h, Host Driver needs to reset SD Clock Enable (MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA) before changing this field to avoid generating clock glitches. After setting this field, the Host Driver sets SD Clock Enable again. This bit is not effective in UHS-II mode.

1h: High Speed Mode

0h: Normal Speed Mode
1 DATA_WIDTH R/W 0h

Data Transfer Width (SD Mode Only)

This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode.

1h: 4 bit mode

0h: 1 bit mode
0 LED_CONTROL R/W 0h

LED Control

This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction.

1h: LED on

0h: LED off

3.6.8.13 MMCSD1_POWER_CONTROL Register (Offset = 29h) [reset = 0h]

MMCSD1_POWER_CONTROL is shown in Figure 14-7435 and described in Table 14-15094.

Return to Summary Table.

This register is used to program the SD Bus power and voltage level.

Table 14-15093 MMCSD1_POWER_CONTROL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0029h
Figure 14-7435 MMCSD1_POWER_CONTROL Register
7 6 5 4 3 2 1 0
UHS2_VOLTAGE UHS2_POWER SD_BUS_VOLTAGE SD_BUS_POWER
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15094 MMCSD1_POWER_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-5 UHS2_VOLTAGE R/W 0h

SD Bus Voltage Select for VDD2 (UHS-II Only)

This field determines supply voltage range to VDD2. This field can be set to 5h if the MMCSD1_CAPABILITIES[60] VDD2_1P8_SUPPORT bit is set to 1h.

111b: Not used

110b: Not used

101b: 1.8 V

100b: Reserved for 1.2 V

011b – 001b: Reserved

000b: VDD2 Not Supported
4 UHS2_POWER R/W 0h

SD Bus Power for VDD2 (UHS-II Only)

Setting this bit enables providing VDD2.

1h: Power on

0h: Power off
3-1 SD_BUS_VOLTAGE R/W 0h

SD Bus Voltage Select for VDD1

By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits in the MMCSD1_CAPABILITIES register. If an unsupported voltage is selected, the Host System shall not supply SD bus voltage.

111b: 3.3 V (Flattop.)

110b: 3.0 V (Typ.)

101b: 1.8 V (Typ.) for Embedded

100b – 000b: Reserved
0 SD_BUS_POWER R/W 0h

SD Bus Power for VDD1

Before setting this bit, the SD host driver shall set SD Bus Voltage Select (MMCSD1_POWER_CONTROL[3-1] SD_BUS_VOLTAGE). If the HC detects the No Card State, this bit shall be cleared.

If this bit is cleared, the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state), and drive SDCLK to low level. If card is connected to Host Controller, Host Controller shall set these lines to low before stopping to supply VDD1.

In UHS-II mode, before clearing this bit, Host Driver shall clear the MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA bit and before stopping to supply VDD1, Host Controller shall set DAT[2] to low if DAT[2] is used as out-of band interrupt.

1h: Power on

0h: Power off

3.6.8.14 MMCSD1_BLOCK_GAP_CONTROL Register (Offset = 2Ah) [reset = 80h]

MMCSD1_BLOCK_GAP_CONTROL is shown in Figure 14-7436 and described in Table 14-15096.

Return to Summary Table.

This register is used to program the block gap request, read wait control and interrupt at block gap.

Table 14-15095 MMCSD1_BLOCK_GAP_CONTROL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 002Ah
Figure 14-7436 MMCSD1_BLOCK_GAP_CONTROL Register
7 6 5 4 3 2 1 0
BOOT_ACK_ENA ALT_BOOT_MODE BOOT_ENABLE RESERVED INTRPT_AT_BLK_GAP RDWAIT_CTRL CONTINUE STOP_AT_BLK_GAP
R/W-1h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15096 MMCSD1_BLOCK_GAP_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7 BOOT_ACK_ENA R/W 1h

Boot Acknowledge Check

To check for the boot acknowledge in boot operation.

1h: Wait for boot ack from eMMC card

0h: Will not wait for boot ack from eMMC card
6 ALT_BOOT_MODE R/W 0h

Alternative Boot Mode

To start boot code access in alternative mode.

1h: To start alternate boot mode access

0h: To stop alternate boot mode access
5 BOOT_ENABLE R/W 0h

Boot Enable

To start boot code access.

1h: To start boot code access

0h: To stop boot code access
4 RESERVED R 0h

Reserved
3 INTRPT_AT_BLK_GAP R/W 0h

Interrupt At Block Gap (SD Mode Only)

This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1h enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0h. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card.
2 RDWAIT_CTRL R/W 0h

Read Wait Control (SD Mode Only)

The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1h otherwise DAT line conflict may occur. If this bit is set to 0h, Suspend/Resume cannot be supported.

In UHS-II mode, Read Wait is disabled and DAT[2] line is used for Interrupt Signal from UHS-II Card.

1h: Enable Read Wait Control

0h: Disable Read Wait Control
1 CONTINUE R/W 0h

Continue Request

This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0h (MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP = 0h) and set this bit to restart the transfer.

The Host Controller automatically clears this bit when the transaction re-starts.

If MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP = 1h, any write to this bit is ignored.

In SD mode, this bit is cleared in either of the following cases:

1) In the case of a read transaction, the DAT Line Active changes from 0h to 1h as a read transaction restarts.

2) In the case of a write transaction, the Write transfer active changes from 0h to 1h as the write transaction restarts.

Therefore it is not necessary for Host driver to set this bit to 0h. If MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP = 1h, any write to this bit is ignored.

1h: Restart

0h: Ignored
0 STOP_AT_BLK_GAP R/W 0h

Stop At Block Gap Request

This bit is used to stop executing a transaction at the next block gap for non-DMA, SDMA and ADMA transfers. Until the transfer complete is set to 1h, indicating a transfer completion the HD shall leave this bit set to 1h.

Clearing both the MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP and MMCSD1_BLOCK_GAP_CONTROL[1] CONTINUE bits shall not cause the transaction to restart. The MMCSD1_BLOCK_GAP_CONTROL[2] RDWAIT_CTRL bit is used to stop the read transaction at the block gap. The HC shall honour Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the HD shall not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1h (MMCSD1_BLOCK_GAP_CONTROL[2] RDWAIT_CTRL) = 1h). In case of write transfers in which the HD writes data to the MMCSD1_DATA_PORT register, the HD shall set this bit after all block data is written. If this bit is set to 1h, the HD shall not write data to the MMCSD1_DATA_PORT register. This bit affects Read Transfer Active, Write Transfer Active, DAT line active and Command Inhibit (DAT) in the MMCSD1_PRESENTSTATE register.

In case of UHS-II, a transaction can be stopped at the boundary of DATA Burst (Flow Control basis). Host Controller waits for sending Flow Control MSG until the MMCSD1_BLOCK_GAP_CONTROL[1] CONTINUE bit is set to 1h.

1h: Stop

0h: Transfer

There are three cases to restart the transfer after stop at the block gap. Which case is appropriate depends on whether the HC issues a Suspend command or the SD card accepts the Suspend command.

1. If the HD does not issue Suspend command, the Continue Request shall be used to restart the transfer.

2. If the HD issues a Suspend command and the SD card accepts it, a Resume Command shall be used to restart the transfer.

3. If the HD issues a Suspend command and the SD card does not accept it, the Continue Request shall be used to restart the transfer.

Any time Stop At Block Gap Request stops the data transfer, the HD shall wait for Transfer Complete (in the MMCSD1_NORMAL_INTR_STS register) before attempting to restart the transfer. When restarting the data transfer by Continue Request, the HD shall clear Stop At Block Gap Request before or simultaneously.

Host Controller should not generate timeout interrupts while Stop At Block Gap is set. Host Driver should ignore timeout interrupts while Stop At Block Gap is set.

3.6.8.15 MMCSD1_WAKEUP_CONTROL Register (Offset = 2Bh) [reset = 0h]

MMCSD1_WAKEUP_CONTROL is shown in Figure 14-7437 and described in Table 14-15098.

Return to Summary Table.

This register is used to program the wakeup functionality.

The MMCSD1_WAKEUP_CONTROL register is mandatory for the HC, but wakeup functionality depends on the HC system hardware and software. The HD shall maintain voltage on the SD Bus, by setting the MMCSD1_POWER_CONTROL[0] SD_BUS_POWER bit to 1h, when wakeup event via card interrupt is desired.

Table 14-15097 MMCSD1_WAKEUP_CONTROL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 002Bh
Figure 14-7437 MMCSD1_WAKEUP_CONTROL Register
7 6 5 4 3 2 1 0
RESERVED CARD_REMOVAL CARD_INSERTION CARD_INTERRUPT
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15098 MMCSD1_WAKEUP_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 0h

Reserved
2 CARD_REMOVAL R/W 0h

Wakeup Event Enable On SD Card Removal

This bit enables wakeup event via Card removal assertion in the MMCSD1_NORMAL_INTR_STS register.

FN_WUS (Wake up Support) in CIS does not affect this bit.

1h: Enable

0h: Disable
1 CARD_INSERTION R/W 0h

Wakeup Event Enable On SD Card Insertion

This bit enables wakeup event via Card Insertion assertion in the MMCSD1_NORMAL_INTR_STS register.

FN_WUS (Wake up Support) in CIS does not affect this bit.

1h: Enable

0h: Disable
0 CARD_INTERRUPT R/W 0h

Wakeup Event Enable On Card Interrupt

This bit enables wakeup event via Card Interrupt assertion in the MMCSD1_NORMAL_INTR_STS register.

This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h.

1h: Enable

0h: Disable

3.6.8.16 MMCSD1_CLOCK_CONTROL Register (Offset = 2Ch) [reset = 0h]

MMCSD1_CLOCK_CONTROL is shown in Figure 14-7438 and described in Table 14-15100.

Return to Summary Table.

This register is used to program the Clock frequency select, Clock generator select, Clock enable, Internal clock state fields.

At the initialization of the HC, the HD shall set the SDCLK Frequency Select (MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL) according to the MMCSD1_CAPABILITIES register. This register controls SDCLK in SD Mode and RCLK in UHS-II mode.

Table 14-15099 MMCSD1_CLOCK_CONTROL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 002Ch
Figure 14-7438 MMCSD1_CLOCK_CONTROL Register
15 14 13 12 11 10 9 8
SDCLK_FRQSEL
R/W-0h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL_UPBITS CLKGEN_SEL RESERVED PLL_ENA SD_CLK_ENA INT_CLK_STABLE INT_CLK_ENA
R/W-0h R/W-0h R-0h R/W-0h R/W-0h R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15100 MMCSD1_CLOCK_CONTROL Register Field Descriptions
Bit Field Type Reset Description
15-8 SDCLK_FRQSEL R/W 0h

SDCLK/RCLK Frequency Select

This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the Capabilities register (MMCSD1_CAPABILITIES[15-8] BASE_CLK_FREQ).

Only the following settings are allowed.

(1) 8-bit Divided Clock Mode:

80h: base clock divided by 256

40h: base clock divided by 128

20h: base clock divided by 64

10h: base clock divided by 32

08h: base clock divided by 16

04h: base clock divided by 8

02h: base clock divided by 4

01h: base clock divided by 2

00h: base clock (10 MHz - 63 MHz)

Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the most significant bit is used as the divisor. But multiple bits should not be set. The three default divider values can be calculated by the frequency that is defined by the MMCSD1_CAPABILITIES[15-8] BASE_CLK_FREQ bit field.

400 KHz divider value

25 MHz divider value

50 MHz divider value

According to the Physical Layer Specification, the maximum SD Clock frequency is 25 MHz in normal speed mode and 50 MHz in high speed mode, and shall never exceed this limit.

The frequency of SDCLK is set by the following formula:

Clock Frequency = (Base Clock) / divisor

Thus, choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency.

For example, if the MMCSD1_CAPABILITIES[15-8] BASE_CLK_FREQ bit field has the value 33 MHz, and the target frequency is 25 MHz, then choosing the divisor value of 1h will yield 16.5 MHz, which is the nearest frequency less than or equal to the target. Similarly, to approach a clock value of 400 KHz, the divisor value of 40h yields the optimal clock value of 258 KHz.

(2) 10-bit Divided Clock Mode:

Host Controller Version 3.00 or later supports this mandatory mode instead of the 8-bit Divided Clock Mode. The length of divider is extended to 10 bits and all divider values shall be supported.

3FFh: 1/2046 Divided Clock

N: 1/2N Divided Clock (Duty 50%)

002h: 1/4 Divided Clock

001h: 1/2 Divided Clock

000h: Base Clock (10 MHz - 254 MHz)

(3) Programmable Clock Mode:

Host Controller Version 3.00 or later supports this mode as optional. A non-zero value set to the MMCSD1_CAPABILITIES[55-48] CLOCK_MULTIPLIER bit field indicates support of this clock mode. The multiplier enables the Host System to select a finer grain SD clock frequency. It is not necessary to support all frequency generation specified by this field because programmable clock generator is vendor specific and dependent on the implementation. Therefore, this mode is used with Preset Value registers (MMCSD1_PRESET_VALUE0 - MMCSD1_PRESET_VALUE10). The Host Controller vendor provides possible settings and the Host System vendor sets appropriate values to the Preset Value registers (MMCSD1_PRESET_VALUE0 - MMCSD1_PRESET_VALUE10).

3FFh - Base Clock × M / 1024

........... .......................

N-1 - Base Clock × M / N

........... .......................

002h - Base Clock × M / 3

001h - Base Clock × M / 2

000h - Base Clock × M

This field depends on setting of the MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA bit.

If MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA = 0h, this field is set by Host Driver.

If MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA = 1h, this field is automatically set to a value specified in one of Preset Value registers (MMCSD1_PRESET_VALUE0 - MMCSD1_PRESET_VALUE10).
7-6 SDCLK_FRQSEL_UPBITS R/W 0h

Upper Bits of SDCLK/RCLK Frequency Select

This bit field is assigned to the MMCSD1_CLOCK_CONTROL[9-8] SDCLK_FRQSEL bit field of clock divider in SDCLK/RCLK Frequency Select.
5 CLKGEN_SEL R/W 0h

Clock Generator Select

This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select (MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL).

If the Programmable Clock Mode is supported (non-zero value is set to the MMCSD1_CAPABILITIES[55-48] CLOCK_MULTIPLIER bit field), this bit attribute is R/W, and if not supported, this bit attribute is RO and zero is read.

This bit depends on the setting of the MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA bit.

If MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA = 0h, this bit is set by Host Driver.

If MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA = 1h, this bit is automatically set to a value specified in one of Preset Value registers (MMCSD1_PRESET_VALUE0 - MMCSD1_PRESET_VALUE10).

1h: Programmable Clock Mode

0h: Divided Clock Mode
4 RESERVED R 0h

Reserved
3 PLL_ENA R/W 0h

PLL Enable

This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable (MMCSD1_CLOCK_CONTROL[0] INT_CLK_ENA) and PLL Enable and to minimize output latency (for example SDCLK/RCLK, D0 lane) from SD Clock Enable (MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA). There are two modes to keep Host Drivers compatibility. In both modes, PLL Locked timing is indicated by Internal Clock Stable (MMCSD1_CLOCK_CONTROL[1] INT_CLK_STABLE).

(1) When MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 0h (Host Driver Version 3, which does not support this bit) or this bit is not implemented, the MMCSD1_CLOCK_CONTROL[0] INT_CLK_ENA bit (or the MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA bit) may activate PLL (exit low power mode and start locking clock).

(2) When MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 1h (Host Driver Version 4), the MMCSD1_CLOCK_CONTROL[0] INT_CLK_ENA bit is set before setting this bit and then setting this bit may activate PLL (exit low power mode and start locking clock).

1h: PLL is enabled

0h: PLL is in low power mode
2 SD_CLK_ENA R/W 0h

SD Clock Enable

The HC shall stop SDCLK when writing this bit to 0h. The MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field can be changed when this bit is 0h. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared.

1h: Enable providing SDCLK or RCLK

0h: Disable providing SDCLK or RCLK
1 INT_CLK_STABLE R 0h

Internal Clock Stable

This bit is set to 1h when SD clock is stable after writing 1h to MMCSD1_CLOCK_CONTROL[0] INT_CLK_ENA bit. The SD Host Driver shall wait to set the MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA bit until this bit is set to 1h.

Note: This is useful when using PLL for a clock oscillator that requires setup time.

(1) Internal Clock Stable (when MMCSD1_CLOCK_CONTROL[3] PLL_ENA = 0h or not supported)

This bit is set to 1h when internal clock is stable after writing 1h to MMCSD1_CLOCK_CONTROL[0] INT_CLK_ENA bit.

(2) PLL Clock Stable (when MMCSD1_CLOCK_CONTROL[3] PLL_ENA = 1h)

Host Controller which supports PLL Enable sets this status to 0h once when PLL Enable is changed 0h to 1h and then this status is set to 1h when PLL is locked (PLL uses an internal clock in stable as a reference clock which is enabled by the MMCSD1_CLOCK_CONTROL[0] INT_CLK_ENA bit). After this bit is set to 1h, Host Driver may set the MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA bit.

1h: Ready

0h: Not Ready
0 INT_CLK_ENA R/W 0h

Internal Clock Enable

This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1h. When clock oscillation is stable, the HC shall set the MMCSD1_CLOCK_CONTROL[1] INT_CLK_STABLE bit to 1h. This bit shall not affect card detection.

1h: Oscillate

0h: Stop

3.6.8.17 MMCSD1_TIMEOUT_CONTROL Register (Offset = 2Eh) [reset = 0h]

MMCSD1_TIMEOUT_CONTROL is shown in Figure 14-7439 and described in Table 14-15102.

Return to Summary Table.

The register sets the data timeout counter value.

At the initialization of the HC, the HD shall set the Data Timeout Counter Value according to the MMCSD1_CAPABILITIES register.

Table 14-15101 MMCSD1_TIMEOUT_CONTROL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 002Eh
Figure 14-7439 MMCSD1_TIMEOUT_CONTROL Register
7 6 5 4 3 2 1 0
RESERVED COUNTER_VALUE
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15102 MMCSD1_TIMEOUT_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h

Reserved
3-0 COUNTER_VALUE R/W 0h

Data Timeout Counter Value

This value determines the interval by which DAT line time-outs are detected. Refer to the MMCSD1_ERROR_INTR_STS[4] DATA_TIMEOUT bit for information on factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the SD clock TMCLK by this value. When setting this register, prevent inadvertent time-out events by clearing the MMCSD1_ERROR_INTR_STS[4] DATA_TIMEOUT bit.

1111: Reserved

1110: TMCLK × 227

--------------------

--------------------

0001: TMCLK × 214

0000: TMCLK × 213

3.6.8.18 MMCSD1_SOFTWARE_RESET Register (Offset = 2Fh) [reset = 0h]

MMCSD1_SOFTWARE_RESET is shown in Figure 14-7440 and described in Table 14-15104.

Return to Summary Table.

This register is used to program the software reset for data, command and for all.

A reset pulse is generated when writing 1h to each bit of this register. After completing the reset, the HC shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are 0h.

Table 14-15103 MMCSD1_SOFTWARE_RESET Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 002Fh
Figure 14-7440 MMCSD1_SOFTWARE_RESET Register
7 6 5 4 3 2 1 0
RESERVED SWRST_FOR_DAT SWRST_FOR_CMD SWRST_FOR_ALL
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15104 MMCSD1_SOFTWARE_RESET Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 0h

Reserved
2 SWRST_FOR_DAT R/W 0h

Software Reset for DAT Line (SD Mode Only)

Only part of data circuit is reset. The following registers and bits are cleared by this bit:

MMCSD1_DATA_PORT

Buffer is cleared and Initialized.

MMCSD1_PRESENTSTATE

Buffer read Enable

Buffer write Enable

Read Transfer Active

Write Transfer Active

DAT Line Active

Command Inhibit (DAT)

MMCSD1_BLOCK_GAP_CONTROL

Continue Request

Stop At Block Gap Request

MMCSD1_NORMAL_INTR_ST

Buffer Read Ready

Buffer Write Ready

Block Gap Event

Transfer Complete

1h: Reset

0h: Work
1 SWRST_FOR_CMD R/W 0h

Software Reset for CMD Line (SD Mode Only)

Only part of command circuit is reset to be able to issue a command. From Version 4.10, this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit (including response error statuses related to Command Inhibit (CMD) control - MMCSD1_PRESENTSTATE[0] INHIBIT_CMD bit) and does not affect data transfer circuit. Host Controller can continue data transfer even this reset is executed during handling of sub command response errors.

The following registers and bits are cleared by this bit:

MMCSD1_PRESENTSTATE register:

Command Inhibit (CMD)

MMCSD1_NORMAL_INTR_STS register:

Command Complete

MMCSD1_ERROR_INTR_STS register (Error Interrupt Status from Version 4.10)

Response error statuses related to Command Inhibit (CMD) - MMCSD1_PRESENTSTATE[0] INHIBIT_CMD bit

1h: Reset

0h: Work
0 SWRST_FOR_ALL R/W 0h

Software Reset for All

This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0h. During its initialization, the HD shall set this bit to 1h to reset the HC. The HC shall reset this bit to 0h when Capabilities registers are valid and the HD can read them. Additional use of 'Software Reset For All' may not affect the value of the Capabilities registers. If this bit is set to 1h, the SD card shall reset itself and must be re-initialized by the HD.

1h: Reset

0h: Work

3.6.8.19 MMCSD1_NORMAL_INTR_STS Register (Offset = 30h) [reset = 0h]

MMCSD1_NORMAL_INTR_STS is shown in Figure 14-7441 and described in Table 14-15106.

Return to Summary Table.

This register gives the status of all the interrupts.

The Normal Interrupt Signal Enable (see MMCSD1_NORMAL_INTR_SIG_ENA register) affects read of this register, but Normal Interrupt Signal does not affect these reads. An Interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1h. For all bits except Card Interrupt (MMCSD1_NORMAL_INTR_STS[8] CARD_INTR) and Error Interrupt (MMCSD1_NORMAL_INTR_STS[15] ERROR_INTR), writing 1h to a bit clears it. The MMCSD1_NORMAL_INTR_STS[8] CARD_INTR bit is cleared when the card stops asserting the interrupt: that is when the Card Driver services the Interrupt condition.

Table 14-15105 MMCSD1_NORMAL_INTR_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0030h
Figure 14-7441 MMCSD1_NORMAL_INTR_STS Register
15 14 13 12 11 10 9 8
ERROR_INTR BOOT_COMPLETE RCV_BOOT_ACK RETUNING_EVENT INTC INTB INTA CARD_INTR
R-0h R/W1C-0h R/W1C-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
CARD_REM CARD_INS BUF_RD_READY BUF_WR_READY DMA_INTERRUPT BLK_GAP_EVENT XFER_COMPLETE CMD_COMPLETE
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 14-15106 MMCSD1_NORMAL_INTR_STS Register Field Descriptions
Bit Field Type Reset Description
15 ERROR_INTR R 0h

Error Interrupt

If any of the bits in the MMCSD1_ERROR_INTR_STS register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first.

In UHS-II mode is enabled, if any of the bits in the MMCSD1_UHS2_ERR_INTR_STS register are set, this bit is also set.

0h: No Error

1h: Error
14 BOOT_COMPLETE R/W1C 0h

Boot Terminate Interrupt

This status is set if the boot operation gets terminated.

0h: Boot operation is not terminated

1h: Boot operation is terminated
13 RCV_BOOT_ACK R/W1C 0h

Boot Acknowledge Receive

This status is set if the boot acknowledge is received from device.

0h: Boot acknowledge is not received

1h: Boot acknowledge is received
12 RETUNING_EVENT R 0h

Re-Tuning Event (UHS-I Only)

This status is set if the MMCSD1_PRESENTSTATE[3] RETUNING_REQ bit changes from 0h to 1h.

Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer (not large block count) can be completed without re-tuning.

In UHS-II mode, this bit is not effective.

1h: Re-Tuning should be performed

0h: Re-Tuning is not required
11 INTC R 0h

int_c (Embedded)

This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_C interrupt factor.
10 INTB R 0h

int_b (Embedded)

This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_B interrupt factor.
9 INTA R 0h

int_a (Embedded)

This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_A interrupt factor.
8 CARD_INTR R 0h

Card Interrupt

When this status has been set and the Host Driver needs to start this interrupt service, the MMCSD1_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit may be set to 0h in order to clear the card interrupt status latched in the Host Controller and to stop driving the interrupt signal to the Host System. After completion of the card interrupt service (it should reset interrupt factors in the SD card and the interrupt signal may not be asserted), set the MMCSD1_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit to 1h and start sampling the interrupt signal again.

Writing this bit to 1h does not clear this bit. It is cleared by resetting the SD card interrupt factor.

(1) DAT[1] Interrupt Input in SD Mode

In 1-bit mode, the Host Controller shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the SD card and the interrupt to the Host System. Interrupt detected by DAT[1] is supported when there is a card per slot. In case of UHS-I mode, switching time of Interrupt Period is relaxed for 2 clock cycles. Then Host Controller needs to delay start of interrupt sampling at least 2 clocks and should sample interrupt while Interrupt Period is stable.

(2) DAT[2] Interrupt Input in UHS-II Mode

When the MMCSD1_PRESENTSTATE[16] CARD_INSERTED and MMCSD1_POWER_CONTROL[0] SD_BUS_POWER bits are set to 1h, Host Controller configures DAT[2] as Interrupt Input and enables pull-up of DAT[2]. DAT[2] interrupt is asynchronous to RCLK, low level sensitive and 3.3 V signal level. DAT[2] interrupt is masked by setting the MMCSD1_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit to 0h. When either the MMCSD1_PRESENTSTATE[16] CARD_INSERTED bit or the MMCSD1_POWER_CONTROL[0] SD_BUS_POWER bit is set to 0h, Host Controller sets DAT[2] to low. Only point to point connection is allowed between Host and Card.

(3) INT MSG in UHS-II Mode

INT MSG is enabled by setting the MMCSD1_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit. DAT[2] and INT MSG interrupt sources are ORed and indicated to Card Interrupt. If any bit in the MMCSD1_UHS2_DEVICE_INTR_STATUS register is set to 1h, INT MSG interrupt is generated. INT MSG interrupt is cleared by writing a correspondent bit to 1h in the MMCSD1_UHS2_DEVICE_INTR_STATUS register. Masking DAT[2] interrupt also disables INT MSG interupt due to the MMCSD1_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit is set to 0h. SDIO Version 4.00 does not support INT MSG.

1h: Generate Card Interrupt

0h: No Card Interrupt
7 CARD_REM R/W1C 0h

Card Removal

This status is set if the MMCSD1_PRESENTSTATE[16] CARD_INSERTED bit changes from 1h to 0h. When the HD writes this bit to 1h to clear this status the status of the MMCSD1_PRESENTSTATE[16] CARD_INSERTED bit should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.

0h: Card State Stable or Debouncing

1h: Card Removed
6 CARD_INS R/W1C 0h

Card Insertion

This status is set if the MMCSD1_PRESENTSTATE[16] CARD_INSERTED bit changes from 0h to 1h. When the HD writes this bit to 1h to clear this status the status of the MMCSD1_PRESENTSTATE[16] CARD_INSERTED bit should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.

0h: Card State Stable or Debouncing

1h: Card Inserted
5 BUF_RD_READY R/W1C 0h

Buffer Read Ready

This status is set if the MMCSD1_PRESENTSTATE[11] BUF_RD_ENA bit changes from 0h to 1h.

The MMCSD1_PRESENTSTATE[11] BUF_RD_ENA bit is set to 1h for every CMD19 execution in tuning procedure.

In UHS-II mode, this bit is set at FC (Flow Control) unit basis.

0h: Not Ready to read Buffer

1h: Ready to read Buffer
4 BUF_WR_READY R/W1C 0h

Buffer Write Ready

This status is set if the MMCSD1_PRESENTSTATE[10] BUF_WR_ENA bit changes from 0h to 1h.

In UHS-II mode, this bit is set at FC (Flow Control) unit basis.

0h: Not Ready to Write Buffer

1h: Ready to Write Buffer
3 DMA_INTERRUPT R/W1C 0h

DMA Interrupt

This status is set if the HC detects the Host DMA Buffer Boundary in the MMCSD1_BLOCK_SIZE regiser.

0h: No DMA Interrupt

1h: DMA Interrupt is Generated
2 BLK_GAP_EVENT R/W1C 0h

Block Gap Event

If the MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP bit is set, this bit is set.

Read Transaction:

This bit is set at the falling edge of the DAT Line Active Status (see MMCSD1_PRESENTSTATE[2] DATA_LINE_ACTIVE bit). When the transaction is stopped at SD Bus timing. The Read Wait must be supported in order to use this function.

Write Transaction:

This bit is set at the falling edge of Write Transfer Active Status (see MMCSD1_PRESENTSTATE[8] WR_XFER_ACTIVE bit). After getting CRC status at SD Bus timing. In UHS-II mode, this bit is set at FC (Flow Control) unit basis.

0h: No Block Gap Event

1h: Transaction stopped at Block Gap
1 XFER_COMPLETE R/W1C 0h

Transfer Complete

This bit is set when a read/write transaction is completed.

SD Mode

Read Transaction:

This bit is set at the falling edge of Read Transfer Active Status (MMCSD1_PRESENTSTATE[9] RD_XFER_ACTIVE).

There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (after the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP bit (after valid data has been read to the Host System).

Write Transaction:

This bit is set at the falling edge of the DAT Line Active Status (see MMCSD1_PRESENTSTATE[2] DATA_LINE_ACTIVE bit). There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting the MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP bit and data transfers completed (after valid data is written to the SD card and the busy signal is released).

Note: MMCSD1_NORMAL_INTR_STS[1] XFER_COMPLETE bit has higher priority than the MMCSD1_ERROR_INTR_STS[4] DATA_TIMEOUT bit. If both bits are set to 1h, the data transfer can be considered complete.

Note: While performing tuning procedure (the MMCSD1_HOST_CONTROL2[6] EXECUTE_TUNING bit is set to 1h), the MMCSD1_NORMAL_INTR_STS[1] XFER_COMPLETE bit is not set to 1h.

Command with Busy:

This bit is set when busy is de-asserted. Refer to DAT Line Active and Command Inhibit (DAT) in the MMCSD1_PRESENTSTATE register.

UHS-I mode

While performing tuning procedure (the MMCSD1_HOST_CONTROL2[6] EXECUTE_TUNING bit is set to 1h), the MMCSD1_NORMAL_INTR_STS[1] XFER_COMPLETE bit is not set to 1h.

0h: No Data Transfer Complete

1h: Data Transfer Complete

UHS-II Mode

This interrupt is generated in following two cases:

(a) EBSY Completion (for EBSY supported commands)

When the MMCSD1_UHS2_XFER_MODE[14] EBSY_WAIT bit is set to 1h, this bit is set when EBSY packet has been received, and all valid data have been sent to system memory in case of read operation.

(b) Stop and Continue during DCMD Data Transfer

When the MMCSD1_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP bit is set to 1h and data transfer is stopped at the Flow Control.

Following is for both SD mode and UHS-II mode.

The table below shows that the MMCSD1_NORMAL_INTR_STS[1] XFER_COMPLETE bit has higher priority than the MMCSD1_ERROR_INTR_STS[4] DATA_TIMEOUT bit. If both bits are set to 1h, execution of a command can be considered to be completed.

1h: Command execution is completed

0h: Not complete
0 CMD_COMPLETE R/W1C 0h

Command Complete

SD Mode

This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23).

Note: The MMCSD1_ERROR_INTR_STS[0] CMD_TIMEOUT bit has higher priority than the MMCSD1_NORMAL_INTR_STS[0] CMD_COMPLETE bit. If both are set to 1h, it can be considered that the response was not received correctly.

Version 4.00 defines response check function for R1 and R5. If the MMCSD1_TRANSFER_MODE[8] RESP_INTR_DIS bit is set to 1h, generation of this interrupt is prohibited regardless of the MMCSD1_NORMAL_INTR_SIG_ENA[0] CMD_COMPLETE bit.

UHS-II Mode

If the MMCSD1_TRANSFER_MODE[8] RESP_INTR_DIS bit is set to 0h, this interrupt is generated when response packet is received.

If the MMCSD1_TRANSFER_MODE[8] RESP_INTR_DIS bit is set to 1h, generation of this interrupt is prohibited regardless of the MMCSD1_NORMAL_INTR_SIG_ENA[0] CMD_COMPLETE bit.

0h: No Command Complete

1h: Command Complete

Table 14-15107 shows the relation between transfer complete and data timeout error.

Table 14-15107 Relation between transfer complete and data timeout error
Transfer Complete Data Timeout Error Meaning of the Status
0 0 Interrupted by Another Factor
0 1 Timeout occur during transfer
1 Don't Care Data Transfer Complete

Table 14-15108 shows the relation between command complete and command timeout error.

Table 14-15108 Relation between command complete and command timeout error
Command Complete Command Timeout Error Meaning of the Status
0 0 Interrupted by Another Factor
Don't Care 1 Response not received within 64 SDCLK cycles
1 0 Response Received

3.6.8.20 MMCSD1_ERROR_INTR_STS Register (Offset = 32h) [reset = 0h]

MMCSD1_ERROR_INTR_STS is shown in Figure 14-7442 and described in Table 14-15110.

Return to Summary Table.

This register gives the status of the error interrupts.

Status defined in this register can be enabled by the MMCSD1_ERROR_INTR_STS_ENA register, but not by the MMCSD1_ERROR_INTR_SIG_ENA register. The Interrupt is generated when the MMCSD1_ERROR_INTR_SIG_ENA register is enabled and at least one of the statuses is set to 1h. Writing to 1h clears the bit and writing to 0h keeps the bit unchanged. More than one status can be cleared at the one register write.

Table 14-15109 MMCSD1_ERROR_INTR_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0032h
Figure 14-7442 MMCSD1_ERROR_INTR_STS Register
15 14 13 12 11 10 9 8
RESERVED HOST RESP RESERVED ADMA AUTO_CMD
R-0h R/W1C-0h R/W1C-0h R-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
CURR_LIMIT DATA_ENDBIT DATA_CRC DATA_TIMEOUT CMD_INDEX CMD_ENDBIT CMD_CRC CMD_TIMEOUT
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 14-15110 MMCSD1_ERROR_INTR_STS Register Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R 0h

Reserved
12 HOST R/W1C 0h

Target Response Error

Occurs when detecting ERROR in m_hresp (DMA transaction)

0h: No error

1h: Error
11 RESP R/W1C 0h

Response Error (SD Mode Only)

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If the MMCSD1_TRANSFER_MODE[7] RESP_ERR_CHK_ENA bit is set to 1h, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1h.

0h: No error

1h: Error
10 RESERVED R 0h

Reserved
9 ADMA R/W1C 0h

ADMA Error

This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the MMCSD1_ADMA_ERR_STATUS register.

0h: No error

1h: Error
8 AUTO_CMD R/W1C 0h

Auto CMD Error (SD Mode Only)

Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that any of the bits D00 to D05 in the MMCSD1_AUTOCMD_ERR_STS register has changed from 0h to 1h. D07 is effective in case of Auto CMD12. The MMCSD1_AUTOCMD_ERR_STS register is valid while this bit is set to 1h and may be cleared with clearing of this bit (another implementation is also allowed).

0h: No error

1h: Error
7 CURR_LIMIT R/W1C 0h

Current Limit Error

By setting the MMCSD1_POWER_CONTROL[0] SD_BUS_POWER bit, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1h means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function.

0h: No error

1h: Power Fail
6 DATA_ENDBIT R/W1C 0h

Data End Bit Error (SD Mode Only)

Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status.

0h: No error

1h: Error
5 DATA_CRC R/W1C 0h

Data CRC Error (SD Mode Only)

Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 2h.

0h: No error

1h: Error
4 DATA_TIMEOUT R/W1C 0h

Data Timeout Error (SD Mode Only)

Occurs when detecting one of following timeout conditions:

1. Busy Timeout for R1b, R5b type

2. Busy Timeout after Write CRC status

3. Write CRC status Timeout

4. Read Data Timeout

0h: No error

1h: Timeout
3 CMD_INDEX R/W1C 0h

Command Index Error (SD Mode Only)

Occurs if a Command Index error occurs in the Command Response (MMCSD1_RESPONSE_0 to MMCSD1_RESPONSE_7).

0h: No error

1h: Error
2 CMD_ENDBIT R/W1C 0h

Command End Bit Error (SD Mode Only)

Occurs when detecting that the end bit of a command response is 0h.

0h: No error

1h: End Bit Error Generated
1 CMD_CRC R/W1C 0h

Command CRC Error (SD Mode Only)

Command CRC Error is generated in two cases.

1. If a response is returned and the MMCSD1_ERROR_INTR_STS[0] CMD_TIMEOUT bit is set to 0h, this bit is set to 1h when detecting a CRT error in the command response.

2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command (Stop driving CMD line) and set this bit to 1h. The MMCSD1_ERROR_INTR_STS[0] CMD_TIMEOUT bit shall also be set to 1h to distinguish CMD line conflict.

0h: No error

1h: CRC Error Generated
0 CMD_TIMEOUT R/W1C 0h

Command Timeout Error (SD Mode Only)

Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case the MMCSD1_ERROR_INTR_STS[1] CMD_CRC bit shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC.

0h: No error

1h: Timeout

Table 14-15111 shows the relation between command CRC error and command time-out error.

Table 14-15111 Relation between command CRC error and command time-out error
Command CRC Error Command Time-out Error Kinds of Error
0 0 No Error
0 1 Response Timeout Error
1 0 Response CRC Error
1 1 CMD Line Conflict

3.6.8.21 MMCSD1_NORMAL_INTR_STS_ENA Register (Offset = 34h) [reset = 0h]

MMCSD1_NORMAL_INTR_STS_ENA is shown in Figure 14-7443 and described in Table 14-15113.

Return to Summary Table.

This register is used to enable the MMCSD1_NORMAL_INTR_STS register fields.

Table 14-15112 MMCSD1_NORMAL_INTR_STS_ENA Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0034h
Figure 14-7443 MMCSD1_NORMAL_INTR_STS_ENA Register
15 14 13 12 11 10 9 8
BIT15_FIXED0 BOOT_COMPLETE RCV_BOOT_ACK RETUNING_EVENT INTC INTB INTA CARD_INTERRUPT
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CARD_REMOVAL CARD_INSERTION BUF_RD_READY BUF_WR_READY DMA_INTERRUPT BLK_GAP_EVENT XFER_COMPLETE CMD_COMPLETE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15113 MMCSD1_NORMAL_INTR_STS_ENA Register Field Descriptions
Bit Field Type Reset Description
15 BIT15_FIXED0 R 0h

Fixed to 0

The HC shall control error Interrupts using the MMCSD1_ERROR_INTR_STS_ENA register.
14 BOOT_COMPLETE R/W 0h

Boot Terminate Interrupt Enable

0h: Masked

1h: Enabled
13 RCV_BOOT_ACK R/W 0h

Boot Acknowledge Enable

0h: Masked

1h: Enabled
12 RETUNING_EVENT R/W 0h

Re-Tuning Event Status Enable (UHS-I Only)

0h: Masked

1h: Enabled
11 INTC R/W 0h

INT_C Status Enable (Embedded)

If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts.
10 INTB R/W 0h

INT_B Status Enable (Embedded)

If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts.
9 INTA R/W 0h

INT_A Status Enable (Embedded)

If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts.
8 CARD_INTERRUPT R/W 0h

Card Interrupt Status Enable

If this bit is set to 0h, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1h. The HD may clear the MMCSD1_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit before servicing the Card Interrupt and may set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts.

By setting this bit to 0h, interrupt input should be masked by implementation so that the interrupt Input is not affected by external signal in any state (for example: floating).

0h: Masked

1h: Enabled
7 CARD_REMOVAL R/W 0h

Card Removal Status Enable

0h: Masked

1h: Enabled
6 CARD_INSERTION R/W 0h

Card Insertion Status Enable

0h: Masked

1h: Enabled
5 BUF_RD_READY R/W 0h

Buffer Read Ready Status Enable

0h: Masked

1h: Enabled
4 BUF_WR_READY R/W 0h

Buffer Write Ready Status Enable

0h: Masked

1h: Enabled
3 DMA_INTERRUPT R/W 0h

DMA Interrupt Status Enable

0h: Masked

1h: Enabled
2 BLK_GAP_EVENT R/W 0h

Block Gap Event Status Enable

0h: Masked

1h: Enabled
1 XFER_COMPLETE R/W 0h

Transfer Complete Status Enable

0h: Masked

1h: Enabled
0 CMD_COMPLETE R/W 0h

Command Complete Status Enable

0h: Masked

1h: Enabled

Note: The HC may sample the card Interrupt signal during interrupt period and may hold its value in the flip-flop. If the MMCSD1_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit is set to 0h, the HC shall clear all internal signals regarding Card Interrupt (MMCSD1_NORMAL_INTR_STS[8] CARD_INTR).

3.6.8.22 MMCSD1_ERROR_INTR_STS_ENA Register (Offset = 36h) [reset = 0h]

MMCSD1_ERROR_INTR_STS_ENA is shown in Figure 14-7444 and described in Table 14-15115.

Return to Summary Table.

This register is used to enable the MMCSD1_ERROR_INTR_STS register fields.

Table 14-15114 MMCSD1_ERROR_INTR_STS_ENA Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0036h
Figure 14-7444 MMCSD1_ERROR_INTR_STS_ENA Register
15 14 13 12 11 10 9 8
VENDOR_SPECIFIC RESP TUNING ADMA AUTO_CMD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CURR_LIMIT DATA_ENDBIT DATA_CRC DATA_TIMEOUT CMD_INDEX CMD_ENDBIT CMD_CRC CMD_TIMEOUT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15115 MMCSD1_ERROR_INTR_STS_ENA Register Field Descriptions
Bit Field Type Reset Description
15-12 VENDOR_SPECIFIC R/W 0h

Vendor Specific Error Status Enable

N/A
11 RESP R/W 0h

Response Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
10 TUNING R/W 0h

Tuning Error Status Enable (UHS-I Only)

0h: Masked

1h: Enabled
9 ADMA R/W 0h

ADMA Error Status Enable

0h: Masked

1h: Enabled
8 AUTO_CMD R/W 0h

Auto CMD Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
7 CURR_LIMIT R/W 0h

Current Limit Error Status Enable

0h: Masked

1h: Enabled
6 DATA_ENDBIT R/W 0h

Data End Bit Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
5 DATA_CRC R/W 0h

Data CRC Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
4 DATA_TIMEOUT R/W 0h

Data Timeout Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
3 CMD_INDEX R/W 0h

Command Index Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
2 CMD_ENDBIT R/W 0h

Command End Bit Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
1 CMD_CRC R/W 0h

Command CRC Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
0 CMD_TIMEOUT R/W 0h

Command Timeout Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled

Note: To Detect CMD Line conflict, the HD must set both MMCSD1_ERROR_INTR_STS_ENA[0] CMD_TIMEOUT and MMCSD1_ERROR_INTR_STS_ENA[1] CMD_CRC bits to 1h.

3.6.8.23 MMCSD1_NORMAL_INTR_SIG_ENA Register (Offset = 38h) [reset = 0h]

MMCSD1_NORMAL_INTR_SIG_ENA is shown in Figure 14-7445 and described in Table 14-15117.

Return to Summary Table.

Normal Interrupt Signal Enable Register

This register is used to select which interrupt status is indicated to the Host System as the Interrupt. These status bits all share the sample 1 bit interrupt line. Setting any of these bits to 1h enables Interrupt generation.

Table 14-15116 MMCSD1_NORMAL_INTR_SIG_ENA Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0038h
Figure 14-7445 MMCSD1_NORMAL_INTR_SIG_ENA Register
15 14 13 12 11 10 9 8
BIT15_FIXED0 BOOT_COMPLETE RCV_BOOT_ACK RETUNING_EVENT INTC INTB INTA CARD_INTERRUPT
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CARD_REMOVAL CARD_INSERTION BUF_RD_READY BUF_WR_READY DMA_INTERRUPT BLK_GAP_EVENT XFER_COMPLETE CMD_COMPLETE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15117 MMCSD1_NORMAL_INTR_SIG_ENA Register Field Descriptions
Bit Field Type Reset Description
15 BIT15_FIXED0 R 0h

Fixed to 0

The HD shall control error Interrupts using the MMCSD1_ERROR_INTR_SIG_ENA register.
14 BOOT_COMPLETE R/W 0h

Boot Terminate Interrupt Signal Enable

0h: Masked

1h: Enabled
13 RCV_BOOT_ACK R/W 0h

Boot Acknowledge Receive Signal Enable

0h: Masked

1h: Enabled
12 RETUNING_EVENT R/W 0h

Re-Tuning Event Signal Enable (UHS-I Only)

0h: Masked

1h: Enabled
11 INTC R/W 0h

INT_C Signal Enable (Embedded)

0h: Masked

1h: Enabled
10 INTB R/W 0h

INT_B Signal Enable (Embedded)

0h: Masked

1h: Enabled
9 INTA R/W 0h

INT_A Signal Enable (Embedded)

0h: Masked

1h: Enabled
8 CARD_INTERRUPT R/W 0h

Card Interrupt Signal Enable

0h: Masked

1h: Enabled
7 CARD_REMOVAL R/W 0h

Card Removal Signal Enable

0h: Masked

1h: Enabled
6 CARD_INSERTION R/W 0h

Card Insertion Signal Enable

0h: Masked

1h: Enabled
5 BUF_RD_READY R/W 0h

Buffer Read Ready Signal Enable

0h: Masked

1h: Enabled
4 BUF_WR_READY R/W 0h

Buffer Write Ready Signal Enable

0h: Masked

1h: Enabled
3 DMA_INTERRUPT R/W 0h

DMA Interrupt Signal Enable

0h: Masked

1h: Enabled
2 BLK_GAP_EVENT R/W 0h

Block Gap Event Signal Enable

0h: Masked

1h: Enabled
1 XFER_COMPLETE R/W 0h

Transfer Complete Signal Enable

0h: Masked

1h: Enabled
0 CMD_COMPLETE R/W 0h

Command Complete Signal Enable

0h: Masked

1h: Enabled

3.6.8.24 MMCSD1_ERROR_INTR_SIG_ENA Register (Offset = 3Ah) [reset = 0h]

MMCSD1_ERROR_INTR_SIG_ENA is shown in Figure 14-7446 and described in Table 14-15119.

Return to Summary Table.

Error Interrupt Signal Enable Register

This register is used to select which interrupt status is notified to the Host System as the Interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1h enables Interrupt generation.

Table 14-15118 MMCSD1_ERROR_INTR_SIG_ENA Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 003Ah
Figure 14-7446 MMCSD1_ERROR_INTR_SIG_ENA Register
15 14 13 12 11 10 9 8
VENDOR_SPECIFIC RESP TUNING ADMA AUTO_CMD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CURR_LIMIT DATA_ENDBIT DATA_CRC DATA_TIMEOUT CMD_INDEX CMD_ENDBIT CMD_CRC CMD_TIMEOUT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15119 MMCSD1_ERROR_INTR_SIG_ENA Register Field Descriptions
Bit Field Type Reset Description
15-12 VENDOR_SPECIFIC R/W 0h

Vendor Specific Error Signal Enable

N/A
11 RESP R/W 0h

Response Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
10 TUNING R/W 0h

Tuning Error Signal Enable (UHS-I Only)

0h: Masked

1h: Enabled
9 ADMA R/W 0h

ADMA Error Signal Enable

0h: Masked

1h: Enabled
8 AUTO_CMD R/W 0h

Auto CMD Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
7 CURR_LIMIT R/W 0h

Current Limit Error Signal Enable

0h: Masked

1h: Enabled
6 DATA_ENDBIT R/W 0h

Data End Bit Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
5 DATA_CRC R/W 0h

Data CRC Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
4 DATA_TIMEOUT R/W 0h

Data Timeout Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
3 CMD_INDEX R/W 0h

Command Index Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
2 CMD_ENDBIT R/W 0h

Command End Bit Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
1 CMD_CRC R/W 0h

Command CRC Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
0 CMD_TIMEOUT R/W 0h

Command Timeout Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled

3.6.8.25 MMCSD1_AUTOCMD_ERR_STS Register (Offset = 3Ch) [reset = 0h]

MMCSD1_AUTOCMD_ERR_STS is shown in Figure 14-7447 and described in Table 14-15121.

Return to Summary Table.

This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23.

The Host driver can determine what kind of Auto CMD12/CMD23 errors occur by this register. Auto CMD23 errors are indicated in bit 04-01. This register is valid only when the Auto CMD Error is set.

Table 14-15120 MMCSD1_AUTOCMD_ERR_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 003Ch
Figure 14-7447 MMCSD1_AUTOCMD_ERR_STS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CMD_NOT_ISSUED RESERVED INDEX ENDBIT CRC TIMEOUT ACMD12_NOT_EXEC
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15121 MMCSD1_AUTOCMD_ERR_STS Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h

Reserved
7 CMD_NOT_ISSUED R 0h

Command Not Issued By Auto CMD12 Error

Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register.

This bit is set to 0h when Auto CMD Error is generated by Auto CMD23.

0h: No Error

1h: Not Issued
6-5 RESERVED R 0h

Reserved
4 INDEX R 0h

Auto CMD Index Error

Occurs if the Command Index error occurs in response to a command.

0h: No Error

1h: Error
3 ENDBIT R 0h

Auto CMD End Bit Error

Occurs when detecting that the end bit of command response is 0h.

0h: No Error

1h: End Bit Error Generated
2 CRC R 0h

Auto CMD CRC Error

Occurs when detecting a CRC error in the command response.

0h: No Error

1h: CRC Error Generated
1 TIMEOUT R 0h

Auto CMD Timeout Error

Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.

If this bit is set to 1h, the other error status bits (D04 - D02) are meaningless.

0h: No Error

1h: Timeout
0 ACMD12_NOT_EXEC R 0h

Auto CMD12 not Executed

If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1h means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1h, other error status bits (D04 - D01) are meaningless.

This bit is set to 0h when Auto CMD Error is generated by Auto CMD23.

0h: Executed

1h: Not Executed

Table 14-15122 shows the relation between Auto CMD12 CRC error and Auto CMD12 timeout error.

Table 14-15122 Relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error
Auto Cmd12 CRC Error Auto CMD12 Timeout Error Kinds of Error
0 0 No Error
0 1 Response Timeout Error
1 0 Response CRC Error
1 1 CMD Line Conflict

The timing of changing Auto CMD12 Error Status can be classified in three scenarios:

1. When the HC is going to issue Auto CMD12:

Set D00 to 1h if Auto CMD12 cannot be issued due to an error in the previous command.

Set D00 to 0h if Auto CMD12 is issued.

2. At the end bit of Auto CMD12 response:

Check received responses by checking the error bits D01, D02, D03, D04.

set to 1h if Error is Detected.

set to 0h if Error is Not Detected.

3. Before reading the Auto CMD12 Error Status bit D07:

Set D07 to 1h if there is a command cannot be issued.

Set D07 to 0h if there is no command to issue.

Timing of generating the Auto CMD12 Error and writing to the MMCSD1_COMMAND register are Asynchronous. Then D07 shall be sampled when driver never writing to the MMCSD1_COMMAND register. So just before reading the MMCSD1_AUTOCMD_ERR_STS register is good timing to set the D07 status bit.

3.6.8.26 MMCSD1_HOST_CONTROL2 Register (Offset = 3Eh) [reset = 0h]

MMCSD1_HOST_CONTROL2 is shown in Figure 14-7448 and described in Table 14-15124.

Return to Summary Table.

This register is used to program UHS Mode Select, Driver Strength Select, Execute Tuning, Sampling Clock Select, Asynchronous Interrupt Enable and Preset Value Enable.

Table 14-15123 MMCSD1_HOST_CONTROL2 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 003Eh
Figure 14-7448 MMCSD1_HOST_CONTROL2 Register
15 14 13 12 11 10 9 8
PRESET_VALUE_ENA ASYNCH_INTR_ENA BIT64_ADDRESSING HOST_VER40_ENA CMD23_ENA ADMA2_LEN_MODE DRIVER_STRENGTH2 UHS2_INTF_ENABLE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
SAMPLING_CLK_SELECT EXECUTE_TUNING DRIVER_STRENGTH1 V1P8_SIGNAL_ENA UHS_MODE_SELECT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15124 MMCSD1_HOST_CONTROL2 Register Field Descriptions
Bit Field Type Reset Description
15 PRESET_VALUE_ENA R/W 0h

Preset Value Enable

Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When the MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA bit is set to automatic. This bit enables the functions defined in the Preset Value registers (MMCSD1_PRESET_VALUE0 - MMCSD1_PRESET_VALUE10).

If this bit is set to 0h, SDCLK Frequency Select, Clock Generator Select in the MMCSD1_CLOCK_CONTROL register and Driver Strength Select in the MMCSD1_HOST_CONTROL2 register are set by Host Driver.

If this bit is set to 1h, SDCLK Frequency Select, Clock Generator Select in the MMCSD1_CLOCK_CONTROL register and Driver Strength Select in the MMCSD1_HOST_CONTROL2 register are set by Host Controller as specified in the Preset Value registers (MMCSD1_PRESET_VALUE0 - MMCSD1_PRESET_VALUE10).

0h: SDCLK and Driver Strength are controlled by Host Driver

1h: Automatic Selection by Preset Value are Enabled
14 ASYNCH_INTR_ENA R/W 0h

Asynchronous Interrupt Enable

This bit can be set to 1h if a card support asynchronous interrupt and the MMCSD1_CAPABILITIES[29] ASYNCH_INTR_SUPPORT bit is set to 1h. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode . If this bit is set to 1h, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver Card Interrupt to the host when it is asserted by the Card.

0h: Disabled

1h: Enabled
13 BIT64_ADDRESSING R/W 0h

64-bit Addressing

This field is effective when the MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h.

Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host system. Host Driver sets this bit depends on addressing mode of installed OS. Refer to 64-bit System Address Support in the MMCSD1_CAPABILITIES register.

0h: 32-bits Addressing

1h: 64-bits Addressing
12 HOST_VER40_ENA R/W 0h

Host Version 4 Enable

This bit selects either Version 3.00 compatible mode or Version 4.00 mode. In Version 4.00, support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit.

In Version 4.10, supported 32-bit Block Count for all operations.

Functions of following fields are modified.

SDMA Address

SDMA uses the MMCSD1_ADMA_SYS_ADDRESS register instead of SDMA System Address register (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI)

ADMA2/ADMA3 Selection

ADMA3 is selected by MMCSD1_HOST_CONTROL1[4-3] DMA_SELECT bit.

64-bit ADMA Descriptor Size

128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1h.

Selection of 32-bit/64-bit System Addressing

Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register instead of MMCSD1_HOST_CONTROL1[4-3] DMA_SELECT bit.

32-bit Block Count

SDMA System Address register (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI) is modified to 32-bit Block Count register.

0h: Version 3.00 Compatible Mode

1h: Version 4.Mode
11 CMD23_ENA R/W 0h

CMD23 Enable

In memory card initialization, Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 (SCR[33] = 1h), this bit is set to 1h. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 datatransfer. Refer to MMCSD1_TRANSFER_MODE[3-2] AUTO_CMD_ENA bit.
10 ADMA2_LEN_MODE R/W 0h

ADMA2 Length Mode

This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit.

0h: 16-bit Data Length Mode

1h: 26-bit Data Length Mode
9 DRIVER_STRENGTH2 R/W 0h

Driver Strength Select

This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value.
8 UHS2_INTF_ENABLE R/W 0h

UHS-II Interface Enable

This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization, this bit shall be set to 1h. Before trying to start SD mode initialization, this bit shall be set to 0h.

This bit is used to enable UHS-II IF Detection, Lane Synchronization and In Dormant State in the MMCSD1_PRESENTSTATE register, and to select clock source of either SD mode or UHS-II mode.

Host Controller shall not leave unused SD 4-bit Interface lines (CLK, CMD and DAT[3:2]) floating in UHS-II mode by using pull-up or driving to low. When DAT[2] is used as interrupt input in UHS-II mode, DAT[2] of Host Controller is set to input and then DAT[2] of SDIO card is set to output to avoid conflict.

0h: 4-bit SD Interface Enabled

1h: UHS-II Interface Enabled
7 SAMPLING_CLK_SELECT R/W 0h

Sampling Clock Select (UHS-I Only)

This bit is set by tuning procedure when the MMCSD1_HOST_CONTROL2[6] EXECUTE_TUNING bit is cleared. Writing 1h to this bit is meaningless and ignored. Setting 1h means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is cleared by writing 0h. Change of this bit is not allowed while the Host Controller is receiving response or a read data block.

0h: Fixed clock is used to sample data

1h: Tuned clock is used to sample data
6 EXECUTE_TUNING R/W 0h

Execute Tuning (UHS-I Only)

This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to the MMCSD1_HOST_CONTROL2[7] SAMPLING_CLK_SELECT bit. Tuning procedure is aborted by writing 0h for more detail about tuning procedure.

0h: Not Tuned or Tuning Completed

1h: Execute Tuning
5-4 DRIVER_STRENGTH1 R/W 0h

Driver Strength Select (UHS-I Only)

Host Controller output driver in 1.8 V signaling is selected by this bit. In 3.3 V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the MMCSD1_CAPABILITIES register. This bit depends on setting of the MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA bit.

If MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA = 0h, this field is set by Host Driver.

If MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA = 1h, this field is automatically set by a value specified in the one of Preset Value registers (MMCSD1_PRESET_VALUE0 - MMCSD1_PRESET_VALUE10).

0h: Driver Type B is Selected (Default)

1h: Driver Type A is Selected

2h: Driver Type C is Selected

3h: Driver Type D is Selected
3 V1P8_SIGNAL_ENA R/W 0h

1.8 V Signaling Enable (UHS-I Only)

This bit controls voltage regulator for I/O cell. 3.3 V is supplied to the card regardless of signaling voltage.

Setting this bit from 0h to 1h starts changing signal voltage from 3.3 V to 1.8 V.

1.8 V regulator output shall be stable within 5 ms. Host Controller clears this bit if switching to 1.8 V signaling fails.

Clearing this bit from 1h to 0h starts changing signal voltage from 1.8 V to 3.3 V.

3.3 V regulator output shall be stable within 5 ms.

Host Driver can set this bit to 1h when Host Controller supports 1.8 V signaling (one of support bits is set to 1h: SDR50, SDR104 or DDR50 in the MMCSD1_CAPABILITIES register) and the card or device supports UHS-I.

0h: 3.3 V Signaling

1h: 1.8 V Signaling
2-0 UHS_MODE_SELECT R/W 0h

UHS Mode Select (UHS-I Only)

This field is used to select one of UHS-I modes or UHS-II mode. In case of UHS-I mode, this field is effective when the MMCSD1_HOST_CONTROL2[3] V1P8_SIGNAL_ENA bit is set to 1h. In case of UHS-II mode, the MMCSD1_HOST_CONTROL2[3] V1P8_SIGNAL_ENA bit shall be set to 0h. Setting of this field is used to select one of preset values in UHS-I or UHS-II mode.

If the MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA is set to 1h,Host Controller sets SDCLK/RCLK Frequency Select, Clock Generator Select in the MMCSD1_CLOCK_CONTROL register and Driver Strength Select according to Preset Value registers (MMCSD1_PRESET_VALUE0 - MMCSD1_PRESET_VALUE10). In this case, one of preset value registers is selected by this field. Host Driver needs to reset the MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA bit before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets the MMCSD1_CLOCK_CONTROL[2] SD_CLK_ENA bit again.

0h: SDR12

1h: SDR25

2h: SDR50

3h: SDR104

4h: DDR50

5h: HS400

6h: Reserved

7h: UHS-II

When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more details.

3.6.8.27 MMCSD1_CAPABILITIES Register (Offset = 40h) [reset = 180004073FE8C801h]

MMCSD1_CAPABILITIES is shown in Figure 14-7449 and described in Table 14-15126.

Return to Summary Table.

This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initialization.

Table 14-15125 MMCSD1_CAPABILITIES Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0040h
Figure 14-7449 MMCSD1_CAPABILITIES Register
63 62 61 60 59 58 57 56
HS400_SUPPORT RESERVED VDD2_1P8_SUPPORT ADMA3_SUPPORT RESERVED SPI_BLK_MODE SPI_SUPPORT
R-0h R-0h R-1h R-1h R-0h R-0h R-0h
55 54 53 52 51 50 49 48
CLOCK_MULTIPLIER
R-0h
47 46 45 44 43 42 41 40
RETUNING_MODES TUNING_FOR_SDR50 RESERVED RETUNING_TIMER_CNT
R-0h R-0h R-0h R-4h
39 38 37 36 35 34 33 32
RESERVED DRIVERD_SUPPORT DRIVERC_SUPPORT DRIVERA_SUPPORT UHS2_SUPPORT DDR50_SUPPORT SDR104_SUPPORT SDR50_SUPPORT
R-0h R-0h R-0h R-0h R-0h R-1h R-1h R-1h
31 30 29 28 27 26 25 24
SLOT_TYPE ASYNCH_INTR_SUPPORT ADDR_64BIT_SUPPORT_V3 ADDR_64BIT_SUPPORT_V4 VOLT_1P8_SUPPORT VOLT_3P0_SUPPORT VOLT_3P3_SUPPORT
R-0h R-1h R-1h R-1h R-1h R-1h R-1h
23 22 21 20 19 18 17 16
SUSP_RES_SUPPORT SDMA_SUPPORT HIGH_SPEED_SUPPORT RESERVED ADMA2_SUPPORT BUS_8BIT_SUPPORT MAX_BLK_LENGTH
R-1h R-1h R-1h R-0h R-1h R-0h R-0h
15 14 13 12 11 10 9 8
BASE_CLK_FREQ
R-C8h
7 6 5 4 3 2 1 0
TIMEOUT_CLK_UNIT RESERVED TIMEOUT_CLK_FREQ
R-0h R-0h R-1h
LEGEND: R = Read Only; -n = value after reset
Table 14-15126 MMCSD1_CAPABILITIES Register Field Descriptions
Bit Field Type Reset Description
63 HS400_SUPPORT R 0h

HS400 Support

0h: HS400 is Not Supported

1h: HS400 is Supported
62-61 RESERVED R 0h

Reserved
60 VDD2_1P8_SUPPORT R 1h

1.8 V VDD2 Support

This bit indicates that support of VDD2 on Host system.

0h: 1.8 V VDD2 is not supported

1h: 1.8 V VDD2 is supported
59 ADMA3_SUPPORT R 1h

ADMA3 Support

This bit indicates that support of ADMA3 on Host Controller.

0h: ADMA3 is not supported

1h: ADMA3 is supported
58 RESERVED R 0h

Reserved
57 SPI_BLK_MODE R 0h

SPI Block Mode

This bit indicates whether SPI Block Mode is supported or not.

0h: Not Supported

1h: Supported
56 SPI_SUPPORT R 0h

SPI Mode

This bit indicates whether SPI Mode is supported or not.

0h: Not Supported

1h: Supported
55-48 CLOCK_MULTIPLIER R 0h

Clock Multiplier

This field indicates clock multiplier value of programmable clock generator. Refer to the MMCSD1_CLOCK_CONTROL register. Setting 00h means that Host Controller does not support programmable clock generator.

FFh: Clock Multiplier M = 256

----

02h: Clock Multiplier M = 3

01h: Clock Multiplier M = 2

00h: Clock Multiplier is Not Supported
47-46 RETUNING_MODES R 0h

Re-tuning Modes (UHS-I Only)

This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver.

0h: Mode 1

1h: Mode 2

2h: Mode 3

3h: Reserved

There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue.
45 TUNING_FOR_SDR50 R 0h

Use Tuning for SDR50 (UHS-I Only)

If this bit is set to 1h, this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104).

0h: SDR50 does not require tuning

1h: SDR50 requires tuning

Note: Tuning is required for SDR50 to compensate temperature variation.
44 RESERVED R 0h

Reserved
43-40 RETUNING_TIMER_CNT R 4h

Timer Count for Re-Tuning (UHS-I Only)

This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3.

0h - Get information via other source

1h = 1 seconds

2h = 2 seconds

3h = 4 seconds

4h = 8 seconds

----

n = 2(n-1) seconds

----

Bh = 1024 seconds

Fh - Ch = Reserved
39 RESERVED R 0h

Reserved
38 DRIVERD_SUPPORT R 0h

Driver Type D Support (UHS-I Only)

This bit indicates support of Driver Type D for 1.8 Signaling.

0h: Driver Type D is Not Supported

1h: Driver Type D is Supported
37 DRIVERC_SUPPORT R 0h

Driver Type C Support (UHS-I Only)

This bit indicates support of Driver Type C for 1.8 Signaling.

0h: Driver Type C is Not Supported

1h: Driver Type C is Supported
36 DRIVERA_SUPPORT R 0h

Driver Type A Support (UHS-I Only)

This bit indicates support of Driver Type A for 1.8 Signaling.

0h: Driver Type A is Not Supported

1h: Driver Type A is Supported
35 UHS2_SUPPORT R 0h

UHS-II Support (UHS-II Only)

This bit indicates whether Host Controller supports UHS-II. If this bit is set to 1h, the MMCSD1_CAPABILITIES[60] VDD2_1P8_SUPPORT bit shall be set to 1h (Host System shall support VDD2 power supply).

0h: UHS-II is Not Supported

1h: UHS-II is Supported
34 DDR50_SUPPORT R 1h

DDR50 Support (UHS-I Only)

This bit indicates whether DDR50 is supported or not.

0h: DDR50 is Not Supported

1h: DDR50 is Supported
33 SDR104_SUPPORT R 1h

SDR104 Support (UHS-I Only)

This bit indicates whether SDR104 is supported or not. SDR104 requires tuning.

0h: SDR104 is Not Supported

1h: SDR104 is Supported
32 SDR50_SUPPORT R 1h

SDR50 Support (UHS-I Only)

If SDR104 is supported, this bit shall be set to 1h. Bit 40 indicates whether SDR50 requires tuning or not.

0h: SDR50 is Not Supported

1h: SDR50 is Supported
31-30 SLOT_TYPE R 0h

Slot Type

This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot). Embedded slot for one device (1h) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot (2h) can be set if Host Controller supports Shared Bus Control register.

The Standard Host Driver controls only a removable card or one embedded device is connected to a SD bus slot. If a slot is configured for shared bus (2h), the Standard Host Driver does not control embedded devices connected to a shared bus. Shared bus slot is controlled by a specific host driver developed by a Host System.

0h: Removable Card Slot

1h: Embedded Slot for One Device

2h: Shared Bus Slot (SD Mode)

3h: UHS-II Multiple Embedded Devices
29 ASYNCH_INTR_SUPPORT R 1h

Asynchronous Interrupt Support (SD Mode Only)

Refer to SDIO Specification Version 3.00 about asynchronous interrupt.

0h: Asynchronous Interrupt Not Supported

1h: Asynchronous Interrupt Supported
28 ADDR_64BIT_SUPPORT_V3 R 1h

64-bit System Address Support for V3

Meaning of this bit is different depends on Versions. Host Controller Version 3.00 and Version 4.10 use this bit as 64-bit System Address support for V3 mode. Host Controller Version 4.00 uses this bit as 64-bit System Address support for both V3 and V4 modes.

SDMA cannot be used in 64-bit Addressing in Version 3 mode.

If this bit is set to 1h, 64-bit ADMA2 with using 96-bit Descriptor may be enabled as follows:

In case of Host Controller Version 3, 64-bit ADMA2 is enabled by MMCSD1_HOST_CONTROL1[4-3] DMA_SELECT = 3h. In case of Host Controller Version 4, 64-bit ADMA2 for Version 3 is enabled by setting MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 0h and MMCSD1_HOST_CONTROL1[4-3] DMA_SELECT = 3h.

0h: 64-bit System Address for V3 is not Supported

1h: 64-bit System Address for V3 is Supported
27 ADDR_64BIT_SUPPORT_V4 R 1h

64-bit System Address Support for V4

This bit is added from Version 4.10. Setting 1h to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode .

When this bit is set to 1h, full or a part of 64-bit address should be used to decode Host Controller Registers so that Host Controller Registers can be placed above system memory area. 64-bit address decode of Host Controller Registers is effective regardless of setting to the MMCSD1_HOST_CONTROL2[13] BIT64_ADDRESSING bit.

If this bit is set to 1h, 64-bit DMA Addressing for Version 4 is enabled by setting MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 1h, MMCSD1_HOST_CONTROL2[13] BIT64_ADDRESSING = 1h. SDMA can be used and ADMA2 uses 128-bit Descriptor.

0h: 64-bit System Address for V4 is not Supported

1h: 64-bit System Address for V4 is Supported
26 VOLT_1P8_SUPPORT R 1h

Voltage Support 1.8 V

This bit indicates whether the HC supports 1.8 V.

0h: 1.8 V Not Supported

1h: 1.8 V Supported
25 VOLT_3P0_SUPPORT R 1h

Voltage Support 3.0 V

This bit indicates whether the HC supports 3.0 V.

0h: 3.0 V Not Supported

1h: 3.0 V Supported
24 VOLT_3P3_SUPPORT R 1h

Voltage Support 3.3 V

This bit indicates whether the HC supports 3.3 V.

0h: 3.3 V Not Supported

1h: 3.3 V Supported
23 SUSP_RES_SUPPORT R 1h

Suspend/Resume Support

This bit indicates whether the HC supports Suspend/Resume functionality. If this bit is 0h, the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend/Resume commands.

0h: Not Supported

1h: Supported
22 SDMA_SUPPORT R 1h

SDMA Support

This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.

Version 4.10 Host Controller shall support SDMA if ADMA2 is supported.

0h: SDMA Not Supported

1h: SDMA Supported
21 HIGH_SPEED_SUPPORT R 1h

High Speed Support

This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC).

0h: High Speed Not Supported

1h: High Speed Supported
20 RESERVED R 0h

Reserved
19 ADMA2_SUPPORT R 1h

ADMA2 Support

0h: ADMA2 Not support

1h: ADMA2 support
18 BUS_8BIT_SUPPORT R 0h

8-bit Support for Embedded Device (Embedded)

This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when the MMCSD1_CAPABILITIES[31-30] SLOT_TYPE bit field is set to 2h.

0h: 8-bit Bus Width Not Supported

1h: 8-bit Bus Width Supported
17-16 MAX_BLK_LENGTH R 0h

Max Block Length

This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below.

0h: 512 byte

1h: 1024 byte

2h: 2048 byte

3h: 4096 byte
15-8 BASE_CLK_FREQ R C8h

Base Clock Frequency for SD Clock

(1) 6-bit Base Clock Frequency:

This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz.

11xx xxxxb: Not Supported

0011 1111b: 63 MHz

0000 0010b: 2 MHz

0000 0001b: 1 MHz

0000 0000b: Get Information via another method

(2) 8-bit Base Clock Frequency:

This mode is supported by the Host Controller Version 3.00. Unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz.

FFh: 255 MHz

02h: 2 MHz

01h: 1 MHz

00h: Get Information via another method

If the real frequency is 16.5 MHz, the lager value shall be set 0001 0001b (17 MHz) because the Host Driver use this value to calculate the clock divider value (refer to the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method.
7 TIMEOUT_CLK_UNIT R 0h

Timeout Clock Unit

This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCSD1_ERROR_INTR_STS[4] DATA_TIMEOUT).

0h: KHz

1h: MHz
6 RESERVED R 0h

Reserved
5-0 TIMEOUT_CLK_FREQ R 1h

Timeout Clock Frequency

This bit shows the base clock frequency used to detect Data Timeout Error (MMCSD1_ERROR_INTR_STS[4] DATA_TIMEOUT).

0h: Get Information via another method

Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz

Table 14-15127 shows the 64-bit System Address Support depends on Versions.

Table 14-15127 64-bit System Address Support depends on Versions
Host Controller Version 3.00 Version 4.00 Version 4.10
D28 (from Version 2.00) for V3 for V3 and V4 for V3
D27 (from Version 4.10) D27 (from Version 4.10) Not Defined for V4
Register Decode 32-bit or 64-bit (up to implementation) 32-bit or 64-bit (up to implementation) If D27 = 1h, 64-bit
SDMA Not supported Supported when MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 1h Supported when MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 1h
ADMA2 (96-bit Descriptor) DMA Select = 3h Selected by MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 0h Selected by MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 0h
ADMA2 (128-bit Descriptor) Not Defined Selected by MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 1h Selected by MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA = 1h

As the specification of 64-bit System Address Support has been changed, capabilities of 64-bit functions are different depends on versions.

Definition of D28 is different depends on Versions. 96-bit Descriptor was defined by Version 2 but notation V3 is used including V2. Version 4.10 divides 64-bit System Address Support into V3 mode (D28) and V4 mode (D27) so that V3 mode can be optional. Migrate to V4 is recommended. From Host Controller Version 4.00, either V3 mode or V4 mode is selected by Host Version 4 Enable in the Host Control 2 register. V3 mode can be used if 64-bit System Address Support for V3 is set to 1h. V4 mode can be used if 64-bit System Address Support for V4 is set to 1h.

Prior to Version 4.10, address length of Host Controller registers decoding is not defined and whether 32-bit or 64-bit address is used to decode Host Controller registers is up to implementation. If Host Controller decodes 32-bit system address in default, the Host Controller Registers shall be placed in 32-bit addressing space.

When D27 = 1h, Host Controller Version 4.10 or later should use full or a part of 64-bit address to decode Host Controller Registers so that Host Controller Registers can be placed above system memory area. 64-bit address decode of Host Controller Registers is effective regardless of setting to the MMCSD1_HOST_CONTROL2[13] BIT64_ADDRESSING bit. How to decode register also should follow a system bus specification or a mother board specification.

From Version 4.00, 64-bit System Addressing of DMA is enabled by setting to the MMCSD1_HOST_CONTROL2[13] BIT64_ADDRESSING bit. 64-bit SDMA is not supported in V3 mode and is supported in V4 mode. There are two Descriptor types for ADMA2 96-bit (V3) or 128-bit (V4). Support of 96-bit Descriptor is optional for Host Controller Version 4.10. If D28 = 0h, 96-bit Descriptor is not supported.

Note: The Host System shall support at least one of these voltages above. The HD sets the MMCSD1_POWER_CONTROL[3:1] SD_BUS_VOLTAGE bit field according to these support bits. If multiple voltages are supported, select the usable lower voltage by comparing the OCR value from the card.

These registers indicate maximum current capability for each voltage. The value is meaningful if Voltage Support is set in the MMCSD1_CAPABILITIES register.

Table 14-15128 describes the re-tuning modes.

Table 14-15128 64-bit System Address Support depends on Versions
Bit47-46 Re-Tuning Mode Data length Timer Modes
0h Mode1 4 MB (Max.) Always enabled
1h Mode2 4 MB (Max.) Stop during data transfer
2h Reserved Reserved Reserved
3h Reserved Reserved Reserved

There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue.

Data length per a read/write command is restricted by whether Host Controller generates Re-Tuning Request during data transfer so that re-tuning procedures can be inserted during data transfers.

3.6.8.28 MMCSD1_MAX_CURRENT_CAP Register (Offset = 48h) [reset = 0h]

MMCSD1_MAX_CURRENT_CAP is shown in Figure 14-7450 and described in Table 14-15130.

Return to Summary Table.

This register indicates maximum current capability for each voltage.

Table 14-15129 MMCSD1_MAX_CURRENT_CAP Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0048h
Figure 14-7450 MMCSD1_MAX_CURRENT_CAP Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
RESERVED
R-0h
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED VDD2_1P8V
R-0h R-0h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED VDD1_1P8V
R-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDD1_3P0V VDD1_3P3V
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15130 MMCSD1_MAX_CURRENT_CAP Register Field Descriptions
Bit Field Type Reset Description
63-40 RESERVED R 0h

Reserved
39-32 VDD2_1P8V R 0h

Maximum Current for 1.8 V VDD2
31-24 RESERVED R 0h

Reserved
23-16 VDD1_1P8V R 0h

Maximum Current for 1.8 V VDD1
15-8 VDD1_3P0V R 0h

Maximum Current for 3.0 V VDD1
7-0 VDD1_3P3V R 0h

Maximum Current for 3.3 V VDD1

Table 14-15131 describes the maximum current value.

Table 14-15131 Maximum Current Value Definition
Register Value Current Value
0 Get Information via another method
1 4 mA
2 8 mA
3 12 mA
------------------- -------------------
255 1020 mA

3.6.8.29 MMCSD1_FORCE_EVNT_ACMD_ERR_STS Register (Offset = 50h) [reset = 0h]

MMCSD1_FORCE_EVNT_ACMD_ERR_STS is shown in Figure 14-7451 and described in Table 14-15133.

Return to Summary Table.

This register is not physically implemented, rather it is an address where the MMCSD1_AUTOCMD_ERR_STS register can be written.

Writing 1h: set each bit of the MMCSD1_AUTOCMD_ERR_STS register

Writing 0h: no effect

By setting a bit in this register, the correspondent bit is set in the MMCSD1_ERROR_INTR_STS register. In order to generate interrupt signal, the correspondent bit shall be set in the MMCSD1_ERROR_INTR_STS_ENA register and MMCSD1_ERROR_INTR_SIG_ENA register.

Table 14-15132 MMCSD1_FORCE_EVNT_ACMD_ERR_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0050h
Figure 14-7451 MMCSD1_FORCE_EVNT_ACMD_ERR_STS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CMD_NOT_ISS RESERVED RESP INDEX ENDBIT CRC TIMEOUT ACMD_NOT_EXEC
W-0h R-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 14-15133 MMCSD1_FORCE_EVNT_ACMD_ERR_STS Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h

Reserved
7 CMD_NOT_ISS W 0h

Force Event for Command Not Issued by AUTO CMD12 Error

0h: Not Affected

1h: Command Not Issued By Auto CMD12 Error Status is set
6 RESERVED R 0h

Reserved
5 RESP W 0h

Force Event for AUTO CMD Response Error

0h: Not Affected

1h: Auto CMD Response Error Status is set
4 INDEX W 0h

Force Event for AUTO CMD Index Error

0h: Not Affected

1h: Auto CMD Index Error Status is set
3 ENDBIT W 0h

Force Event for AUTO CMD End Bit Error

0h: Not Affected

1h: Auto CMD End bit Error Status is set
2 CRC W 0h

Force Event for AUTO CMD Timeout Error

0h: Not Affected

1h: Auto CMD CRC Error Status is set
1 TIMEOUT W 0h

Force Event for AUTO CMD Timeout Error

0h: Not Affected

1h: Auto CMD Timeout Error Status is set
0 ACMD_NOT_EXEC W 0h

Force Event for AUTO CMD12 Not Executed

0h: Not Affected

1h: Auto CMD12 Not Executed Status is set

3.6.8.30 MMCSD1_FORCE_EVNT_ERR_INT_STS Register (Offset = 52h) [reset = 0h]

MMCSD1_FORCE_EVNT_ERR_INT_STS is shown in Figure 14-7452 and described in Table 14-15135.

Return to Summary Table.

This register is not physically implemented, rather it is an address where the MMCSD1_ERROR_INTR_STS register can be written.

The MMCSD1_FORCE_EVNT_ERR_INT_STS register is not a physically implemented register. Rather, it is an address at which the MMCSD1_ERROR_INTR_STS register can be written. The effect of a write to this address will be reflected in the MMCSD1_ERROR_INTR_STS register if the corresponding bit of the MMCSD1_ERROR_INTR_STS_ENA register is set.

Writing 1h: set each bit of the MMCSD1_ERROR_INTR_STS register

Writing 0h: no effect

Table 14-15134 MMCSD1_FORCE_EVNT_ERR_INT_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0052h
Figure 14-7452 MMCSD1_FORCE_EVNT_ERR_INT_STS Register
15 14 13 12 11 10 9 8
VEND_SPEC RESP TUNING ADMA AUTO_CMD
W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
CURR_LIM DAT_ENDBIT DAT_CRC DAT_TIMEOUT CMD_INDEX CMD_ENDBIT CMD_CRC CMD_TIMEOUT
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: W = Write Only; -n = value after reset
Table 14-15135 MMCSD1_FORCE_EVNT_ERR_INT_STS Register Field Descriptions
Bit Field Type Reset Description
15-12 VEND_SPEC W 0h

N/A
11 RESP W 0h

Force Event for Response Error

0h: Not Affected

1h: Response Error Status is set
10 TUNING W 0h

Force Event for Tuning Error

0h: Not Affected

1h: Tuning Error Status is set
9 ADMA W 0h

Force Event for ADMA Error

0h: Not Affected

1h: ADMA Error Status is set
8 AUTO_CMD W 0h

Force Event for Auto CMD Error

0h: Not Affected

1h: Auto CMD Error Status is set
7 CURR_LIM W 0h

Force Event for Current Limit Error

0h: Not Affected

1h: Current Limit Error Status is set
6 DAT_ENDBIT W 0h

Force Event for Data End Bit Error

0h: Not Affected

1h: Data End Bit Error Status is set
5 DAT_CRC W 0h

Force Event for Data CRC Error

0h: Not Affected

1h: CRC Error Status is set
4 DAT_TIMEOUT W 0h

Force Event for Data Timeout Error

0h: Not Affected

1h: Timeout Error Status is set
3 CMD_INDEX W 0h

Force Event for Command Index Error

0h: Not Affected

1h: Command Index Error Status is set
2 CMD_ENDBIT W 0h

Force Event for Command End Bit Error

0h: Not Affected

1h: Command End Bit Error Status is set
1 CMD_CRC W 0h

Force Event for Command CRC Error

0h: Not Affected

1h: Command CRC Error Status is set
0 CMD_TIMEOUT W 0h

Force Event for CMD Timeout Error

0h: Not Affected

1h: Command Timeout Error Status is set

3.6.8.31 MMCSD1_ADMA_ERR_STATUS Register (Offset = 54h) [reset = 0h]

MMCSD1_ADMA_ERR_STATUS is shown in Figure 14-7453 and described in Table 14-15137.

Return to Summary Table.

When the ADMA Error interrupt occur, this register holds the ADMA State (MMCSD1_ADMA_ERR_STATUS[1-0] ADMA_ERR_STATE) and the MMCSD1_ADMA_SYS_ADDRESS register holds address around the error descriptor.

Table 14-15136 MMCSD1_ADMA_ERR_STATUS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0054h
Figure 14-7453 MMCSD1_ADMA_ERR_STATUS Register
7 6 5 4 3 2 1 0
RESERVED ADMA_LENGTH_ERR ADMA_ERR_STATE
R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15137 MMCSD1_ADMA_ERR_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 0h

Reserved
2 ADMA_LENGTH_ERR R 0h

ADMA Length Mismatch Error

This error occurs in the following 2 cases.

While the MMCSD1_TRANSFER_MODE[1] BLK_CNT_ENA bit being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be divided by the block length.

0h: No Error

1h: Error
1-0 ADMA_ERR_STATE R 0h

ADMA Error State

This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "2h" because ADMA never stops in this state.

D01 - D00: ADMA Error State when error occurred

Contents of SYS_SDR register

0h: ST_STOP (Stop DMA) Points to next of the error descriptor

1h: ST_FDS (Fetch Descriptor) Points to the error descriptor

2h: Never set this state (Not used)

3h: ST_TFR (Transfer Data) Points to the next of the error descriptor

3.6.8.32 MMCSD1_ADMA_SYS_ADDRESS Register (Offset = 58h) [reset = Xh]

MMCSD1_ADMA_SYS_ADDRESS is shown in Figure 14-7454 and described in Table 14-15139.

Return to Summary Table.

This register contains the physical address used for ADMA data transfer.

Table 14-15138 MMCSD1_ADMA_SYS_ADDRESS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0058h
Figure 14-7454 MMCSD1_ADMA_SYS_ADDRESS Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
ADMA_ADDR
R/W-Xh
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADMA_ADDR
R/W-Xh
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15139 MMCSD1_ADMA_SYS_ADDRESS Register Field Descriptions
Bit Field Type Reset Description
63-0 ADMA_ADDR R/W Xh

ADMA System Address

The 32-bit addressing Host Driver uses lower 32-bit of this register (upper 32-bit should be set to 0h) and shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this register and assumes it to be 0h.

DMA in 64-bit addressing. The 64-bit addressing Host Driver uses all bits of this register and shall program Descriptor Table on 64-bit boundary and set 64-bit boundary address to this register. DMA2/3 ignores lower 3-bit of this register andassumes it to be 0h.

SDMA

If the MMCSD1_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h, SDMA use this register to indicate System Address of data location instead of using SDMA System Address register (MMCSD1_SDMA_SYS_ADDR_LO/MMCSD1_SDMA_SYS_ADDR_HI). SDMA can be used in 32-bit and 64-bit addressing in Version 4.00.

ADMA2

This register holds byte address of executing command of the Descriptor table. At the start of ADMA2, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state.

ADMA3

This register is set by ADMA3. Host Driver is not necessary to set this register. The ADMA3 increments address of this register, which points to next line, when every time fetching a Descriptor line. When Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state.

Register Value - 00000000_xxxxxxxxh

Addressing Mode - 32-bit System Address

Register Value - xxxxxxxx_xxxxxxxxh

Addressing Mode - 64-bit System Address

3.6.8.33 MMCSD1_PRESET_VALUE0 Register (Offset = 60h) [reset = 100h]

MMCSD1_PRESET_VALUE0 is shown in Figure 14-7455 and described in Table 14-15142.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

When the MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA bit is set to 1h, SDCLK/RCLK Frequency Select and Clock Generator Select in the MMCSD1_CLOCK_CONTROL register, and Driver Strength Select in the MMCSD1_HOST_CONTROL2 register are automatically set based on the Selected Bus Speed Mode (see Table 14-15140). This means the Host Driver needs not set these fields when preset is enabled.

Before starting the initialization sequence, the Host Driver needs to set a clock preset value to SDCLK/RCLK Frequency Select in the MMCSD1_CLOCK_CONTROL register. The MMCSD1_HOST_CONTROL2[15] PRESET_VALUE_ENA bit can be set after initialization completed.

Table 14-15140 shows the conditions to select one of preset value registers.

Table 14-15140 Preset Value Register Select Condition
Selected Bus Speed Mode 1.8 V Signaling Enable (Host Control 2) High Speed Enable (Host Control 1) UHS-1 Mode Selection (Host Control 2)
Default Speed 0 0 don't care
High Speed 0 1 don't care
SDR12 1 don't care 0h
SDR25 1 don't care 1h
SDR50 1 don't care 2h
SDR104 1 don't care 3h
DDR50 1 don't care 4h
HS400 1 don't care 5h
Reserved Not determined don't care 6h
UHS-II 0 don't care 7h
Table 14-15141 MMCSD1_PRESET_VALUE0 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0060h
Figure 14-7455 MMCSD1_PRESET_VALUE0 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-100h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-100h
LEGEND: R = Read Only; -n = value after reset
Table 14-15142 MMCSD1_PRESET_VALUE0 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 100h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.34 MMCSD1_PRESET_VALUE1 Register (Offset = 62h) [reset = 4h]

MMCSD1_PRESET_VALUE1 is shown in Figure 14-7456 and described in Table 14-15144.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15143 MMCSD1_PRESET_VALUE1 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0062h
Figure 14-7456 MMCSD1_PRESET_VALUE1 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-4h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-4h
LEGEND: R = Read Only; -n = value after reset
Table 14-15144 MMCSD1_PRESET_VALUE1 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 4h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.35 MMCSD1_PRESET_VALUE2 Register (Offset = 64h) [reset = 2h]

MMCSD1_PRESET_VALUE2 is shown in Figure 14-7457 and described in Table 14-15146.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15145 MMCSD1_PRESET_VALUE2 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0064h
Figure 14-7457 MMCSD1_PRESET_VALUE2 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-2h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-2h
LEGEND: R = Read Only; -n = value after reset
Table 14-15146 MMCSD1_PRESET_VALUE2 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 2h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.36 MMCSD1_PRESET_VALUE3 Register (Offset = 66h) [reset = 4h]

MMCSD1_PRESET_VALUE3 is shown in Figure 14-7458 and described in Table 14-15148.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15147 MMCSD1_PRESET_VALUE3 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0066h
Figure 14-7458 MMCSD1_PRESET_VALUE3 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-4h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-4h
LEGEND: R = Read Only; -n = value after reset
Table 14-15148 MMCSD1_PRESET_VALUE3 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 4h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.37 MMCSD1_PRESET_VALUE4 Register (Offset = 68h) [reset = 2h]

MMCSD1_PRESET_VALUE4 is shown in Figure 14-7459 and described in Table 14-15150.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15149 MMCSD1_PRESET_VALUE4 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0068h
Figure 14-7459 MMCSD1_PRESET_VALUE4 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-2h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-2h
LEGEND: R = Read Only; -n = value after reset
Table 14-15150 MMCSD1_PRESET_VALUE4 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 2h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.38 MMCSD1_PRESET_VALUE5 Register (Offset = 6Ah) [reset = 1h]

MMCSD1_PRESET_VALUE5 is shown in Figure 14-7460 and described in Table 14-15152.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15151 MMCSD1_PRESET_VALUE5 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 006Ah
Figure 14-7460 MMCSD1_PRESET_VALUE5 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-1h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-1h
LEGEND: R = Read Only; -n = value after reset
Table 14-15152 MMCSD1_PRESET_VALUE5 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 1h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.39 MMCSD1_PRESET_VALUE6 Register (Offset = 6Ch) [reset = 0h]

MMCSD1_PRESET_VALUE6 is shown in Figure 14-7461 and described in Table 14-15154.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15153 MMCSD1_PRESET_VALUE6 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 006Ch
Figure 14-7461 MMCSD1_PRESET_VALUE6 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15154 MMCSD1_PRESET_VALUE6 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 0h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.40 MMCSD1_PRESET_VALUE7 Register (Offset = 6Eh) [reset = 2h]

MMCSD1_PRESET_VALUE7 is shown in Figure 14-7462 and described in Table 14-15156.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15155 MMCSD1_PRESET_VALUE7 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 006Eh
Figure 14-7462 MMCSD1_PRESET_VALUE7 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-2h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-2h
LEGEND: R = Read Only; -n = value after reset
Table 14-15156 MMCSD1_PRESET_VALUE7 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 2h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.41 MMCSD1_PRESET_VALUE8 Register (Offset = 72h) [reset = 0h]

MMCSD1_PRESET_VALUE8 is shown in Figure 14-7463 and described in Table 14-15158.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15157 MMCSD1_PRESET_VALUE8 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0072h
Figure 14-7463 MMCSD1_PRESET_VALUE8 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15158 MMCSD1_PRESET_VALUE8 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 0h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.42 MMCSD1_PRESET_VALUE10 Register (Offset = 74h) [reset = 0h]

MMCSD1_PRESET_VALUE10 is shown in Figure 14-7464 and described in Table 14-15160.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 14-15159 MMCSD1_PRESET_VALUE10 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0074h
Figure 14-7464 MMCSD1_PRESET_VALUE10 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15160 MMCSD1_PRESET_VALUE10 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 0h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD1_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

3.6.8.43 MMCSD1_ADMA3_DESC_ADDRESS Register (Offset = 78h) [reset = Xh]

MMCSD1_ADMA3_DESC_ADDRESS is shown in Figure 14-7465 and described in Table 14-15162.

Return to Summary Table.

The start address of Integrated DMA Descriptor is set to this register.

Table 14-15161 MMCSD1_ADMA3_DESC_ADDRESS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0078h
Figure 14-7465 MMCSD1_ADMA3_DESC_ADDRESS Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
INTG_DESC_ADDR
R/W-Xh
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTG_DESC_ADDR
R/W-Xh
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15162 MMCSD1_ADMA3_DESC_ADDRESS Register Field Descriptions
Bit Field Type Reset Description
63-0 INTG_DESC_ADDR R/W Xh

ADMA3 Integrated Descriptor Address

The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the next Descriptor address.

The 32-bit addressing Host Driver uses lower 32-bit of this register and shall program Descriptor Table on 32-bit boundary. ADMA3 ignores lower 2-bit of this register and assumes it to be 0h. Writing to 07Bh starts ADMA3 data transfer.

The 64-bit addressing Host Driver uses all 64-bit of this register and shall program Descriptor Table on 64-bit boundary. ADMA3 ignores lower 3-bit of this register and assumes it to be 0h. Writing to 07Fh starts ADMA3 data transfer.

Register Value - 00000000_xxxxxxxxh Addressing Mode - 32-bit System Address

Register Value - xxxxxxxx_xxxxxxxxh Addressing Mode - 64-bit System Address

3.6.8.44 MMCSD1_UHS2_BLOCK_SIZE Register (Offset = 80h) [reset = 0h]

MMCSD1_UHS2_BLOCK_SIZE is shown in Figure 14-7466 and described in Table 14-15164.

Return to Summary Table.

This register is used to configure the number of bytes in a data block.

Table 14-15163 MMCSD1_UHS2_BLOCK_SIZE Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0080h
Figure 14-7466 MMCSD1_UHS2_BLOCK_SIZE Register
15 14 13 12 11 10 9 8
RESERVED SDMA_BUF_BOUNDARY XFER_BLK_SIZE
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
XFER_BLK_SIZE
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15164 MMCSD1_UHS2_BLOCK_SIZE Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0h

Reserved
14-12 SDMA_BUF_BOUNDARY R/W 0h

UHS-II SDMA Buffer Boundary (SDMA only)

When system memory is managed by paging, SDMA data transfer is performed in unit of paging. A page size of system memory management is set to this field.

Host Controller generates the DMA Interrupt at the page boundary and requests the Host Driver to update the MMCSD1_ADMA_SYS_ADDRESS register. SDMA waits until the MMCSD1_ADMA_SYS_ADDRESS register is written.

At the end of transfer, the Host Controller may issue or may not issue DMA Interrupt. In particular, DMA Interrupt shall not be issued after Transfer Complete Interrupt is issued (see MMCSD1_NORMAL_INTR_STS[1] XFER_COMPLETE).

These bits shall be supported when the MMCSD1_CAPABILITIES[22] SDMA_SUPPORT bit is set to 1h and this function is active when the MMCSD1_UHS2_XFER_MODE[0] DMA_ENA bit register is set to 1h. ADMA does not use this field.

0h: 4K bytes (Detects A11 carry out)

1h: 8K bytes (Detects A12 carry out)

2h: 16K Bytes (Detects A13 carry out)

3h: 32K Bytes (Detects A14 carry out)

4h: 64K bytes (Detects A15 carry out)

5h: 128K Bytes (Detects A16 carry out)

6h: 256K Bytes (Detects A17 carry out)

7h: 512K Bytes (Detects A18 carry out)
11-0 XFER_BLK_SIZE R/W 0h

UHS-II Block Size

This bit field specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes.

Variable block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This bit field is effective when the MMCSD1_UHS2_COMMAND[5] DATA_PRESENT bit is set to 1h.

0000h - No data transfer

0001h - 1 Byte

0002h - 2 Bytes

0003h - 3 Bytes

... ...

01FFh - 511 Bytes

0200h - 512 Bytes

... ...

0800h - 2048 Bytes

3.6.8.45 MMCSD1_UHS2_BLOCK_COUNT Register (Offset = 84h) [reset = 0h]

MMCSD1_UHS2_BLOCK_COUNT is shown in Figure 14-7467 and described in Table 14-15166.

Return to Summary Table.

This register is used to configure the number of data blocks.

Table 14-15165 MMCSD1_UHS2_BLOCK_COUNT Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0084h
Figure 14-7467 MMCSD1_UHS2_BLOCK_COUNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFER_BLK_COUNT
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15166 MMCSD1_UHS2_BLOCK_COUNT Register Field Descriptions
Bit Field Type Reset Description
31-0 XFER_BLK_COUNT R/W 0h

UHS-II Block Count

This register is effective when the MMCSD1_UHS2_COMMAND[5] DATA_PRESENT bit is set to 1h and is enabled when the MMCSD1_UHS2_XFER_MODE[1] BLK_CNT_ENA bit is set to 1h and the MMCSD1_UHS2_XFER_MODE[5] BYTE_MODE bit is set to 0h. Data transfer stops when the count reaches zero. Setting the block count to 0h results in no data blocks is transferred.

This register should be accessed only when no transaction is executing (after transactions are stopped). During data transfer, read operations on this register may return an invalid value and write operations are ignored.

00000000h: Stop Count

00000001h: 1 block

00000002h: 2 blocks

... ...

FFFFFFFFh: 4G blocks - 1

3.6.8.46 MMCSD1_UHS2_COMMAND_PKT_0 to MMCSD1_UHS2_COMMAND_PKT_19 Register (Offset = 88h to 9Bh) [reset = 0h]

MMCSD1_UHS2_COMMAND_PKT_0 to MMCSD1_UHS2_COMMAND_PKT_19 is shown in Figure 14-7468 and described in Table 14-15169.

Return to Summary Table.

UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see Table 14-15167). The command length varies depends on a Command Packet type. The length is specified by the MMCSD1_UHS2_COMMAND register.

Table 14-15167 UHS-II Command Packet Register
Offset Preset Value Registers
088h Command Packet Byte 0
089h Command Packet Byte 1
08Ah Command Packet Byte 2
.... ....
09Bh Command Packet Byte 19
Table 14-15168 MMCSD1_UHS2_COMMAND_PKT_0 to MMCSD1_UHS2_COMMAND_PKT_19 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0088h to 0FA0 009Bh
Figure 14-7468 MMCSD1_UHS2_COMMAND_PKT_0 to MMCSD1_UHS2_COMMAND_PKT_19 Register
7 6 5 4 3 2 1 0
CMD_PKT_BYTE
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15169 MMCSD1_UHS2_COMMAND_PKT_0 to MMCSD1_UHS2_COMMAND_PKT_19 Register Field Descriptions
Bit Field Type Reset Description
7-0 CMD_PKT_BYTE R/W 0h

Command Packet Byte

UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type.

3.6.8.47 MMCSD1_UHS2_XFER_MODE Register (Offset = 9Ch) [reset = 0h]

MMCSD1_UHS2_XFER_MODE is shown in Figure 14-7469 and described in Table 14-15171.

Return to Summary Table.

This register is used to control the operations of data transfers.

On issuing a Command Packet, a Command Packet image is set to UHS-II Command Packet register (see MMCSD1_UHS2_COMMAND_PKT_0 - MMCSD1_UHS2_COMMAND_PKT_19) but Host Controller does not analyze the setting of UHS-II Command Packet register. Instead, Host Controller refers setting of this register to issue a Command Packet to make the control easy. Setting of these registers shall be correspondent.

Table 14-15170 MMCSD1_UHS2_XFER_MODE Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 009Ch
Figure 14-7469 MMCSD1_UHS2_XFER_MODE Register
15 14 13 12 11 10 9 8
DUPLEX_SELECT EBSY_WAIT RESERVED RESP_INTR_DIS
R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
RESP_ERR_CHK_ENA RESP_TYPE BYTE_MODE DATA_XFER_DIR RESERVED BLK_CNT_ENA DMA_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15171 MMCSD1_UHS2_XFER_MODE Register Field Descriptions
Bit Field Type Reset Description
15 DUPLEX_SELECT R/W 0h

Half/Full Select

Use of 2 lane half duplex mode is determined by Host Driver.

0h: Full Duplex Mode

1h: 2 Lane Half Duplex Mode
14 EBSY_WAIT R/W 0h

EBSY Wait

This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.

If this bit is set to 1h, Host Controller waits receiving of EBSY packet and on receiving EBSY packet, the MMCSD1_NORMAL_INTR_STS[1] XFER_COMPLETE bit is set to 1h to indicate end of busy. If an error is indicated in EBSY packet (for example: Memory Error), the MMCSD1_UHS2_ERR_INTR_STS[8] EBSY bit is set to 1h.

Setting of the MMCSD1_UHS2_ERR_INTR_STS[8] EBSY bit also sets the MMCSD1_NORMAL_INTR_STS[15] ERROR_INTR bit to 1h. The MMCSD1_NORMAL_INTR_STS[15] ERROR_INTR and MMCSD1_NORMAL_INTR_STS[1] XFER_COMPLETE bits shall be set together.

0h: Issue a command without busy

1h: Wait EBSY
13-9 RESERVED R 0h

Reserved
8 RESP_INTR_DIS R/W 0h

Response Interrupt Disable

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.

If Host Driver checks response error, sets this bit to 0h and waits the MMCSD1_NORMAL_INTR_STS[0] CMD_COMPLETE bit and then check the response register (MMCSD1_RESPONSE_0 - MMCSD1_RESPONSE_7). If Host Controller checks response error, sets this bit to 1h and sets the MMCSD1_UHS2_XFER_MODE[7] RESP_ERR_CHK_ENA bit to 1h. The MMCSD1_NORMAL_INTR_STS[0] CMD_COMPLETE bit is disabled by this bit regardless of MMCSD1_NORMAL_INTR_SIG_ENA[0] CMD_COMPLETE bit.

0h: Response Interrupt is enabled

1h: Response Interrupt is disabled
7 RESP_ERR_CHK_ENA R/W 0h

Response Error Check Enable

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.

If Host Driver checks response error, this bit is set to 0h and the MMCSD1_UHS2_XFER_MODE[8] RESP_INTR_DIS bit is set to 0h. If Host Controller checks response error, sets this bit to 1h and sets the MMCSD1_UHS2_XFER_MODE[8] RESP_INTR_DIS bit to 1h. Response Type R1/R5 selects either R1 or R5 response type. If an error is detected, RES Packet Error Interrupt is generated in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Response Error Check is disabled

1h: Response Error Check is enabled
6 RESP_TYPE R/W 0h

Response Type R1/R5

When response error check is enabled, this bit selects either R1 or R5 response types.

Two types of response checks are supported: R1 for memory and R5 for SDIO.

Error Statuses Checked in R1:

Bit31 OUT_OF_RANGE

Bit30 ADDRESS_ERROR

Bit29 BLOCK_LEN_ERROR

Bit26 WP_VIOLATION

Bit25 CARD_IS_LOCKED

Bit23 COM_CRC_ERROR

Bit21 CARD_ECC_FAILED

Bit20 CC_ERROR

Bit19 ERROR

Response Flags Checked in R5:

Bit07 COM_CRC_ERROR

Bit03 ERROR

Bit01 FUNCTION_NUMBER

Bit00 OUT_OF_RANGE

0h: R1 (Memory)

1h: R5 (SDIO)
5 BYTE_MODE R/W 0h

Block/Byte Mode

This bit specifies whether data transfer is in byte mode or block mode when the MMCSD1_UHS2_COMMAND[5] DATA_PRESENT bit is set to 1h. This bit is effective to a command with data transfer.

0h: Block Mode

1h: Byte Mode
4 DATA_XFER_DIR R/W 0h

Data Transfer Direction

This bit specifies direction of data transfer when the MMCSD1_UHS2_COMMAND[5] DATA_PRESENT bit is set to 1h. This bit is effective to a command with data transfer.

0h: Read (Card to Host)

1h: Write (Host to Card)
3-2 RESERVED R 0h

Reserved
1 BLK_CNT_ENA R/W 0h

Block Count Enable

This bit specifies whether data transfer uses the MMCSD1_UHS2_BLOCK_COUNT register. If this bit is set to 1h, data transfer is terminated by Block Count. Setting to the MMCSD1_UHS2_BLOCK_COUNT register shall be equivalent to TLEN in UHS-II Command Packet register (MMCSD1_UHS2_COMMAND_PKT_0 - MMCSD1_UHS2_COMMAND_PKT_19).

0h: Block Count Disabled

1h: Block Count Enabled
0 DMA_ENA R/W 0h

DMA Enable

This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by the MMCSD1_HOST_CONTROL1[4-3] DMA_SELECT bit field.

0h: DMA is disabled

1h: DMA is enabled

3.6.8.48 MMCSD1_UHS2_COMMAND Register (Offset = 9Eh) [reset = 0h]

MMCSD1_UHS2_COMMAND is shown in Figure 14-7470 and described in Table 14-15173.

Return to Summary Table.

This register is used to program the Command for host controller.

Table 14-15172 MMCSD1_UHS2_COMMAND Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 009Eh
Figure 14-7470 MMCSD1_UHS2_COMMAND Register
15 14 13 12 11 10 9 8
RESERVED PKT_LENGTH
R-0h R/W-0h
7 6 5 4 3 2 1 0
CMD_TYPE DATA_PRESENT RESERVED SUB_COMMAND RESERVED
R/W-0h R/W-0h R-0h R/W-0h R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15173 MMCSD1_UHS2_COMMAND Register Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R 0h

Reserved
12-8 PKT_LENGTH R/W 0h

UHS-II Command Packet Length

A command packet length, which is set in the UHS-II Command Packet register (MMCSD1_UHS2_COMMAND_PKT_0 - MMCSD1_UHS2_COMMAND_PKT_19), is set to this bit field.

00011b – 00000b: 3-0 Bytes (Not used)

00100b: 4 Bytes

.... ....

10100b: 20 Bytes

11111b – 10101b
7-6 CMD_TYPE R/W 0h

Command Type

This field is used to distinguish a specific command like abort command. If this field is set to 0h, the UHS-II RES Packet is stored in UHS-II Response register (MMCSD1_UHS2_RESPONSE_0 - MMCSD1_UHS2_RESPONSE_19). To avoid overwriting the UHS-II Response register, when this field is set to 1h, the RES Packet (4 bytes length) of TRANS_ABORT CCMD is stored in the Response register (04FB 0010h - 04FB 0013h (04F9 8010h - 04F9 8013h)) and when this field is set to 2h, the RES Packet (8 bytes length) of memory or SDIO abort command (CMD12 or SDIO Abort command) is stored in the Response register (04FB 0018h - 04FB 001Fh (04F9 8018h - 04F9 801Fh)). When this field is set to 3h, Host Controller controls lane to go into dormant state.

0h: Normal Command

1h: TRANS_ABORT CCMD

2h: CMD12 or SDIO Abort command

3h: Go Dormant Command
5 DATA_PRESENT R/W 0h

Data Present

This bit specifies whether the command is accompanied by data packet.

0h: No Data Present

1h: Data Present
4-3 RESERVED R 0h

Reserved
2 SUB_COMMAND R/W 0h

Sub Command Flag

This bit is added from Version 4.10 to distinguish a main command or sub command.

When issuing a main command, this bit is set to 0h and when issuing a sub command, this bit is set to 1h. Setting of this bit is checked by the MMCSD1_PRESENTSTATE[28] SUB_COMMAND_STS bit.

0h: Sub Command

1h: Main Command
1-0 RESERVED R 0h

Reserved

3.6.8.49 MMCSD1_UHS2_RESPONSE_0 to MMCSD1_UHS2_RESPONSE_19 Register (Offset = A0h to B3h) [reset = 0h]

MMCSD1_UHS2_RESPONSE_0 to MMCSD1_UHS2_RESPONSE_19 is shown in Figure 14-7471 and described in Table 14-15175.

Return to Summary Table.

This register is used to store received UHS-II RES Packet image.

Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command, which is specified by setting 1h or 2h to the MMCSD1_UHS2_COMMAND[7-6] CMD_TYPE bit field. The maximum response length is 20 bytes.

Table 14-15174 MMCSD1_UHS2_RESPONSE_0 to UHS2_RESPONSE_19 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00A0h to 0FA0 00B3h
Figure 14-7471 MMCSD1_UHS2_RESPONSE_0 to MMCSD1_UHS2_RESPONSE_19 Register
7 6 5 4 3 2 1 0
RESP_PKT_BYTE
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15175 MMCSD1_UHS2_RESPONSE_0 to UHS2_RESPONSE_19 Register Field Descriptions
Bit Field Type Reset Description
7-0 RESP_PKT_BYTE R 0h

Response Packet Byte

Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command.

Table 14-15176 shows UHS-II Response Register offsets.

Table 14-15176 UHS-II Response Register
Offset Preset Value Registers
0FA0 0A0h / 04F9 8A0h Response Packet Byte 0
0FA0 0A1h / 04F9 8A1h Response Packet Byte 1
0FA0 0A2h / 04F9 8A2h Response Packet Byte 2
.... .... .... ....
0FA0 0B3h / 04F9 8B3h Response Packet Byte 19

3.6.8.50 MMCSD1_UHS2_MESSAGE_SELECT Register (Offset = B4h) [reset = 0h]

MMCSD1_UHS2_MESSAGE_SELECT is shown in Figure 14-7472 and described in Table 14-15178.

Return to Summary Table.

This register is used to access internal buffer.

Table 14-15177 MMCSD1_UHS2_MESSAGE_SELECT Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00B4h
Figure 14-7472 MMCSD1_UHS2_MESSAGE_SELECT Register
7 6 5 4 3 2 1 0
RESERVED MSG_SEL
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15178 MMCSD1_UHS2_MESSAGE_SELECT Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 0h

Reserved
1-0 MSG_SEL R/W 0h

UHS-II MSG Select

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs can be read from the MMCSD1_UHS2_MESSAGE register (04FB 00BBh - 04FB 00B8h (04F9 80BBh - 04F9 80B8h) by setting this register

(assumed for debug usage).

0h: The latest MSG

1h: One MSG before

2h: Two MSGs before

3h: Three MSGs before

3.6.8.51 MMCSD1_UHS2_MESSAGE Register (Offset = B8h) [reset = 0h]

MMCSD1_UHS2_MESSAGE is shown in Figure 14-7473 and described in Table 14-15180.

Return to Summary Table.

This register is used to access internal buffer.

Table 14-15179 MMCSD1_UHS2_MESSAGE Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00B8h
Figure 14-7473 MMCSD1_UHS2_MESSAGE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSG_BYTE3 MSG_BYTE2
R-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSG_BYTE1 MSG_BYTE0
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15180 MMCSD1_UHS2_MESSAGE Register Field Descriptions
Bit Field Type Reset Description
31-24 MSG_BYTE3 R 0h

UHS II MSG

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the MMCSD1_UHS2_MESSAGE_SELECT register. Usually 2 duplicate MSG packets are sent from/to UHS-II card. One of these 2 MSG packets which Host Controller recognizes as valid one is stored in the MMCSD1_UHS2_MESSAGE Register.
23-16 MSG_BYTE2 R 0h

UHS II MSG

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the MMCSD1_UHS2_MESSAGE_SELECT register. Usually 2 duplicate MSG packets are sent from/to UHS-II card. One of these 2 MSG packets which Host Controller recognizes as valid one is stored in the MMCSD1_UHS2_MESSAGE Register.
15-8 MSG_BYTE1 R 0h

UHS II MSG

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the MMCSD1_UHS2_MESSAGE_SELECT register. Usually 2 duplicate MSG packets are sent from/to UHS-II card. One of these 2 MSG packets which Host Controller recognizes as valid one is stored in the MMCSD1_UHS2_MESSAGE Register.
7-0 MSG_BYTE0 R 0h

UHS II MSG

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the MMCSD1_UHS2_MESSAGE_SELECT register. Usually 2 duplicate MSG packets are sent from/to UHS-II card. One of these 2 MSG packets which Host Controller recognizes as valid one is stored in the MMCSD1_UHS2_MESSAGE Register.

3.6.8.52 MMCSD1_UHS2_DEVICE_INTR_STATUS Register (Offset = BCh) [reset = 0h]

MMCSD1_UHS2_DEVICE_INTR_STATUS is shown in Figure 14-7474 and described in Table 14-15182.

Return to Summary Table.

This register shows receipt of INT MSG from which device.

Table 14-15181 MMCSD1_UHS2_DEVICE_INTR_STATUS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00BCh
Figure 14-7474 MMCSD1_UHS2_DEVICE_INTR_STATUS Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_INT_STS
R/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 14-15182 MMCSD1_UHS2_DEVICE_INTR_STATUS Register Field Descriptions
Bit Field Type Reset Description
15-0 DEV_INT_STS R/W1C 0h

UHS-II Device Interrupt Status

This register shows receipt of INT MSG from which device and is effective when the MMCSD1_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 1h. On receiving INT MSG from a device, Host Controller saves the INT MSG to MMCSD1_UHS2_DEVICE_INT_CODE register. A bit of this register, which is correspondent to Device ID, is set to 1h and generate Card Interrupt in Normal Interrupt Status register (see MMCSD1_NORMAL_INTR_STS[8] CARD_INTR).

Writing a bit to 1h clears the status bit (interrupt is treated) and writing a bit to 0h keeps the status value (interrupt is untreated). If the MMCSD1_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 0h, this register is cleared to 0h and Host Controller ignores receipt of INT MSG.

Effective bit range of this register is determined by the MMCSD1_UHS2_GEN_CAP[21-18] CORECFG_UHS2_MAX_DEVICES bit field. If N devices are supported, bits 1 to N are effective. Then Device ID is supposed to be assigned from 1 sequentially at the UHS-II Initialization. A bit of unsupported Device ID in this register shall be indicated to 0h.

D00 - Not used (Reserved)

D01 - Setting 1h means INT MSG is received from Device ID 1

D02 - Setting 1h means INT MSG is received from Device ID 2

.... .....

D15 - Setting 1h means INT MSG is received from Device ID 15

3.6.8.53 MMCSD1_UHS2_DEVICE_SELECT Register (Offset = BEh) [reset = 0h]

MMCSD1_UHS2_DEVICE_SELECT is shown in Figure 14-7475 and described in Table 14-15184.

Return to Summary Table.

UHS-II Device Select Register.

Table 14-15183 MMCSD1_UHS2_DEVICE_SELECT Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00BEh
Figure 14-7475 MMCSD1_UHS2_DEVICE_SELECT Register
7 6 5 4 3 2 1 0
INT_MSG_ENA RESERVED DEV_SEL
R/W-0h R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15184 MMCSD1_UHS2_DEVICE_SELECT Register Field Descriptions
Bit Field Type Reset Description
7 INT_MSG_ENA R/W 0h

INT MSG Enable (Optional)

This bit enables receipt of INT MSG. If this bit is set to 1h, receipt of INT MSG is informed by the MMCSD1_NORMAL_INTR_STS[8] CARD_INTR bit. If this bit is set to 0h, Host Controller ignores receipt of INT MSG and may not set the MMCSD1_UHS2_DEVICE_INT_CODE register.

Support of INT MSG Interrupt is optional. If trying to set this bit to 1h but still this bit is read 0, INT MSG Interrupt is not supported by the Host Controller. In this case, the MMCSD1_UHS2_DEVICE_INTR_STATUS register always shall be read 0 and the MMCSD1_UHS2_DEVICE_INT_CODE register may not be implemented.

0h: Disabled

1h: Enabled
6-4 RESERVED R 0h

Reserved
3-0 DEV_SEL R/W 0h

UHS-II Device Select

Host Controller holds an INT MSG packet per device. One of INT MSGs (up to 15) can be selected by this field and read from the MMCSD1_UHS2_DEVICE_INT_CODE. This field is effective when the MMCSD1_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 1h.

The number of devices implemented in the Host Controller is indicated by the MMCSD1_UHS2_GEN_CAP[21-18] CORECFG_UHS2_MAX_DEVICES bit field.

0h: Unselected (Default)

1h: INT MSG of Device ID 1 is selected

2h: INT MSG of Device ID 2 is selected

..... .....

Fh: INT MSG of Device ID 15 is selected

3.6.8.54 MMCSD1_UHS2_DEVICE_INT_CODE Register (Offset = BFh) [reset = 0h]

MMCSD1_UHS2_DEVICE_INT_CODE is shown in Figure 14-7476 and described in Table 14-15186.

Return to Summary Table.

This register is effective when the MMCSD1_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 1h.

Table 14-15185 MMCSD1_UHS2_DEVICE_INT_CODE Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00BFh
Figure 14-7476 MMCSD1_UHS2_DEVICE_INT_CODE Register
7 6 5 4 3 2 1 0
DEV_INTR
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15186 MMCSD1_UHS2_DEVICE_INT_CODE Register Field Descriptions
Bit Field Type Reset Description
7-0 DEV_INTR R 0h

UHS II Device Interrupt

This register is effective when the MMCSD1_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 1h. Host Controller holds an INT MSG packet per device. One of INT MSGs (Code length is 1 byte) up to 15 can be read from this register by selecting UHS-II Device Select (MMCSD1_UHS2_DEVICE_SELECT[3-0] DEV_SEL).

The number of the registers to hold INT MSGs is determined by the MMCSD1_UHS2_GEN_CAP[21-18] CORECFG_UHS2_MAX_DEVICES bit field. Device ID is supposed to be assigned from 1 sequentially at the UHS-II Initialization.

3.6.8.55 MMCSD1_UHS2_SOFTWARE_RESET Register (Offset = C0h) [reset = 0h]

MMCSD1_UHS2_SOFTWARE_RESET is shown in Figure 14-7477 and described in Table 14-15188.

Return to Summary Table.

UHS-II Software Reset Register.

Table 14-15187 MMCSD1_UHS2_SOFTWARE_RESET Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00C0h
Figure 14-7477 MMCSD1_UHS2_SOFTWARE_RESET Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED HOST_SDTRAN_RESET HOST_FULL_RESET
R-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15188 MMCSD1_UHS2_SOFTWARE_RESET Register Field Descriptions
Bit Field Type Reset Description
15-2 RESERVED R 0h

Reserved
1 HOST_SDTRAN_RESET R/W 0h

Host SD-TRAN Reset

Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completion of SD-TRAN reset. If CMD0 is issued, SD-TRAN Initialization sequence from CMD8 is required to use UHS-II mode. Assuming that bus power is maintained and CM-TRAN Initialization is not required.

Host Controller requires to do followings:

(1) SD Clock Enable is maintained (continue to provide RCLK).

(2) All setting register is maintained.

(3) Internal sequencers are reset to just after power on be able to issue a command.

(4) All Interrupt Status, Status Enable and Signal Enable are cleared.

(5) Data transfer is terminated and data in buffer is discarded.

0h: Not Affected

1h: Reset SD-TRAN
0 HOST_FULL_RESET R/W 0h

Host Full Reset

On issuing FULL_RESET CCMD, Host Driver set this bit to 1h to reset Host Controller. This bit is cleared automatically at completion of Host Controller reset. Initialization sequence from PHY Initialization is required to use UHS-II mode. Assuming that bus power is maintained.

Host Controller requires to do followings:

(1) SD Clock Enable is cleared (internal Clock is still synchronized).

(2) All setting register is cleared.

(3) Internal sequencers are reset to just after power on.

(4) All Interrupt Status, Status Enable and Signal Enable are cleared.

0h: Not Affected

1h: Reset Host Controller

3.6.8.56 MMCSD1_UHS2_TIMER_CONTROL Register (Offset = C2h) [reset = 0h]

MMCSD1_UHS2_TIMER_CONTROL is shown in Figure 14-7478 and described in Table 14-15190.

Return to Summary Table.

UHS-II Timeout Control Register.

Table 14-15189 MMCSD1_UHS2_TIMER_CONTROL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00C2h
Figure 14-7478 MMCSD1_UHS2_TIMER_CONTROL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
DEADLOCK_TIMEOUT_CTR CMDRESP_TIMEOUT_CTR
R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15190 MMCSD1_UHS2_TIMER_CONTROL Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h

Reserved
7-4 DEADLOCK_TIMEOUT_CTR R/W 0h

Timeout Counter Value for Deadlock

This value determines the deadlock period while host expecting to receive a packet (1 second). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for Deadlock (in the MMCSD1_UHS2_ERR_INTR_STS_ENA register).

Fh: Reserved

Eh: TMCLK x 227

.... ....

1h: TMCLK x 214

0h: TMCLK x 213
3-0 CMDRESP_TIMEOUT_CTR R/W 0h

Timeout Counter Value for CMD_RES

This value determines the interval between command packet and response packet (5 ms). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for CMD_RES (in the MMCSD1_UHS2_ERR_INTR_STS_ENA register).

Fh: Reserved

Eh: TMCLK x 227

.... ....

1h: TMCLK x 214

0h: TMCLK x 213

3.6.8.57 MMCSD1_UHS2_ERR_INTR_STS Register (Offset = C4h) [reset = 0h]

MMCSD1_UHS2_ERR_INTR_STS is shown in Figure 14-7479 and described in Table 14-15192.

Return to Summary Table.

This register gives the status of all UHS-II interrupts.

Table 14-15191 MMCSD1_UHS2_ERR_INTR_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00C4h
Figure 14-7479 MMCSD1_UHS2_ERR_INTR_STS Register
31 30 29 28 27 26 25 24
VENDOR_SPECFIC_ERR RESERVED
R/W1C-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DEADLOCK_TIMEOUT CMD_RESP_TIMEOUT
R-0h R/W1C-0h R/W1C-0h
15 14 13 12 11 10 9 8
ADMA2_ADMA3 RESERVED EBSY
R/W1C-0h R-0h R/W1C-0h
7 6 5 4 3 2 1 0
UNRECOVERABLE RESERVED TID FRAMING CRC RETRY_EXPIRED RESP_PKT HEADER
R/W1C-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 14-15192 MMCSD1_UHS2_ERR_INTR_STS Register Field Descriptions
Bit Field Type Reset Description
31-27 VENDOR_SPECFIC_ERR R/W1C 0h

Vendor Specific Error

Vendor may use this field for vendor specific error status.

0h: Interrupt is not generated

1h: Vendor Specific Error
26-18 RESERVED R 0h

Reserved
17 DEADLOCK_TIMEOUT R/W1C 0h

Timeout for Deadlock

Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout (1 second). Timeout value is determined by the setting of the MMCSD1_UHS2_TIMER_CONTROL[7-4] DEADLOCK_TIMEOUT_CTR bit field.

0h: Interrupt is not generated

1h: Deadlock Error
16 CMD_RESP_TIMEOUT R/W1C 0h

Timeout for CMD_RES

Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout (5 ms). Timeout value is determined by the setting of the MMCSD1_UHS2_TIMER_CONTROL[3-0] CMDRESP_TIMEOUT_CTR bit field.

0h: Interrupt is not generated

1h: RES Packet Timeout Error
15 ADMA2_ADMA3 R/W1C 0h

ADMA2/3 Error

Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the MMCSD1_ADMA_ERR_STATUS register, which is defined in the Host spec 3.00.

0h: Interrupt is not generated

1h: ADMA2/3 Error
14-9 RESERVED R 0h

Reserved
8 EBSY R/W1C 0h

EBSY Error

On receiving EBSY packet, if the packet indicates an error, this bit is set to 1h. Setting of this bit also sets Error Interrupt and Transfer Completer together in the MMCSD1_NORMAL_INTR_STS register. This error check is effective for a command with setting the MMCSD1_UHS2_XFER_MODE[14] EBSY_WAIT bit.

0h: Interrupt is not generated

1h: EBSY Error (Backend Error)
7 UNRECOVERABLE R/W1C 0h

Unrecoverable Error

Setting of this bit means that Unrecoverable Error is set in a packet from a device.

0h: Interrupt is not generated

1h: Device Unrecoverable Error
6 RESERVED R 0h

Reserved
5 TID R/W1C 0h

TID Error

Setting of this bit means that TID Error occurs.

0h: Interrupt is not generated

1h: TID Error
4 FRAMING R/W1C 0h

Framing Error

Setting of this bit means that Framing Error occurs during a packet receiving.

0h: Interrupt is not generated

1h: Framing Error
3 CRC R/W1C 0h

CRC Error

Setting of this bit means that CRC Error occurs during a packet receiving.

0h: Interrupt is not generated

1h: CRC Error
2 RETRY_EXPIRED R/W1C 0h

Retry Expired

Setting of this bit means that Retry Counter Expired Error occurs during data transfer. If this bit is set, either Framing Error or CRC Error in this register shall be set.

0h: Interrupt is not generated

1h: Retry Expired Error
1 RESP_PKT R/W1C 0h

RES Packet Error

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If the MMCSD1_UHS2_XFER_MODE[7] RESP_ERR_CHK_ENA bit is set to 1h, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1h.

0h: Interrupt is not generated

1h: RES Packet Error
0 HEADER R/W1C 0h

Header Error

Setting of this bit means that Header Error occurs in a received packet.

0h: Interrupt is not generated

1h: Header Error

3.6.8.58 MMCSD1_UHS2_ERR_INTR_STS_ENA Register (Offset = C8h) [reset = 0h]

MMCSD1_UHS2_ERR_INTR_STS_ENA is shown in Figure 14-7480 and described in Table 14-15194.

Return to Summary Table.

This register is used to enable the MMCSD1_UHS2_ERR_INTR_STS register fields.

Table 14-15193 MMCSD1_UHS2_ERR_INTR_STS_ENA Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00C8h
Figure 14-7480 MMCSD1_UHS2_ERR_INTR_STS_ENA Register
31 30 29 28 27 26 25 24
VENDOR_SPECFIC RESERVED
R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DEADLOCK_TIMEOUT CMD_RESP_TIMEOUT
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
ADMA2_ADMA3 RESERVED EBSY
R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
UNRECOVERABLE RESERVED TID FRAMING CRC RETRY_EXPIRED RESP_PKT HEADER
R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15194 MMCSD1_UHS2_ERR_INTR_STS_ENA Register Field Descriptions
Bit Field Type Reset Description
31-27 VENDOR_SPECFIC R/W 0h

Vendor Specific Error

Setting this bit to 1h enables setting of Vendor Specific Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
26-18 RESERVED R 0h

Reserved
17 DEADLOCK_TIMEOUT R/W 0h

Timeout for Deadlock

Setting this bit to 1h enables setting of Timeout for Dead lock bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
16 CMD_RESP_TIMEOUT R/W 0h

Timeout for CMD_RES

Setting this bit to 1h enables setting of Timeout for CMD_RES bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
15 ADMA2_ADMA3 R/W 0h

ADMA2/3 Error

Setting this bit to 1h enables setting of ADMA2/3 Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
14-9 RESERVED R 0h

Reserved
8 EBSY R/W 0h

EBSY Error

Setting this bit to 1h enables setting of EBSY Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
7 UNRECOVERABLE R/W 0h

Unrecoverable Error

Setting this bit to 1h enables setting of Unrecoverable Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
6 RESERVED R 0h

Reserved
5 TID R/W 0h

TID Error

Setting this bit to 1h enables setting of TID Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
4 FRAMING R/W 0h

Framing Error

Setting this bit to 1h enables setting of Framing Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
3 CRC R/W 0h

CRC Error

Setting this bit to 1h enables setting of CRC Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
2 RETRY_EXPIRED R/W 0h

Retry Expired

Setting this bit to 1h enables setting of Retry Expired bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
1 RESP_PKT R/W 0h

RES Packet Error

Setting this bit to 1h enables setting of RES Packet Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
0 HEADER R/W 0h

Header Error

Setting this bit to 1h enables setting of Header Error bit in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled

3.6.8.59 MMCSD1_UHS2_ERR_INTR_SIG_ENA Register (Offset = CCh) [reset = 0h]

MMCSD1_UHS2_ERR_INTR_SIG_ENA is shown in Figure 14-7481 and described in Table 14-15196.

Return to Summary Table.

This register is used to generate UHS-II Interrupt signals.

Table 14-15195 MMCSD1_UHS2_ERR_INTR_SIG_ENA Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00CCh
Figure 14-7481 MMCSD1_UHS2_ERR_INTR_SIG_ENA Register
31 30 29 28 27 26 25 24
VENDOR_SPECFIC RESERVED
R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DEADLOCK_TIMEOUT CMD_RESP_TIMEOUT
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
ADMA2_ADMA3 RESERVED EBSY
R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
UNRECOVERABLE RESERVED TID FRAMING CRC RETRY_EXPIRED_SIG_ENA RESP_PKT HEADER
R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15196 MMCSD1_UHS2_ERR_INTR_SIG_ENA Register Field Descriptions
Bit Field Type Reset Description
31-27 VENDOR_SPECFIC R/W 0h

Vendor Specific Error

Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
26-18 RESERVED R 0h

Reserved
17 DEADLOCK_TIMEOUT R/W 0h

Timeout for Deadlock

Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
16 CMD_RESP_TIMEOUT R/W 0h

Timeout for CMD_RES

Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
15 ADMA2_ADMA3 R/W 0h

ADMA2/3 Error

Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
14-9 RESERVED R 0h

Reserved
8 EBSY R/W 0h

EBSY Error

Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
7 UNRECOVERABLE R/W 0h

Unrecoverable Error

Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
6 RESERVED R 0h

Reserved
5 TID R/W 0h

TID Error

Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
4 FRAMING R/W 0h

Framing Error

Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
3 CRC R/W 0h

CRC Error

Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
2 RETRY_EXPIRED_SIG_ENA R/W 0h

Retry Expired

Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
1 RESP_PKT R/W 0h

RES Packet Error

Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
0 HEADER R/W 0h

Header Error

Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled

3.6.8.60 MMCSD1_UHS2_SETTINGS_PTR Register (Offset = E0h) [reset = 100h]

MMCSD1_UHS2_SETTINGS_PTR is shown in Figure 14-7482 and described in Table 14-15198.

Return to Summary Table.

This register is pointer for UHS-II settings.

Table 14-15197 MMCSD1_UHS2_SETTINGS_PTR Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00E0h
Figure 14-7482 MMCSD1_UHS2_SETTINGS_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UHS2_SETTINGS_PTR
R-100h
LEGEND: R = Read Only; -n = value after reset
Table 14-15198 MMCSD1_UHS2_SETTINGS_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 UHS2_SETTINGS_PTR R 100h

Pointer for UHS-II Settings Register

3.6.8.61 MMCSD1_UHS2_CAPABILITIES_PTR Register (Offset = E2h) [reset = 110h]

MMCSD1_UHS2_CAPABILITIES_PTR is shown in Figure 14-7483 and described in Table 14-15200.

Return to Summary Table.

This register is pointer for UHS-II Capabilities Register.

Table 14-15199 MMCSD1_UHS2_CAPABILITIES_PTR Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00E2h
Figure 14-7483 MMCSD1_UHS2_CAPABILITIES_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UHS2_CAPABILITIES_PTR
R-110h
LEGEND: R = Read Only; -n = value after reset
Table 14-15200 MMCSD1_UHS2_CAPABILITIES_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 UHS2_CAPABILITIES_PTR R 110h

Pointer for UHS-II Capabilities Register

3.6.8.62 MMCSD1_UHS2_TEST_PTR Register (Offset = E4h) [reset = 120h]

MMCSD1_UHS2_TEST_PTR is shown in Figure 14-7484 and described in Table 14-15202.

Return to Summary Table.

This register is pointer for UHS-II Test Register.

Table 14-15201 MMCSD1_UHS2_TEST_PTR Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00E4h
Figure 14-7484 MMCSD1_UHS2_TEST_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UHS2_TEST_PTR
R-120h
LEGEND: R = Read Only; -n = value after reset
Table 14-15202 MMCSD1_UHS2_TEST_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 UHS2_TEST_PTR R 120h

Pointer for UHS-II Test Register

3.6.8.63 MMCSD1_SHARED_BUS_CTRL_PTR Register (Offset = E6h) [reset = 130h]

MMCSD1_SHARED_BUS_CTRL_PTR is shown in Figure 14-7485 and described in Table 14-15204.

Return to Summary Table.

This register is pointer for UHS-II Shared Bus Control Register.

Table 14-15203 MMCSD1_SHARED_BUS_CTRL_PTR Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00E6h
Figure 14-7485 MMCSD1_SHARED_BUS_CTRL_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHARED_BUS_CTRL_PTR
R-130h
LEGEND: R = Read Only; -n = value after reset
Table 14-15204 MMCSD1_SHARED_BUS_CTRL_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 SHARED_BUS_CTRL_PTR R 130h

Pointer for Shared Bus Control Register

3.6.8.64 MMCSD1_VENDOR_SPECFIC_PTR Register (Offset = E8h) [reset = 140h]

MMCSD1_VENDOR_SPECFIC_PTR is shown in Figure 14-7486 and described in Table 14-15206.

Return to Summary Table.

This register is pointer for UHS-II Vendor Specific Register.

Table 14-15205 MMCSD1_VENDOR_SPECFIC_PTR Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00E8h
Figure 14-7486 MMCSD1_VENDOR_SPECFIC_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VENDOR_SPECFIC_PTR
R-140h
LEGEND: R = Read Only; -n = value after reset
Table 14-15206 MMCSD1_VENDOR_SPECFIC_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 VENDOR_SPECFIC_PTR R 140h

Pointer for Vendor Specific Area

3.6.8.65 MMCSD1_BOOT_TIMEOUT_CONTROL Register (Offset = F4h) [reset = 0h]

MMCSD1_BOOT_TIMEOUT_CONTROL is shown in Figure 14-7487 and described in Table 14-15208.

Return to Summary Table.

This is used to program the boot timeout value counter.

Table 14-15207 MMCSD1_BOOT_TIMEOUT_CONTROL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00F4h
Figure 14-7487 MMCSD1_BOOT_TIMEOUT_CONTROL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_TIMEOUT_CNT
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15208 MMCSD1_BOOT_TIMEOUT_CONTROL Register Field Descriptions
Bit Field Type Reset Description
31-0 DATA_TIMEOUT_CNT R/W 0h

Boot Data Timeout Counter Value

This value determines the interval by which DAT line timeouts are detected during boot operation for eMMC4.4 card.

The value is in number of SD clock.

3.6.8.66 MMCSD1_VENDOR_REGISTER Register (Offset = F8h) [reset = 4E20h]

MMCSD1_VENDOR_REGISTER is shown in Figure 14-7488 and described in Table 14-15210.

Return to Summary Table.

Vendor register added for Auto Gate SD CLK, CMD11 Power Down Timer, Enhanced Strobe and eMMC Hardware Reset.

Table 14-15209 MMCSD1_VENDOR_REGISTER Instances
Instance Physical Address
MMCSD1_CTL_CFG 04FB 00F8h
Figure 14-7488 MMCSD1_VENDOR_REGISTER Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED AUTOGATE_SDCLK
R-0h R/W-0h
15 14 13 12 11 10 9 8
CMD11_PD_TIMER
R/W-1388h
7 6 5 4 3 2 1 0
CMD11_PD_TIMER EMMC_HW_RESET ENHANCED_STROBE
R/W-1388h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15210 MMCSD1_VENDOR_REGISTER Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h

Reserved
16 AUTOGATE_SDCLK R/W 0h

Auto Gate SD CLK

If this bit is set, SD CLK will be gated automatically when there is no transfer.

This is applicable only for Embedded Device.

0h: Disable

1h: Enable
15-2 CMD11_PD_TIMER R/W 1388h

CMD11 Power Down Timer Value
1 EMMC_HW_RESET R/W 0h

eMMC Hardware Reset

Hardware reset signal is generared for eMMC card when this bit is set.

0h: De-sassert hardware reset pin

1h: Drives the hardware reset pin as ZERO (Active LOW to eMMC card)
0 ENHANCED_STROBE R/W 0h

Enhanced Strobe

This bit enables the enhanced strobe logic of the Host Controller.

3.6.8.67 MMCSD1_SLOT_INT_STS Register (Offset = FCh) [reset = 0h]

MMCSD1_SLOT_INT_STS is shown in Figure 14-7489 and described in Table 14-15212.

Return to Summary Table.

This register is used to read the interrupt signal for each slot.

Table 14-15211 MMCSD1_SLOT_INT_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00FCh
Figure 14-7489 MMCSD1_SLOT_INT_STS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INTR_SIG
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15212 MMCSD1_SLOT_INT_STS Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h

Reserved
7-0 INTR_SIG R 0h

Interrupt Signal for Slot#0

These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot.

3.6.8.68 MMCSD1_HOST_CONTROLLER_VER Register (Offset = FEh) [reset = 1004h]

MMCSD1_HOST_CONTROLLER_VER is shown in Figure 14-7490 and described in Table 14-15214.

Return to Summary Table.

This register is used to read the vendor version number and specification version number.

Table 14-15213 MMCSD1_HOST_CONTROLLER_VER Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 00FEh
Figure 14-7490 MMCSD1_HOST_CONTROLLER_VER Register
15 14 13 12 11 10 9 8
VEN_VER_NUM
R-10h
7 6 5 4 3 2 1 0
SPEC_VER_NUM
R-4h
LEGEND: R = Read Only; -n = value after reset
Table 14-15214 MMCSD1_HOST_CONTROLLER_VER Register Field Descriptions
Bit Field Type Reset Description
15-8 VEN_VER_NUM R 10h

Vendor Version Number

The Vendor Version Number is set to 10h (1.0)
7-0 SPEC_VER_NUM R 4h

Specification Version Number

This status indicates the Host Controller Specification Version. The upper and lower 4-bits indicate the version.

0h: SD Host Controller Specification Version 1.00

1h: SD Host Controller Specification Version 2.00 Including the feature of the ADMA and Test Register

2h: SD Host Controller Specification Version 3.00

3h: SD Host Controller Specification Version 4.00

4h: SD Host Controller Specification Version 4.10

Others: Reserved

3.6.8.69 MMCSD1_UHS2_GEN_SETTINGS Register (Offset = 100h) [reset = 0h]

MMCSD1_UHS2_GEN_SETTINGS is shown in Figure 14-7491 and described in Table 14-15216.

Return to Summary Table.

Start Address of General settings is pointed by the MMCSD1_UHS2_SETTINGS_PTR Register.

Table 14-15215 MMCSD1_UHS2_GEN_SETTINGS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0100h
Figure 14-7491 MMCSD1_UHS2_GEN_SETTINGS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED NUMLANES
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED POWER_MODE
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15216 MMCSD1_UHS2_GEN_SETTINGS Register Field Descriptions
Bit Field Type Reset Description
31-14 RESERVED R 0h

Reserved
13-8 NUMLANES R/W 0h

Number of Lanes and Functionalities

The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional.

0h: 2 Lanes FD or 2L-HD

1h: Not Used

2h: 3 Lanes 2D1U-FD (Embedded)

3h: 3 Lanes 1D2U-FD (Embedded)

4h: 4 Lanes 2D2U-FD (Embedded)

Others: Reserved
7-1 RESERVED R 0h

Reserved
0 POWER_MODE R/W 0h

Power Mode

This field determines either Fast mode or Low Power mode. Host and all devices connected to the host shall be set to the same mode.

0h: Fast Mode

1h: Low Power Mode

3.6.8.70 MMCSD1_UHS2_PHY_SETTINGS Register (Offset = 104h) [reset = 0h]

MMCSD1_UHS2_PHY_SETTINGS is shown in Figure 14-7492 and described in Table 14-15218.

Return to Summary Table.

Start Address of PHY settings is pointed by the MMCSD1_UHS2_SETTINGS_PTR Register.

Table 14-15217 MMCSD1_UHS2_PHY_SETTINGS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0104h
Figure 14-7492 MMCSD1_UHS2_PHY_SETTINGS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
N_LSS_DIR N_LSS_SYN
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
HIBERNATE_ENA RESERVED
R/W-0h R-0h
7 6 5 4 3 2 1 0
SPEED_RANGE RESERVED
R/W-0h R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15218 MMCSD1_UHS2_PHY_SETTINGS Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h

Reserved
23-20 N_LSS_DIR R/W 0h

Host N_LSS_DIR

The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field.

0h: 8 x 16 LSS

1h: 8 x 1 LSS

2h: 8 x 2 LSS

3h: 8 x 3 LSS

.... ....

Fh: 8 x 15 LSS
19-16 N_LSS_SYN R/W 0h

Host N_LSS_SYN

The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field.

0h: 4 x 16 LSS

1h: 4 x 1 LSS

2h: 4 x 2 LSS 3h - 4 x 3 LSS

.... ....

Fh: 4 x 15 LSS
15 HIBERNATE_ENA R/W 0h

Hibernate Enable

After checking card capability of Hibernate mode, if all devices support Hibernate mode, this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode, VDD1 Power may be off.

0h: Hibernate Disabled

1h: Hibernate Enabled
14-8 RESERVED R 0h

Reserved
7-6 SPEED_RANGE R/W 0h

Speed Range

PLL multiplier is selected by this field. Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State.

0h: Range A (Defalt)

1h: Range B

2h: Reserved

3h: Reserved
5-0 RESERVED R 0h

Reserved

3.6.8.71 MMCSD1_UHS2_LNK_TRN_SETTINGS Register (Offset = 108h) [reset = 0h]

MMCSD1_UHS2_LNK_TRN_SETTINGS is shown in Figure 14-7493 and described in Table 14-15220.

Return to Summary Table.

Start Address of LINK/TRAN settings is pointed by the MMCSD1_UHS2_SETTINGS_PTR Register.

Table 14-15219 MMCSD1_UHS2_LNK_TRN_SETTINGS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0108h
Figure 14-7493 MMCSD1_UHS2_LNK_TRN_SETTINGS Register
63 62 61 60 59 58 57 56
RESERVED
R-0h
55 54 53 52 51 50 49 48
RESERVED
R-0h
47 46 45 44 43 42 41 40
RESERVED
R-0h
39 38 37 36 35 34 33 32
N_DATA_GAP
R/W-0h
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED RETRY_COUNT
R-0h R/W-0h
15 14 13 12 11 10 9 8
HOST_NFCU
R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15220 MMCSD1_UHS2_LNK_TRN_SETTINGS Register Field Descriptions
Bit Field Type Reset Description
63-40 RESERVED R 0h

Reserved
39-32 N_DATA_GAP R/W 0h

Host N_DATA_GAP

The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field.

00h: No Gap

01h: 1 LSS

02h: 2 LSS

03h: 3 LSS

.... ....

FFh: 255 LSS
31-18 RESERVED R 0h

Reserved
17-16 RETRY_COUNT R/W 0h

Retry Count

Data Burst retry count is set to this field.

00h: Retry Disabled

01h: 1 time

02h: 2 times

03h: 3 times
15-8 HOST_NFCU R/W 0h

Host N_FCU

Host Driver sets the number of blocks in Data Burst (Flow Control) to this field.

The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended considering buffer size.

00h: 256 Blocks

01h: 1 Block

02h: 2 Blocks

03h: 3 Blocks

.... ....

FFh: 255 Blocks
7-0 RESERVED R 0h

Reserved

3.6.8.72 MMCSD1_UHS2_GEN_CAP Register (Offset = 110h) [reset = 44F11h]

MMCSD1_UHS2_GEN_CAP is shown in Figure 14-7494 and described in Table 14-15222.

Return to Summary Table.

Start Address of General Capabilities is pointed by the MMCSD1_UHS2_GEN_CAP Register.

Table 14-15221 MMCSD1_UHS2_GEN_CAP Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0110h
Figure 14-7494 MMCSD1_UHS2_GEN_CAP Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
CORECFG_UHS2_BUS_TOPLOGY CORECFG_UHS2_MAX_DEVICES DEVICE_TYPE
R-0h R-1h R-0h
15 14 13 12 11 10 9 8
RESERVED CFG_64BIT_ADDRESSING NUM_LANES
R-0h R-1h R-Fh
7 6 5 4 3 2 1 0
GAP DAP
R-1h R-1h
LEGEND: R = Read Only; -n = value after reset
Table 14-15222 MMCSD1_UHS2_GEN_CAP Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h

Reserved
23-22 CORECFG_UHS2_BUS_TOPLOGY R 0h

Bus Topology

This field indicates one of bus topologies configured by a Host system.

0h: P2P Connection

1h: Ring Connection

2h: HUB Connection

3h: HUB is Connected in Ring
21-18 CORECFG_UHS2_MAX_DEVICES R 1h

Number of Devices Supported

This field indicates the maximum number of devices supported by the Host Controller.

0h: Not used

1h: 1 Devices

2h: 2 Devices

.... ....

Fh: 15 Devices
17-16 DEVICE_TYPE R 0h

Removable/Embedded

This field indicates device type configured by a Host system.

0h: Removable Card (P2P)

1h: Embedded Devices

2h: Embedded Devices + Removable Card

3h: Reserved
15 RESERVED R 0h

Reserved
14 CFG_64BIT_ADDRESSING R 1h

64-bit Addressing

This field indicates support of 64-bit addressing by the Host Controller.

0h: 32-bit Addressing is supported

1h: 32-bit and 64-bit Addressing is supported
13-8 NUM_LANES R Fh

Number of Lanes and Functionalities

This field indicates support of lanes by the Host Controller.

0 mean not supported and 1 means supported.

D08: 2L-HD

D09: 2D1U-FD

D10: 1D2U-FD

D11: 2D2U-FD

D12: Reserved

D13: Reserved
7-4 GAP R 1h

GAP (Group Allocation Power)

This field indicates the maximum capability of host power supply for a group configured by a Host system. This field is used to set the argument of DEVICE_INIT CCM.

0h: Not used

1h: 360 mW

2h: 720 mW

.... ....

Fh: 360 x 15 mW
3-0 DAP R 1h

DAP (Device Allocation Power)

This field indicates the maximum capability of host power supply for a device configured by a Host system. This field is used to set the argument of DEVICE_INIT CCMD.

0h: 360 mW (Default)

1h: 360 mW

2h: 720 mW

.... ....

Fh: 360 x 15 mW

3.6.8.73 MMCSD1_UHS2_PHY_CAP Register (Offset = 114h) [reset = 110000h]

MMCSD1_UHS2_PHY_CAP is shown in Figure 14-7495 and described in Table 14-15224.

Return to Summary Table.

Start Address of PHY Capabilities is pointed by the MMCSD1_UHS2_CAPABILITIES_PTR Register.

Table 14-15223 MMCSD1_UHS2_PHY_CAP Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0114h
Figure 14-7495 MMCSD1_UHS2_PHY_CAP Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
N_LSS_DIR N_LSS_SYN
R-1h R-1h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
SPEED_RANGE RESERVED
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15224 MMCSD1_UHS2_PHY_CAP Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h

Reserved
23-20 N_LSS_DIR R 1h

Host N_LSS_DIR

This field indicates the minimum N_LSS_DIR required by the Host Controller.

0h: 4 x 16 LSS

1h: 4 x 1 LSS

2h: 4 x 2 LSS

3h: 4 x 3 LSS

.... ....

Fh: 4 x 15 LSS
19-16 N_LSS_SYN R 1h

Host N_LSS_SYN

This field indicates the minimum N_LSS_SYN required by the Host Controller.

0h: 4 x 16 LSS

1h: 4 x 1 LSS

2h: 4 x 2 LSS

3h: 4 x 3 LSS

.... ....

Fh: 4 x 15 LSS
15-8 RESERVED R 0h

Reserved
7-6 SPEED_RANGE R 0h

Speed Range

This field indicates supported Speed Range by the Host Controller.

0h: Range A (Default)

1h: Range A and Range B

2h: Reserved

3h: Reserved
5-0 RESERVED R 0h

Reserved

3.6.8.74 MMCSD1_UHS2_LNK_TRN_CAP Register (Offset = 118h) [reset = 8120000100h]

MMCSD1_UHS2_LNK_TRN_CAP is shown in Figure 14-7496 and described in Table 14-15226.

Return to Summary Table.

Start Address of LINK/TRAN settings is pointed by the MMCSD1_UHS2_CAPABILITIES_PTR Register.

Table 14-15225 MMCSD1_UHS2_LNK_TRN_CAP Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0118h
Figure 14-7496 MMCSD1_UHS2_LNK_TRN_CAP Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
RESERVED
R-0h
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED N_DATA_GAP
R-0h R-81h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_BLK_LENGTH RESERVED
R-200h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
N_FCU RESERVED
R-1h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15226 MMCSD1_UHS2_LNK_TRN_CAP Register Field Descriptions
Bit Field Type Reset Description
63-40 RESERVED R 0h

Reserved
39-32 N_DATA_GAP R 81h

Host N_DATA_GAP

This field indicates the minimum number of data gap (DIDL) supported by the Host Controller.

00h: No Gap

01h: 1 LSS

02h: 2 LSS

03h: 3 LSS

.... ....

FFh: 255 LSS
31-20 MAX_BLK_LENGTH R 200h

Host Maximum Block Length

This field indicates maximum block length by the Host Controller.

000h: Not Used

001h: 1 byte

002h: 2 bytes

.... ....

200h: 512 bytes

.... ....

800h: 2048 bytes

801h - FFFh: Not Used
19-16 RESERVED R 0h

Reserved
15-8 N_FCU R 1h

Host N_FCU

This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller. This value is determined by supported buffer size.

00h: 256 Blocks

01h: 1 Block

02h: 2 Block

03h: 3 Block

.... ....

FFh: 255 Blocks
7-0 RESERVED R 0h

Reserved

3.6.8.75 MMCSD1_FORCE_UHSII_ERR_INT_STS Register (Offset = 120h) [reset = 0h]

MMCSD1_FORCE_UHSII_ERR_INT_STS is shown in Figure 14-7497 and described in Table 14-15228.

Return to Summary Table.

This register is not physically implemented, rather it is an address where the MMCSD1_UHS2_ERR_INTR_STS register can be written.

Table 14-15227 MMCSD1_FORCE_UHSII_ERR_INT_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0120h
Figure 14-7497 MMCSD1_FORCE_UHSII_ERR_INT_STS Register
31 30 29 28 27 26 25 24
VENDOR_SPECIFIC RESERVED
W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED TIMEOUT_DEADLOCK TIMEOUT_CMD_RES
R-0h W-0h W-0h
15 14 13 12 11 10 9 8
ADMA RESERVED EBSY
W-0h R-0h W-0h
7 6 5 4 3 2 1 0
UNRECOVERABLE RESERVED TID FRAMING CRC RETRY_EXPIRED RES_PKT HEADER
W-0h R-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 14-15228 MMCSD1_FORCE_UHSII_ERR_INT_STS Register Field Descriptions
Bit Field Type Reset Description
31-27 VENDOR_SPECIFIC W 0h

Force Event for Vendor Specific Error

0h: Not Affected

1h: Vendor Specific Error Status is set
26-18 RESERVED R 0h

Reserved
17 TIMEOUT_DEADLOCK W 0h

Force Event for Timeout for Deadlock

Setting this bit forces the Host Controller to set Timeout for Deadlock in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Timeout for Deadlock Error status is set
16 TIMEOUT_CMD_RES W 0h

Force Event for Timeout for CMD_RES

Setting this bit forces the Host Controller to set Timeout for CMD_RES in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Timout for CMD_RES Status is set
15 ADMA W 0h

Force Event for ADMA Error

Setting this bit forces the Host Controller to set ADMA Error in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: ADMA Error Status is set
14-9 RESERVED R 0h

Reserved
8 EBSY W 0h

Force Event for EBSY Error

Setting this bit forces the Host Controller to set EBSY Error in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: EBSY Error Status is set
7 UNRECOVERABLE W 0h

Force Event for Unrecoverable Error

Setting this bit forces the Host Controller to set Unrecoverable Error in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Unrecoverable Error Status is set
6 RESERVED R 0h

Reserved
5 TID W 0h

Force Event for TID Error

Setting this bit forces the Host Controller to set TID Error in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: TID Error Status is set
4 FRAMING W 0h

Force Event for Framing Error

Setting this bit forces the Host Controller to set Framing Error in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Framing Error Status is set
3 CRC W 0h

Force Event for CRC Error

Setting this bit forces the Host Controller to set CRC Error in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: CRC Error Status is set
2 RETRY_EXPIRED W 0h

Force Event for Retry Expired

Setting this bit forces the Host Controller to set Retry Expired in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Retry expired error status is set
1 RES_PKT W 0h

Force Event for RES Packet Error

Setting this bit forces the Host Controller to set RES Packet Error in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: RES packet error status is set
0 HEADER W 0h

Force Event for Header Error

Setting this bit forces the Host Controller to set Header Error in the MMCSD1_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Header error status is set

3.6.8.76 MMCSD1_CQ_VERSION Register (Offset = 200h) [reset = 510h]

MMCSD1_CQ_VERSION is shown in Figure 14-7498 and described in Table 14-15230.

Return to Summary Table.

This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE, in BCD format. The current version is rev 5.1.

The following table describes the CQBASE+00h: Command Queueing Version.

Table 14-15229 MMCSD1_CQ_VERSION Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0200h
Figure 14-7498 MMCSD1_CQ_VERSION Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED EMMC_MAJOR_VER_NUM
R-0h R-5h
7 6 5 4 3 2 1 0
EMMC_MINOR_VER_NUM EMMC_VERSION_SUFFIX
R-1h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15230 MMCSD1_CQ_VERSION Register Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h

Reserved
11-8 EMMC_MAJOR_VER_NUM R 5h

eMMC Major Version Number (digit left of decimal point), in BCD format
7-4 EMMC_MINOR_VER_NUM R 1h

eMMC Minor Version Number (digit right of decimal point), in BCD format
3-0 EMMC_VERSION_SUFFIX R 0h

eMMC Version Suffix (2nd digit right of decimal point), in BCD format

3.6.8.77 MMCSD1_CQ_CAPABILITIES Register (Offset = 204h) [reset = 30C8h]

MMCSD1_CQ_CAPABILITIES is shown in Figure 14-7499 and described in Table 14-15232.

Return to Summary Table.

This register is reserved for capability indication.

Table 14-15231 MMCSD1_CQ_CAPABILITIES Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0204h
Figure 14-7499 MMCSD1_CQ_CAPABILITIES Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
CF_MUL RESERVED CF_VAL
R-3h R-0h R-C8h
7 6 5 4 3 2 1 0
CF_VAL
R-C8h
LEGEND: R = Read Only; -n = value after reset
Table 14-15232 MMCSD1_CQ_CAPABILITIES Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h

Reserved
15-12 CF_MUL R 3h

Internal Timer Clock Frequency Multiplier (ITCFMUL)

ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details (MMCSD1_CQ_CAPABILITIES[9-0] CF_VAL).

Field Value Description:

0h: 0.001 MHz

1h: 0.01 MHz

2h: 0.1 MHz

3h: 1 MHz

4h: 10 MHz

Other values are reserved
11-10 RESERVED R 0h

Reserved
9-0 CF_VAL R C8h

Internal Timer Clock Frequency Value (ITCFVAL)

ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling.

The clock frequency is calculated as ITCFVAL × ITCFMUL.

For example, to encode 19.2 MHz ITCFVAL shall be
C0h (= 192 decimal) and ITCFMUL shall be 2h (0.1 MHz).

192 × 0.1 MHz = 19.2 MHz

3.6.8.78 MMCSD1_CQ_CONFIG Register (Offset = 208h) [reset = 0h]

MMCSD1_CQ_CONFIG is shown in Figure 14-7500 and described in Table 14-15234.

Return to Summary Table.

This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time.

Table 14-15233 MMCSD1_CQ_CONFIG Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0208h
Figure 14-7500 MMCSD1_CQ_CONFIG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DCMD_ENA RESERVED TASK_DESC_SIZE
R-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CQ_ENABLE
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15234 MMCSD1_CQ_CONFIG Register Field Descriptions
Bit Field Type Reset Description
31-13 RESERVED R 0h

Reserved
12 DCMD_ENA R/W 0h

Direct Command (DCMD) Enable

This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor, or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor.

Bit Value Description

0h: Task descriptor in slot #31 is a Data Transfer Task Descriptor

1h: Task descriptor in slot #31 is a DCMD Task Descriptor
11-9 RESERVED R 0h

Reserved
8 TASK_DESC_SIZE R/W 0h

Task Descriptor Size

This bit indicates whether the task descriptor size is 128 bits or 64 bits . This bit can only be configured when the MMCSD1_CQ_CONFIG[0] CQ_ENABLE bit is 0h (command queueing is disabled).

Bit Value Description

0h: Task descriptor size is 64 bits

1h: Task descriptor size is 128 bits
7-1 RESERVED R 0h

Reserved
0 CQ_ENABLE R/W 0h

Command Queueing Enable

Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE).

When this bit is 0h, CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller.

Before software writes 1h to this bit, software shall verify that the eMMC host controller is in idle state and there are no commands or data transfers ongoing.

When software wants to exit command queueing mode, it shall clear all previous tasks if such exist before setting this bit to 0h.

3.6.8.79 MMCSD1_CQ_CONTROL Register (Offset = 20Ch) [reset = 0h]

MMCSD1_CQ_CONTROL is shown in Figure 14-7501 and described in Table 14-15236.

Return to Summary Table.

This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time.

Table 14-15235 MMCSD1_CQ_CONTROL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 020Ch
Figure 14-7501 MMCSD1_CQ_CONTROL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CLEAR_ALL_TASKS
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED HALT_BIT
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15236 MMCSD1_CQ_CONTROL Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h

Reserved
8 CLEAR_ALL_TASKS R/W 0h

Clear All Tasks

Software shall write 1h to this bit when it wants to clear all the tasks sent to the device.

This bit can only be written when CQE is in halt state (Halt bit is 1h).

When software writes 1h, the value of the register is updated to 1h, and CQE shall reset the MMCSD1_CQ_TASK_DOOR_BELL register and all other context information for all unfinished tasks. Then CQE will clear this bit.

Software should poll on this bit until it is set to back 0 and may then resume normal operation, by clearing the Halt bit.

CQE does not communicate to the device that the tasks were cleared. It is softwares responsibility to order the device to discard the tasks in its queue using CMDQ_TASK_MGMT command.

Writing 0h to this register shall have no effect.
7-1 RESERVED R 0h

Reserved
0 HALT_BIT R/W 0h

Halt

Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus.

For example, issuing a Discard Task command (CMDQ_TASK_MGMT).

When software writes 1h, CQE shall complete the ongoing task if such a task is in progress.

Once the task is completed and CQE is in idle state, CQE shall not issue new commands and shall indicate so to software by setting this bit to 1h.

Software may poll on this bit until it is set to 1h, and may only then send commands on the eMMC bus.

In order to exit halt state (resume CQE activity), software shall clear this bit (write 0h). Writing 0h when the value is already 0h shall have no effect.

3.6.8.80 MMCSD1_CQ_INTR_STS Register (Offset = 210h) [reset = 0h]

MMCSD1_CQ_INTR_STS is shown in Figure 14-7502 and described in Table 14-15238.

Return to Summary Table.

This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event, only if the respective bit is set in the MMCSD1_CQ_INTR_STS_ENA register.

Table 14-15237 MMCSD1_CQ_INTR_STS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0210h
Figure 14-7502 MMCSD1_CQ_INTR_STS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TASK_ERROR TASK_CLEARED RESP_ERR_DET TASK_COMPLETE HALT_COMPLETE
R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 14-15238 MMCSD1_CQ_INTR_STS Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h

Reserved
4 TASK_ERROR R/W1C 0h

Task Error Interrupt (TERR)

This bit is asserted when task error is detected due to invalid task descriptor.
3 TASK_CLEARED R/W1C 0h

Task Cleared (TCL)

This status bit is asserted (if MMCSD1_CQ_INTR_STS_ENA[3] TASK_CLEARED = 1h) when a task clear operation is completed by CQE. The completed task clear operation is either an individual task clear (MMCSD1_CQ_TASK_CLEAR) or clearing of all tasks (MMCSD1_CQ_CONTROL).
2 RESP_ERR_DET R/W1C 0h

Response Error Detected Interrupt (RED)

This status bit is asserted (if MMCSD1_CQ_INTR_STS_ENA[2] RESP_ERR_DET = 1h) when a response is received with an error bit set in the device status field.

Software uses the MMCSD1_CQ_RESP_ERR_MASK register to configure which device status bit fields may trigger an interrupt, and which are masked.
1 TASK_COMPLETE R/W1C 0h

Task Complete Interrupt (TCC)

This status bit is asserted (if MMCSD1_CQ_INTR_STS_ENA[1] TASK_COMPLETE = 1h) when at least one of the following two conditions are met:

(1) A task is completed and the INT bit is set in its Task Descriptor

(2) Interrupt caused by Interrupt Coalescing logic

0 HALT_COMPLETE R/W1C 0h

Halt Complete Interrupt (HAC)

This status bit is asserted (if MMCSD1_CQ_INTR_STS_ENA[0] HALT_COMPLETE = 1h) when the MMCSD1_CQ_CONTROL[0] HALT_BIT bit transitions from 0h to 1h indicating that host controller has completed its current ongoing task and has entered halt state.

3.6.8.81 MMCSD1_CQ_INTR_STS_ENA Register (Offset = 214h) [reset = 0h]

MMCSD1_CQ_INTR_STS_ENA is shown in Figure 14-7503 and described in Table 14-15240.

Return to Summary Table.

This register enables and disables the reporting of the corresponding interrupt to host software in 299 MMCSD1_CQ_INTR_STS register. When a bit is set (1h) and the corresponding interrupt condition is active, then the 300 bit in the MMCSD1_CQ_INTR_STS register is asserted. Interrupt sources that are disabled (0h) are not indicated in the MMCSD1_CQ_INTR_STS 301 register. This register is bit-index matched to the MMCSD1_CQ_INTR_STS register.

Table 14-15239 MMCSD1_CQ_INTR_STS_ENA Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0214h
Figure 14-7503 MMCSD1_CQ_INTR_STS_ENA Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TASK_ERROR TASK_CLEARED RESP_ERR_DET TASK_COMPLETE HALT_COMPLETE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15240 MMCSD1_CQ_INTR_STS_ENA Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h

Reserved
4 TASK_ERROR R/W 0h

Task Error Interrupt Status Enable (TERR)

1h: MMCSD1_CQ_INTR_STS[4] TASK_ERROR bit will be set when its interrupt condition is active

0h: MMCSD1_CQ_INTR_STS[4] TASK_ERROR bit is disabled
3 TASK_CLEARED R/W 0h

Task Cleared Status Enable (TCL)

1h: MMCSD1_CQ_INTR_STS[3] TASK_CLEARED bit will be set when its interrupt condition is active

0h: MMCSD1_CQ_INTR_STS[3] TASK_CLEARED bit is disabled
2 RESP_ERR_DET R/W 0h

Response Error Detected Status Enable (RED)

1h: MMCSD1_CQ_INTR_STS[2] RESP_ERR_DET bit will be set when its interrupt condition is active

0h: MMCSD1_CQ_INTR_STS[2] RESP_ERR_DET bit is disabled
1 TASK_COMPLETE R/W 0h

Task Complete Status Enable (TCC)

1h: MMCSD1_CQ_INTR_STS[1] TASK_COMPLETE bit will be set when its interrupt condition is active

0h: MMCSD1_CQ_INTR_STS[1] TASK_COMPLETE bit is disabled
0 HALT_COMPLETE R/W 0h

Halt Complete Status Enable (HAC)

1h: MMCSD1_CQ_INTR_STS[0] HALT_COMPLETE bit will be set when its interrupt condition is active

0h: MMCSD1_CQ_INTR_STS[0] HALT_COMPLETE bit is disabled

3.6.8.82 MMCSD1_CQ_INTR_SIG_ENA Register (Offset = 218h) [reset = 0h]

MMCSD1_CQ_INTR_SIG_ENA is shown in Figure 14-7504 and described in Table 14-15242.

Return to Summary Table.

This register enables and disables the generation of interrupts to host software. When a bit is set 304 (1h) and the corresponding bit in the MMCSD1_CQ_INTR_STS register is set, then an interrupt is generated. Interrupt sources 305 that are disabled (0h) are still indicated in the MMCSD1_CQ_INTR_STS register. This register is bit-index matched 306 to the MMCSD1_CQ_INTR_STS register.

Table 14-15241 MMCSD1_CQ_INTR_SIG_ENA Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0218h
Figure 14-7504 MMCSD1_CQ_INTR_SIG_ENA Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TASK_ERROR TASK_CLEARED RESP_ERR_DET TASK_COMPLETE HALT_COMPLETE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15242 MMCSD1_CQ_INTR_SIG_ENA Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h

Reserved
4 TASK_ERROR R/W 0h

Task Error Interrupt Signal Enable (TERR)

When set and the MMCSD1_CQ_INTR_STS[4] TASK_ERROR bit is asserted, the CQE shall generate an interrupt.
3 TASK_CLEARED R/W 0h

Task Cleared Signal Enable (TCL)

When set and the MMCSD1_CQ_INTR_STS[3] TASK_CLEARED bit is asserted, the CQE shall generate an interrupt.
2 RESP_ERR_DET R/W 0h

Response Error Detected Signal Enable (RED)

When set and the MMCSD1_CQ_INTR_STS[2] RESP_ERR_DET bit is asserted, the CQE shall generate an interrupt.
1 TASK_COMPLETE R/W 0h

Task Complete Signal Enable (TCC)

When set and the MMCSD1_CQ_INTR_STS[1] TASK_COMPLETE bit is asserted, the CQE shall generate an interrupt.
0 HALT_COMPLETE R/W 0h

Halt Complete Signal Enable (HAC)

When set and the MMCSD1_CQ_INTR_STS[0] HALT_COMPLETE bit is asserted, the CQE shall generate an interrupt.

3.6.8.83 MMCSD1_CQ_INTR_COALESCING Register (Offset = 21Ch) [reset = 0h]

MMCSD1_CQ_INTR_COALESCING is shown in Figure 14-7505 and described in Table 14-15244.

Return to Summary Table.

This register controls the interrupt coalescing feature.

Table 14-15243 MMCSD1_CQ_INTR_COALESCING Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 021Ch
Figure 14-7505 MMCSD1_CQ_INTR_COALESCING Register
31 30 29 28 27 26 25 24
CQINTCOALESC_ENABLE RESERVED
R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED IC_STATUS RESERVED
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED CTR_THRESHOLD
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TIMEOUT_VAL
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15244 MMCSD1_CQ_INTR_COALESCING Register Field Descriptions
Bit Field Type Reset Description
31 CQINTCOALESC_ENABLE R/W 0h

Interrupt Coalescing Enable/Disable:

When set to 0h by software, command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT = 1 in the Task Descriptor.

When set to 1h, the interrupt coalescing mechanism is enabled and coalesced interrupts are generated.
30-21 RESERVED R 0h

Reserved
20 IC_STATUS R 0h

Interrupt Coalescing Status Bit (ICSB):

This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter > 0).

Bit Value Description

0h: No task completions have occurred since last counter reset (IC counter = 0)

1h: At least one task completion has been counted (IC counter > 0)
19-13 RESERVED R 0h

Reserved
12-8 CTR_THRESHOLD R/W 0h

Interrupt Coalescing Counter Threshold (ICCTH):

Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt.

Counter Operation: As data transfer tasks with INT = 0 complete, they are counted by CQE. The counter is reset by software during the interrupt service routine.

The counter stops counting when it reaches the value configured in ICCTH.

The maximum allowed value is 31.

Note: When ICCTH is 0h, task completions are not counted, and counting-based interrupts are not generated.
7 RESERVED R 0h

Reserved
6-0 TIMEOUT_VAL R/W 0h

Interrupt Coalescing Timeout Value (ICTOVAL):

Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt.

Timer Operation: The timer is reset by software during the interrupt service routine.

It starts running when a data transfer task with INT = 0 is completed, after the timer was reset. When the timer reaches the value configured in ICTOVAL field it generates an interrupt and stops.

The timers unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field in the MMCSD1_CQ_CAPABILITIES register.

The minimum value is 1h (1024 clock periods) and the maximum value is 7Fh (127 × 1024 clock periods).

For example, a MMCSD1_CQ_CAPABILITIES field value of 0h indicates a 19.2 MHz clock frequency (period = 52.08 ns). If the setting in ICTOVAL is 10h, the calculated polling period is 16 × 1024 × 52.08 ns = 853.33 µs

Note: When ICTOVAL is 0h, the timer is not running, and timer-based interrupts are not generated.

3.6.8.84 MMCSD1_CQ_TDL_BASE_ADDR Register (Offset = 220h) [reset = 0h]

MMCSD1_CQ_TDL_BASE_ADDR is shown in Figure 14-7506 and described in Table 14-15246.

Return to Summary Table.

This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory.

Table 14-15245 MMCSD1_CQ_TDL_BASE_ADDR Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0220h
Figure 14-7506 MMCSD1_CQ_TDL_BASE_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTDLBA_LO
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15246 MMCSD1_CQ_TDL_BASE_ADDR Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTDLBA_LO R/W 0h

Task Descriptor List Base Address (TDLBA)

This register stores the LSB bits (bits 31-0) of the byte address of the head of the Task Descriptor List in system memory.

The size of the task descriptor list is 32 × (Task Descriptor size + Transfer Descriptor size) as configured by Host driver.

This address shall be set on Byte1 KByte boundary.

The lower 10 bits of this register shall be set to 0h by software and shall be ignored by CQE.

3.6.8.85 MMCSD1_CQ_TDL_BASE_ADDR_UPBITS Register (Offset = 224h) [reset = 0h]

MMCSD1_CQ_TDL_BASE_ADDR_UPBITS is shown in Figure 14-7507 and described in Table 14-15248.

Return to Summary Table.

This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory.

Table 14-15247 MMCSD1_CQ_TDL_BASE_ADDR_UPBITS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0224h
Figure 14-7507 MMCSD1_CQ_TDL_BASE_ADDR_UPBITS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTDLBA_HI
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15248 MMCSD1_CQ_TDL_BASE_ADDR_UPBITS Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTDLBA_HI R/W 0h

Task Descriptor List Base Address (TDLBA)

This register stores the MSB bits (bits 63-32) of the byte address of the head of the Task Descriptor List in system memory.

The size of the task descriptor list is 32 × (Task Descriptor size + Transfer Descriptor size) as configured by Host driver.

This register is reserved when using 32-bit addressing mode.

3.6.8.86 MMCSD1_CQ_TASK_DOOR_BELL Register (Offset = 228h) [reset = 0h]

MMCSD1_CQ_TASK_DOOR_BELL is shown in Figure 14-7508 and described in Table 14-15250.

Return to Summary Table.

Using this register, software triggers CQE to process a new task.

Table 14-15249 MMCSD1_CQ_TASK_DOOR_BELL Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0228h
Figure 14-7508 MMCSD1_CQ_TASK_DOOR_BELL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTDB_VAL
W1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 14-15250 MMCSD1_CQ_TASK_DOOR_BELL Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTDB_VAL W1S 0h

Command Queueing Task Doorbell

Software shall configure the MMCSD1_CQ_TDL_BASE_ADDR[31-0] CQTDLBA_LO and MMCSD1_CQ_TDL_BASE_ADDR_UPBITS[31-0] CQTDLBA_HI bit fields, and enable CQE in the MMCSD1_CQ_CONFIG register before using this register.

Writing 1h to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL.

CQE always processes tasks in-order according to the order submitted to the list by the MMCSD1_CQ_TASK_DOOR_BELL register write transactions.

CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to the device.

CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument.

The corresponding bit is cleared to 0h by CQE in one of the following events:

(a) When a task execution is completed (with success or error)

(b) The task is cleared using MMCSD1_CQ_TASK_CLEAR register

(c) All tasks are cleared using MMCSD1_CQ_CONTROL register

(d) CQE is disabled using MMCSD1_CQ_CONFIG register

Software may initiate multiple tasks at the same time (batch submission) by writing 1h to multiple bits of this register in the same transaction.

In the case of batch submission:

CQE shall process the tasks in order of the task index, starting with the lowest index.

If one or more tasks in the batch are marked with QBR, the ordering of execution will be based on said processing order.

Writing 0h by software shall have no impact on the hardware, and will not change the value of the register bit.

3.6.8.87 MMCSD1_CQ_TASK_COMP_NOTIF Register (Offset = 22Ch) [reset = 0h]

MMCSD1_CQ_TASK_COMP_NOTIF is shown in Figure 14-7509 and described in Table 14-15252.

Return to Summary Table.

This register is used by CQE to notify software about completed tasks.

Table 14-15251 MMCSD1_CQ_TASK_COMP_NOTIF Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 022Ch
Figure 14-7509 MMCSD1_CQ_TASK_COMP_NOTIF Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTCN_VAL
R/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 14-15252 MMCSD1_CQ_TASK_COMP_NOTIF Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTCN_VAL R/W1C 0h

Task Complete Notification

CQE shall set bit n of this register (at the same time it clears bit n of the MMCSD1_CQ_TASK_DOOR_BELL register) when a task execution is completed (with success or error).

When receiving interrupt for task completion, software may read this register to know which tasks have finished. After reading this register, software may clear the relevant bit fields by writing 1h to the corresponding bits.

3.6.8.88 MMCSD1_CQ_DEV_QUEUE_STATUS Register (Offset = 230h) [reset = 0h]

MMCSD1_CQ_DEV_QUEUE_STATUS is shown in Figure 14-7510 and described in Table 14-15254.

Return to Summary Table.

This register stores the most recent value of the device's queue status.

Table 14-15253 MMCSD1_CQ_DEV_QUEUE_STATUS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0230h
Figure 14-7510 MMCSD1_CQ_DEV_QUEUE_STATUS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQDQ_STS
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15254 MMCSD1_CQ_DEV_QUEUE_STATUS Register Field Descriptions
Bit Field Type Reset Description
31-0 CQDQ_STS R 0h

Device Queue Status

Every time the Host controller receives a queue status register (QSR) from the device, it updates this register with the response of status command (the device's queue status).

3.6.8.89 MMCSD1_CQ_DEV_PENDING_TASKS Register (Offset = 234h) [reset = 0h]

MMCSD1_CQ_DEV_PENDING_TASKS is shown in Figure 14-7511 and described in Table 14-15256.

Return to Summary Table.

This register indicates to software which tasks are queued in the device, awaiting execution.

Table 14-15255 MMCSD1_CQ_DEV_PENDING_TASKS Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0234h
Figure 14-7511 MMCSD1_CQ_DEV_PENDING_TASKS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQDP_TSKS
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15256 MMCSD1_CQ_DEV_PENDING_TASKS Register Field Descriptions
Bit Field Type Reset Description
31-0 CQDP_TSKS R 0h

Device Pending Tasks

Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task hasnt been executed yet.

CQE shall set this bit after receiving a successful response for CMD45. CQE shall clear this bit after the task has completed execution.

Software needs to read this register in the task-discard procedure, when the controller is halted, to determine if the task is queued in the device. If the task is queued, the driver sends a CMDQ_TASK_MGMT (CMD48) to the device ordering it to discard the task. Then software clears the task in the CQE. Only then the software orders CQE to resume its operation using MMCSD1_CQ_CONTROL register.

3.6.8.90 MMCSD1_CQ_TASK_CLEAR Register (Offset = 238h) [reset = 0h]

MMCSD1_CQ_TASK_CLEAR is shown in Figure 14-7512 and described in Table 14-15258.

Return to Summary Table.

This register is used for removing an outstanding task in the CQE 327. The register should be used only when CQE is in Halt state.

Table 14-15257 MMCSD1_CQ_TASK_CLEAR Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0238h
Figure 14-7512 MMCSD1_CQ_TASK_CLEAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTCLR
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 14-15258 MMCSD1_CQ_TASK_CLEAR Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTCLR R/W 0h

Command Queueing Task Clear

Writing 1h to bit n of this register orders CQE to clear a task which software has previously issued.

This bit can only be written when CQE is in Halt state as indicated in the MMCSD1_CQ_CONFIG register Halt bit.

When software writes 1h to a bit in this register, CQE updates the value to 1h, and starts clearing the data structures related to the task. CQE clears the bit fields (sets a value of 0h) in the MMCSD1_CQ_TASK_CLEAR and in MMCSD1_CQ_TASK_DOOR_BELL registers once clear operation is complete.

Software should poll on the MMCSD1_CQ_TASK_CLEAR register until it is cleared to verify clear operation was complete.

Writing to this register only clears the task in the CQE and does not have impact on the device. In order to discard the task in the device, host software shall send CMDQ_TASK _MGMT while CQE is still in Halt state.

Host driver is not allowed to use this register to clear multiple tasks at the same time. Clearing multiple tasks can be done using MMCSD1_CQ_CONTROL register.

Writing 0h to a register bit shall have no impact.

3.6.8.91 MMCSD1_CQ_SEND_STS_CONFIG1 Register (Offset = 240h) [reset = 11000h]

MMCSD1_CQ_SEND_STS_CONFIG1 is shown in Figure 14-7513 and described in Table 14-15260.

Return to Summary Table.

The register controls when the SEND_QUEUE_STATUS commands are sent.

Table 14-15259 MMCSD1_CQ_SEND_STS_CONFIG1 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0240h
Figure 14-7513 MMCSD1_CQ_SEND_STS_CONFIG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CMD_BLK_CNTR
R-0h R/W-1h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD_IDLE_TIMER
R/W-1000h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15260 MMCSD1_CQ_SEND_STS_CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R 0h

Reserved
19-16 CMD_BLK_CNTR R/W 1h

Send Status Command Block Counter

This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue.

A value of n means CQE shall send status command on the CMD line, during the transfer of data block BLOCK_CNT-n, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction.

A value of 0h means that SEND_QUEUE_STATUS (CMD13) command shall not be sent during the transaction. Instead it will be sent only when the data lines are idle.

A value of 1 means that STATUS command is to be sent during the last block of the transaction.
15-0 CMD_IDLE_TIMER R/W 1000h

Send Status Command Idle Timer

This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling.

Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. When a SEND_QUEUE_STATUS response indicating that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS.

Timer units are clock periods of theclock whose frequency is specified in the Internal Timer Clock Frequency field in the MMCSD1_CQ_CAPABILITIES register.

The minimum value is 1h (1 clock period) and the maximum value is FFFFh (65535 clock periods). Default interval is: 4096 clock periods.

For example, a MMCSD1_CQ_CAPABILITIES field value of 0h indicates a 19.2 MHz clock frequency (period = 52.08 ns).

3.6.8.92 MMCSD1_CQ_SEND_STS_CONFIG2 Register (Offset = 244h) [reset = 0h]

MMCSD1_CQ_SEND_STS_CONFIG2 is shown in Figure 14-7514 and described in Table 14-15262.

Return to Summary Table.

This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument.

Table 14-15261 MMCSD1_CQ_SEND_STS_CONFIG2 Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0244h
Figure 14-7514 MMCSD1_CQ_SEND_STS_CONFIG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED QUEUE_RCA
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 14-15262 MMCSD1_CQ_SEND_STS_CONFIG2 Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h

Reserved
15-0 QUEUE_RCA R/W 0h

Send Queue RCA

This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument.

CQE shall copy this field to bits 31-16 of the argument when transmitting SEND_QUEUE_STATUS (CMD13) command.

3.6.8.93 MMCSD1_CQ_DCMD_RESPONSE Register (Offset = 248h) [reset = 0h]

MMCSD1_CQ_DCMD_RESPONSE is shown in Figure 14-7515 and described in Table 14-15264.

Return to Summary Table.

This register is used for passing the response of a DCMD task to software.

Table 14-15263 MMCSD1_CQ_DCMD_RESPONSE Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0248h
Figure 14-7515 MMCSD1_CQ_DCMD_RESPONSE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST_RESP
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15264 MMCSD1_CQ_DCMD_RESPONSE Register Field Descriptions
Bit Field Type Reset Description
31-0 LAST_RESP R 0h

Direct Command Last Response

This register contains the response of the command generated by the last direct command (DCMD) task which was sent.

CQE shall update this register when it receives the response for a DCMD task.

This register is considered valid only after bit 31 of the MMCSD1_CQ_TASK_DOOR_BELL register is cleared by CQE.

3.6.8.94 MMCSD1_CQ_RESP_ERR_MASK Register (Offset = 250h) [reset = FDF9A080h]

MMCSD1_CQ_RESP_ERR_MASK is shown in Figure 14-7516 and described in Table 14-15266.

Return to Summary Table.

This register controls the generation of Response Error Detection (RED) interrupt.

Table 14-15265 MMCSD1_CQ_RESP_ERR_MASK Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0250h
Figure 14-7516 MMCSD1_CQ_RESP_ERR_MASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQRMEM
R-FDF9A080h
LEGEND: R = Read Only; -n = value after reset
Table 14-15266 MMCSD1_CQ_RESP_ERR_MASK Register Field Descriptions
Bit Field Type Reset Description
31-0 CQRMEM R FDF9A080h

Response Mode Error Mask

This bit is used as in interrupt mask on the device status field which is received in R1/R1b responses.

Bit Value Description (for any bit i):

1h: When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated

0h: When a R1/R1b response is received, bit i in the device status is ignored

The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status.

Note: Responses to CMD13 (SQS) encode the QSR, so they are ignored by this logic.

3.6.8.95 MMCSD1_CQ_TASK_ERR_INFO Register (Offset = 254h) [reset = 0h]

MMCSD1_CQ_TASK_ERR_INFO is shown in Figure 14-7517 and described in Table 14-15268.

Return to Summary Table.

This register is updated by CQE when an error occurs on data or command related to a task activity. When such error is detected by CQE or indicated by the eMMC controller CQE stores in the MMCSD1_CQ_TASK_ERR_INFO register the task IDs and the command indices of the commands which were executed on the 343 command line and data lines when the error occurred.

Software is expected to use this information in the error recovery procedure.

Table 14-15267 MMCSD1_CQ_TASK_ERR_INFO Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0254h
Figure 14-7517 MMCSD1_CQ_TASK_ERR_INFO Register
31 30 29 28 27 26 25 24
DATERR_VALID RESERVED DATERR_TASK_ID
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DATERR_CMD_INDEX
R-0h R-0h
15 14 13 12 11 10 9 8
RESP_MODE_VALID RESERVED RESP_MODE_TASK_ID
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED RESP_MODE_CMD_INDEX
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15268 MMCSD1_CQ_TASK_ERR_INFO Register Field Descriptions
Bit Field Type Reset Description
31 DATERR_VALID R 0h

Data Transfer Error Fields Valid

This bit is updated when an error is detected by CQE, or indicated by eMMC controller.

If a data transfer is in progress when the error is detected/indicated, the bit is set to 1h.

If a no data transfer is in progress when the error is detected/indicated, the bit is cleared to 0h.
30-29 RESERVED R 0h

Reserved
28-24 DATERR_TASK_ID R 0h

Data Transfer Error Task ID

This field indicates the ID of the task which was executed on the data lines when an error occurred.

The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller.
23-22 RESERVED R 0h

Reserved
21-16 DATERR_CMD_INDEX R 0h

Data Transfer Error Command Index

This field indicates the index of the command which was executed on the data lines when an error occurred.

The index shall be set to EXECUTE_READ_TASK (CMD46) or EXECUTE_WRITE_TASK (CMD47) according to the data direction.

The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller.
15 RESP_MODE_VALID R 0h

Response Mode Error Fields Valid

This bit is updated when an error is detected by CQE, or indicated by eMMC controller.

If a command transaction is in progress when the error is detected/indicated, the bit is set to 1h.

If a no command transaction is in progress when the error is detected/indicated, the bit is cleared to 0h.
14-13 RESERVED R 0h

Reserved
12-8 RESP_MODE_TASK_ID R 0h

Response Mode Error Task ID

This field indicates the ID of the task which was executed on the command line when an error occurred.

The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller.
7-6 RESERVED R 0h

Reserved
5-0 RESP_MODE_CMD_INDEX R 0h

Response Mode Error Command Index

This field indicates the index of the command which was executed on the command line when an error occurred.

The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller.

3.6.8.96 MMCSD1_CQ_CMD_RESP_INDEX Register (Offset = 258h) [reset = 0h]

MMCSD1_CQ_CMD_RESP_INDEX is shown in Figure 14-7518 and described in Table 14-15270.

Return to Summary Table.

This register stores the index of the last received command response.

Table 14-15269 MMCSD1_CQ_CMD_RESP_INDEX Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0258h
Figure 14-7518 MMCSD1_CQ_CMD_RESP_INDEX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LAST_CRI
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15270 MMCSD1_CQ_CMD_RESP_INDEX Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h

Reserved
5-0 LAST_CRI R 0h

Last Command Response Index

This field stores the index of the last received command response. CQE shall update the value every time a command response is received.

3.6.8.97 MMCSD1_CQ_CMD_RESP_ARG Register (Offset = 25Ch) [reset = 0h]

MMCSD1_CQ_CMD_RESP_ARG is shown in Figure 14-7519 and described in Table 14-15272.

Return to Summary Table.

This register stores the index of the last received command response.

Table 14-15271 MMCSD1_CQ_CMD_RESP_ARG Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 025Ch
Figure 14-7519 MMCSD1_CQ_CMD_RESP_ARG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST_CRA
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15272 MMCSD1_CQ_CMD_RESP_ARG Register Field Descriptions
Bit Field Type Reset Description
31-0 LAST_CRA R 0h

Last Command Response Argument

This field stores the argument of the last received command. CQE shall update the value every time a command response is received.

3.6.8.98 MMCSD1_CQ_ERROR_TASK_ID Register (Offset = 260h) [reset = 0h]

MMCSD1_CQ_ERROR_TASK_ID is shown in Figure 14-7520 and described in Table 14-15274.

Return to Summary Table.

CQ Error Task ID Register

Table 14-15273 MMCSD1_CQ_ERROR_TASK_ID Instances
Instance Physical Address
MMCSD1_CTL_CFG 0FA0 0260h
Figure 14-7520 MMCSD1_CQ_ERROR_TASK_ID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TERR_ID
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 14-15274 MMCSD1_CQ_ERROR_TASK_ID Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h

Reserved
4-0 TERR_ID R 0h

Task Error ID