SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
| PSC | Power Domain Name | LPSC Name | LPSC Index | Default State | Software Controllable | Modules |
|---|---|---|---|---|---|---|
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | CMP_EVENT_INTROUTER0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | CTRL_MMR0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAIN_GPIOMUX_INTROUTER0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | PLL0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAIN_SEC_MMR0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMESYNC_EVENT_INTROUTER0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | PADCFG_CTRL0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | CPT2_AGGR0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DCC0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DCC1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DCC2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DCC3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DCC4 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DCC5 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_BCDMA_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_CBASS_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_ECC_AGGR_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_INTAGGR_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_IPCSS_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_PKTDMA_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_PSILCFG_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_PSILSS_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_RINGACC_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DMASS0_SEC_PROXY_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER10 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER11 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER4 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER5 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER6 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER7 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER8 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMER9 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | ECAP0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | ECAP1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | ECAP2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EQEP0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EQEP1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EQEP2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | ESM0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSIRX0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSIRX1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSIRX2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSIRX3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSIRX4 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSIRX5 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSITX0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSITX1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSS0_FSAS_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | FSS0_OSPI_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | GICSS0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | GPIO0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | GPIO1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | GTC0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EFUSE0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | CPTS0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | DDPA0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM4 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM5 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM6 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM7 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | EPWM8 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | VTM0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAILBOX0_MAILBOX_CLUSTER_0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAILBOX0_MAILBOX_CLUSTER_1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAILBOX0_MAILBOX_CLUSTER_2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAILBOX0_MAILBOX_CLUSTER_3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAILBOX0_MAILBOX_CLUSTER_4 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAILBOX0_MAILBOX_CLUSTER_5 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAILBOX0_MAILBOX_CLUSTER_6 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MAILBOX0_MAILBOX_CLUSTER_7 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | I2C0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | I2C1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | I2C2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | I2C3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MSRAM_256K0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MSRAM_256K1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MSRAM_256K2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MSRAM_256K3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MSRAM_256K4 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MSRAM_256K5 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MSRAM_256K6 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MSRAM_256K7 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | PDMA0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | PDMA1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | PSRAMECC0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | ROM0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MCSPI0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MCSPI1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MCSPI2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MCSPI3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | MCSPI4 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | SPINLOCK0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | TIMERMGR0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | UART0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | UART1 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | UART2 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | UART3 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | UART4 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | UART5 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_ALWAYSON | 0 | ON | NO | UART6 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_TEST | 1 | ON | YES | DFTSS0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_PBIST | 2 | ON | YES | PBIST0 |
| PSC0 | GP_CORE_CTL | LPSC_MAIN_PBIST | 2 | ON | YES | PBIST1 |
| PSC0 | GP_CORE_CTL | LPSC_MMC4B_0 | 4 | OFF | YES | MMCSD1 |
| PSC0 | GP_CORE_CTL | LPSC_MMC8B_0 | 5 | OFF | YES | MMCSD0 |
| PSC0 | GP_CORE_CTL | LPSC_USB | 6 | OFF | YES | USB0 |
| PSC0 | GP_CORE_CTL | LPSC_ADC | 7 | OFF | YES | ADC0 |
| PSC0 | GP_CORE_CTL | LPSC_DEBUGSS | 8 | ON | YES | DBGSUSPENDROUTER0 |
| PSC0 | GP_CORE_CTL | LPSC_DEBUGSS | 8 | ON | YES | STM0 |
| PSC0 | GP_CORE_CTL | LPSC_DEBUGSS | 8 | ON | YES | DEBUGSS_WRAP0 |
| PSC0 | GP_CORE_CTL | LPSC_DEBUGSS | 8 | ON | YES | DEBUGSS0 |
| PSC0 | GP_CORE_CTL | LPSC_GPMC | 9 | OFF | YES | ELM0 |
| PSC0 | GP_CORE_CTL | LPSC_GPMC | 9 | OFF | YES | GPMC0 |
| PSC0 | GP_CORE_CTL | LPSC_EMIF_CFG_0 | 10 | OFF | YES | DDR16SS0 |
| PSC0 | GP_CORE_CTL | LPSC_MCAN_0 | 12 | OFF | YES | MCAN0 |
| PSC0 | GP_CORE_CTL | LPSC_MCAN_1 | 13 | OFF | YES | MCAN1 |
| PSC0 | GP_CORE_CTL | LPSC_SAUL | 14 | ON | YES | SA2_UL0 |
| PSC0 | GP_CORE_CTL | LPSC_SERDES_0 | 15 | OFF | YES | SERDES_10G0 |
| PSC0 | GP_CORE_CTL | LPSC_PCIE_0 | 16 | OFF | YES | PCIE0 |
| PSC0 | PD_A53_CLUSTER_0 | LPSC_A53_CLUSTER_0 | 20 | OFF | YES | A53SS0 |
| PSC0 | PD_A53_CLUSTER_0 | LPSC_A53_CLUSTER_0_PBIST | 21 | OFF | YES | COMPUTE_CLUSTER0_PBIST_0 |
| PSC0 | PD_A53_0 | LPSC_A53_0 | 22 | OFF | YES | RTI0 |
| PSC0 | PD_A53_0 | LPSC_A53_0 | 22 | OFF | YES | A53SS0_CORE_0 |
| PSC0 | PD_A53_1 | LPSC_A53_1 | 23 | OFF | YES | RTI1 |
| PSC0 | PD_A53_1 | LPSC_A53_1 | 23 | OFF | YES | A53SS0_CORE_1 |
| PSC0 | PD_PULSAR_0 | LPSC_PULSAR_0_R5_0 | 24 | OFF | YES | R5FSS0_CORE0 |
| PSC0 | PD_PULSAR_0 | LPSC_PULSAR_0_R5_0 | 24 | OFF | YES | RTI8 |
| PSC0 | PD_PULSAR_0 | LPSC_PULSAR_0_R5_1 | 25 | OFF | YES | R5FSS0_CORE1 |
| PSC0 | PD_PULSAR_0 | LPSC_PULSAR_0_R5_1 | 25 | OFF | YES | RTI9 |
| PSC0 | PD_PULSAR_0 | LPSC_PULSAR_PBIST_0 | 26 | OFF | YES | PBIST2 |
| PSC0 | PD_PULSAR_1 | LPSC_PULSAR_1_R5_0 | 27 | OFF | YES | R5FSS1_CORE0 |
| PSC0 | PD_PULSAR_1 | LPSC_PULSAR_1_R5_0 | 27 | OFF | YES | RTI10 |
| PSC0 | PD_PULSAR_1 | LPSC_PULSAR_1_R5_1 | 28 | OFF | YES | R5FSS1_CORE1 |
| PSC0 | PD_PULSAR_1 | LPSC_PULSAR_1_R5_1 | 28 | OFF | YES | RTI11 |
| PSC0 | PD_PULSAR_1 | LPSC_PULSAR_PBIST_1 | 29 | OFF | YES | PBIST3 |
| PSC0 | PD_ICSSG_0 | LPSC_ICSSG_0 | 30 | OFF | YES | PRU_ICSSG0 |
| PSC0 | PD_ICSSG_1 | LPSC_ICSSG_1 | 31 | OFF | YES | PRU_ICSSG1 |
| PSC0 | PD_CPSW | LPSC_CPSW3G | 33 | OFF | YES | CPSW0 |