SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The CTRL_MMR0 registers which provide control and status information for the EHRPWM/EQEP modules are shown in Table 5-11.
| Register Name | Description | Associated Functionality Described in: |
|---|---|---|
| MAIN_CTRL_MMR_CFG0_EPWM0_CTRL MAIN_CTRL_MMR_CFG0_EPWM1_CTRL MAIN_CTRL_MMR_CFG0_EPWM2_CTRL MAIN_CTRL_MMR_CFG0_EPWM3_CTRL MAIN_CTRL_MMR_CFG0_EPWM4_CTRL MAIN_CTRL_MMR_CFG0_EPWM5_CTRL MAIN_CTRL_MMR_CFG0_EPWM6_CTRL MAIN_CTRL_MMR_CFG0_EPWM7_CTRL MAIN_CTRL_MMR_CFG0_EPWM8_CTRL | Time base clock, source of PWM synchronization input and other controls for the EHRPWMx(1) module | EPWM(1) Modules Time Base Clock Gating and Daisy-Chain Connectivity between EPWM Modules in Enhanced Pulse Width Modulation (EPWM) Module |
| MAIN_CTRL_MMR_CFG0_SOCA_SEL | Start of Conversion output source | ADC start of conversion signals (PWM_SOCA and PWM_SOCB) in Enhanced Pulse Width Modulation (EPWM) Module |
| MAIN_CTRL_MMR_CFG0_SOCB_SEL | ||
| MAIN_CTRL_MMR_CFG0_EQEP_STAT | Provides EQEPx phase error status information | Device Specific EQEP Features in Enhanced Quadrature Encoder Pulse (EQEP) Module |