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多媒體與工業網路 SoC

AM3352

現行

Sitara 處理器：Arm Cortex-A8、1Gb 乙太網路、顯示器、CAN

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產品規格表
使用指南
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AM3352

現行
產品規格表 立即訂購

產品詳細資料

CPU 1 Arm Cortex-A8 Frequency (MHz) 300, 600, 800, 1000 Display type 1 LCD Protocols Ethernet Hardware accelerators Security Accelerator Features General purpose Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 125
CPU 1 Arm Cortex-A8 Frequency (MHz) 300, 600, 800, 1000 Display type 1 LCD Protocols Ethernet Hardware accelerators Security Accelerator Features General purpose Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 125
NFBGA (ZCE) 298 169 mm² 13 x 13 NFBGA (ZCZ) 324 225 mm² 15 x 15
  • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch
  • Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
    • NEON™ SIMD Coprocessor
    • 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
    • 256KB of L2 Cache With Error Correcting Code (ECC)
    • 176KB of On-Chip Boot ROM
    • 64KB of Dedicated RAM
    • Emulation and Debug - JTAG
    • Interrupt Controller (up to 128 Interrupt Requests)
  • On-Chip Memory (Shared L3 RAM)
    • 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
  • External Memory Interfaces (EMIF)
    • mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
      • mDDR: 200-MHz Clock (400-MHz Data Rate)
      • DDR2: 266-MHz Clock (532-MHz Data Rate)
      • DDR3: 400-MHz Clock (800-MHz Data Rate)
      • DDR3L: 400-MHz Clock (800-MHz Data Rate)
      • 16-Bit Data Bus
      • 1GB of Total Addressable Space
      • Supports One x16 or Two x8 Memory Device Configurations
    • General-Purpose Memory Controller (GPMC)
      • Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
      • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
      • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
    • Two Programmable Real-Time Units (PRUs)
      • 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
      • 8KB of Instruction RAM With Single-Error Detection (Parity)
      • 8KB of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
    • 12KB of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS:
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One Enhanced Capture (eCAP) Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
      • Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
    • Independent Power-on-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
    • Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
    • Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v1 Precision Time Protocol (PTP)
    • Up to Two Controller-Area Network (CAN) Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Two Master and Slave McSPI Serial Interfaces
      • Up to Two Chip Selects
      • Up to 48 MHz
    • Up to Three MMC, SD, SDIO Ports
      • 1-, 4- and 8-Bit MMC, SD, SDIO Modes
      • MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
      • Up to 48-MHz Data Transfer Rate
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3, SD, SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Four Banks of General-Purpose I/O (GPIO) Pins
      • 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
      • GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
    • Eight 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Watchdog Timer
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20 Million Polygons per Second
      • Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • LCD Controller
      • Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
      • Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
      • Integrated LCD Interface Display Driver (LIDD) Controller
      • Integrated Raster Controller
      • Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
      • 512-Word Deep Internal FIFO
      • Supported Display Types:
        • Character Displays - Uses LIDD Controller to Program these Displays
        • Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
        • Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
    • 12-Bit Successive Approximation Register (SAR) ADC
      • 200K Samples per Second
      • Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • Device Identification
    • Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
  • Inter-Processor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
      • Mailbox Registers that Generate Interrupts
        • Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
      • Spinlock has 128 Software-Assigned Lock Registers
  • Security
    • Crypto Hardware Accelerators (AES, SHA, RNG)
    • Secure Boot (optional; requires custom part engagement with TI)
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Packages:
    • 298-Pin S-PBGA-N298 Via Channel Package
      (ZCE Suffix), 0.65-mm Ball Pitch
    • 324-Pin S-PBGA-N324 Package
      (ZCZ Suffix), 0.80-mm Ball Pitch

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
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重要文件 類型 標題 格式選項 日期
* Data sheet AM335x Sitara™ Processors datasheet (Rev. L) PDF | HTML 2019年 11月 15日
* Errata AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I) 2017年 1月 3日
* User guide AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q) 2023年 2月 14日
Application note HSR/PRP Solutions on Sitara Processors for Grid Substation Communication (Rev. A) PDF | HTML 2026年 1月 30日
Application note Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 2025年 11月 24日
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 2025年 9月 5日
Application note AM335x Power Estimation Tool (Rev. A) PDF | HTML 2025年 6月 11日
Application note Basic Ethernet Interface Debug With Linux PDF | HTML 2024年 10月 11日
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 2023年 7月 31日
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 2023年 5月 24日
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022年 10月 11日
Design guide Discrete Power Solution for AM335x in 12mmx12mm Form-Factor Reference Design (Rev. A) PDF | HTML 2021年 11月 9日
Application note nfBGA Packaging (Rev. C) PDF | HTML 2021年 5月 17日
Application note Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A) 2021年 5月 7日
More literature From Start to Finish: A Product Development Roadmap for Sitara™ Processors 2020年 12月 16日
Technical article Selecting the right processor for your data concentrator design PDF | HTML 2020年 8月 3日
White paper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 2020年 7月 28日
User guide Powering the AM335x, AM437x, and AM438x with TPS65218D0 (Rev. B) 2020年 2月 27日
E-book E-book: An engineer’s guide to industrial robot designs 2020年 2月 12日
Application note AM335x Schematic Checklist (Rev. A) PDF | HTML 2019年 12月 19日
Application note AM335x EMIF Tools 2019年 9月 20日
Application note AM335x PMIC Selection Guide (Rev. A) 2019年 9月 19日
Application note Programmable Logic Controllers — Security Threats and Solutions PDF | HTML 2019年 9月 13日
Product overview Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A) 2019年 7月 30日
White paper Power optimization techniques for energy-efficient systems (Rev. A) 2019年 6月 28日
Application note Calculating Useful Lifetimes of Embedded Processors (Rev. B) PDF | HTML 2019年 5月 7日
Application note AM335x Hardware Design Guide PDF | HTML 2019年 5月 3日
Application note How to Port WOLFSSL Onto TI Sitara AM335 Starter Kit PDF | HTML 2019年 4月 24日
User guide Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 2019年 4月 11日
Application note Common EOS pitfalls in board design 2019年 2月 13日
Application note PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) 2019年 1月 18日
Application note McASP Design Guide - Tips, Tricks, and Practical Examples 2019年 1月 10日
Application note PRU Read Latencies (Rev. A) 2018年 12月 21日
Application note PRU-ICSS Getting Starting Guide on Linux (Rev. A) 2018年 12月 10日
Application note PRU-ICSS EtherCAT Slave Troubleshooting Guide 2018年 11月 7日
Application note PRU-ICSS / PRU_ICSSG Migration Guide 2018年 11月 5日
White paper Secure Boot on embedded Sitara™ processors (Rev. A) 2018年 10月 13日
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018年 9月 24日
Application note Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A) 2018年 3月 28日
User guide Powering the AM335x With the TPS650250 (Rev. B) 2018年 3月 14日
White paper Data concentrators: The core of energy and data management (Rev. A) 2018年 2月 21日
User guide PRU Assembly Instruction User Guide 2018年 2月 16日
White paper POWERLINK on TI Sitara Processors (Rev. A) 2018年 1月 10日
White paper Achieving increased functionality and efficiency in vacuum robots 2017年 12月 21日
Product overview TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E) 2017年 12月 19日
User guide TPS65910Ax User's Guide for AM335x Processors (Rev. F) 2017年 12月 8日
Technical article Introduction to EV charging displays PDF | HTML 2017年 11月 15日
User guide Sub-1 GHz Sensor-to-Cloud Linux® E14 Kit 2017年 10月 16日
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017年 8月 14日
Application note Processor-SDK RTOS Power Management and Measurement 2017年 8月 2日
White paper Cities grow smarter through innovative semiconductor technologies 2017年 7月 7日
Application note Sitara Linux ALSA DSP Microphone Array Voice Recognition 2017年 6月 30日
Application note AM335x Reliability Considerations in PLC Applications (Rev. A) 2017年 4月 27日
Application note AM335x Low Power Design Guide (Rev. A) 2017年 2月 28日
White paper Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) 2016年 8月 11日
White paper Building automation for enhanced energy and operational efficiency (Rev. A) 2015年 10月 26日
Application note Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015年 8月 13日
White paper Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B) 2015年 3月 3日
User guide G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide 2014年 11月 13日
User guide Powering the AM335x with the TPS65217x . (Rev. I) 2014年 9月 6日
White paper Mainline Linux™ ensures stability and innovation 2014年 3月 27日
White paper Linaro Speeds Development in TI Linux SDKs 2013年 8月 27日
White paper The Yocto Project:Changing the way embedded Linux software solutions are develop 2013年 3月 14日
White paper Smart thermostats are a cool addition to the connected home 2012年 9月 27日

設計與開發

電源供應解決方案

為 AM3352 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

檢視解決方案
開發板

TMDXEVM3358 — AM335x 評估模組

The AM335x Evaluation Module (EVM) enables developers to immediately start evaluating the AM335x processor family (AM3351, AM3352, AM3354, AM3356, AM3358) and begin building applications for factory automation, building automation, grid infrastructure, and more.

使用指南: PDF
TI.com 無法提供
開發板

TPS65217CEVM — TPS65217C 評估模組

The TPS65217CEVM is a fully assembled platform for evaluating the performance of the TPS65217C power management device.

使用指南: PDF
TI.com 無法提供
開發板

TPS65218EVM-100 — TPS65218 評估模組

The TPS65218EVM is a fully assembled platform for evaluating the performance of the TPS65218 power management device.

使用指南: PDF | HTML
TI.com 無法提供
開發板

ADVAN-3P-SITARA-SOMS — Advantech Sitara SOM 和 SBCS

Advantech offers Sitara™ based embedded core computing solutions including computer-on-modules, single-board-computers and box computers. Their compact, low-power-consumption, and cost-effective Arm®-based platform solutions are designed to deliver easier system integration, better (...)
從：Advantech
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開發板

BEAGL-BONE-GRN-ECO — Seeed Studio BeagleBone® Green eco 評估模組

Seeed Studio BeagleBone® Green Eco 是一款以 AM335x Arm® Cortex®-A8 處理器為基礎的低成本、工業級開放原始碼硬體開發平台。這種四層設計整合了高品質元件，可支援更廣泛的溫度範圍、增強的電源穩定性、增強的嵌入式多媒體卡 (eMMC) 儲存，以及專為工商業應用而設計的 GB 乙太網路。此電路板屬於 Seeed Studio BeagleBone Green 系列，與 BeagleBoard.org 合作開發。此電路板是以 BeagleBone Black 的電路圖設計和軟體為基礎。
從：Seeed Technology Co., Ltd.
使用指南: PDF | HTML
TI.com 無法提供
開發板

BYTES-3P-SITARASOMS — 工作位元組 Sitara SOM

bytes at work develops industrial computing products and services. They offer SOMs based on Sitara Arm® processors.

Learn more about bytes at work at http://www.bytesatwork.io/en. 


從：bytes at work AG
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開發板

COMPU-3P-SITARASOMS — Compulab Sitara SOM

CompuLab is a leading manufacturer of computer-on-module boards and miniature PC systems. CompuLab's products excel with an advanced set of features, outstanding level of integration, high reliability and affordable prices. Annual manufacturing rate of over 100,000 boards and systems positions (...)
從：CompuLab
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開發板

CRLNK-3P-SOMS — 適用於 TI ARM 架構處理器的 Critical Link MitySOM 系統模組

Critical Link is a US-based embedded systems company offering System on Modules (SoMs) and scientific imaging platforms for electronic applications around the world. The MitySOM® and MityDSP® families incorporate DSP, FPGA, and ARM technologies, and are designed for long product lifespan and (...)

從：Critical Link LLC
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開發板

FORLX-3P-SITARA-SOMS — Forlinx Sitara SOM

As a member unit of CSIA (China Software Industry Association) Embedded System Branch, Forlinx Embedded Tech Co., Ltd. has the capability to design, prototype and manufacture printed circuit boards, sub-assemblies and complete electronic products. Forlinx is committed to the development of Sitara (...)
從：Forlinx Embedded Tech. Co., Ltd
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開發板

MYIR-3P-SITARASOMS — MYIR Sitara SOM

MYIR offers a series of development kits and system-on-modules based on TI's AM335x Arm® Cortex®-A8 processors to meet customers' different requirements. MYIR also offers a compact single board computer Rico board based on TI's newest AM437x Arm Cortex-A9 solution. MYIR also offers custom (...)
從：MYIR Tech Limited
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開發板

OCTVO-3P-AM335X — Octavo Systems AM335x 型系統級封裝

Octavo Systems 是為全球創新者提供系統級封裝 (SIP) 架構解決方案的領導者。OSD335x 系列 SiP 裝置是基於德州儀器的 Sitara™ AM335x Arm® Cortex®-A8 處理器開發和部署高效能嵌入式系統的最快速且最具成本效益的方法。

OSD335x 裝置整合執行速度高達 1GHz 的 Sitara™ AM335x Arm® Cortex®-A8 處理器，以及高達 1GB 的 DDR3、TPS65217C 電源管理 IC、TL5209 LDO、EEPROM（選用）、eMMC（選用）、MEMS 振盪器（選用）和被動元件，成為一個易於使用的 BGA 封裝。

(...)

從：Octavo Systems
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開發板

PHYTC-3P-PHYBOARD-AM335X — 適用 AM335x Arm® 架構 Sitara™ 處理器的 PHYTEC® phyBOARD®-AM335x 開發套件

phyBOARD®-AM335x 配備 TI Sitara™ AM335x 為基礎的 phyCORE-AM335x 系統模組 (SOM)，直接焊接在載板 PCB 上。SOM 與載板間的「直接焊接連接 (DSC)」可省略板與板連接器來降低系統成本。phyBOARD 採用 Pico-ITX 尺寸，非常適合部署在各種強大的工業應用中。

PHYTEC 是能讓客戶快速且輕易的將複雜產品導入市場的領先業界系統模組 (SOM)、嵌入式中介軟體和設計服務提供者及整合商。我們利用博深的領域專業、高品質產品、供應鏈專業及敏捷的共同作業實務，從設計到生產逐步引導客戶。PHYTEC (...)

從：PHYTEC
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開發板

PHYTC-3P-PHYCORE-AM335X — 模組上的 PHYTEC phyCORE-AM335x 系統

phyCORE®-AM335x SOM 支援德州儀器 Sitara™ AM335x 系列處理器，該系列配備高處理性能、低功耗和高度整合的週邊設備組，並擁有先進的圖形處理能力和即時通訊協定支援。220 接腳 SOM 互連允許輕鬆存取雙 USB OTG、雙 Gigabit 乙太網路、CAN 和 LCD 等介面。

PHYTEC 是能讓客戶快速且輕易的將複雜產品導入市場的領先業界系統模組 (SOM)、嵌入式中介軟體和設計服務提供者及整合商。我們利用博深的領域專業、高品質產品、供應鏈專業及敏捷的共同作業實務，從設計到生產逐步引導客戶。PHYTEC (...)

從：PHYTEC
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開發板

TQ-3P-SITARASOMS — 適用於 TI Arm 架構處理器和微控制器的 TQ Group 系統模組

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
從：TQ-Group
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開發板

VANWS-3P-VGATEWAY — 來自基於 AM335x 的 Vanteon 無線解決方案的 vGATEWAY 參考設計

Vanteon Gateway™ is a modular bridging platform designed to translate between common wireless interfaces and protocols for Internet of Things (IoT) applications. The Gateway™ platform utilizes the AM335x Sitara ARM-Cortex A8 processor and includes many standard wired and wireless communication (...)

從：Vanteon Wireless Solutions
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開發板

VAR-3P-SITARASOMS — Variscite Sitara SOM

Variscite designs and produces a variety of system on modules and single board computers based TI's Sitara™, OMAP™ and DaVinci™ processors, covering a wide range of products, segments and markets. Variscite provides its customers with a complete development kit supporting Windows (...)
從：Variscite
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子卡

WL1835MODCOM8B — WiLink™ 8 模組 2.4 GHz WiFi® + Bluetooth® COM8 評估模組

TI WiLink™ 8 module family

The WL1835MODCOM8 is one of the two evaluation boards for the TI WiLink 8 combo module family. For designs requiring performance in the 5 GHz band and extended temperature range, see the WL1837MODCOM8I.

The WL1835MODCOM8 Kit for Sitara EVMs easily enables customers to add (...)

使用指南: PDF | HTML
TI.com 無法提供
子卡

WL1837MODCOM8I — WiLink™ 8 雙頻 2.4 和 5 GHz Wi-Fi® + 藍牙® COM8 評估模組

TI WiLink™ 8 module family The WL1837MODCOM8I is one of the two evaluation boards for the TI WiLink™ 8 combo module family. For designs requiring performance in the 2.4 GHz band only, see the WL1835MODCOM8.

The WL1837MODCOM8I, which is compatible with many processors including TI’s (...)

使用指南: PDF | HTML
TI.com 無法提供
偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器（模擬器）。對於大多數裝置，建議使用較新、成本較低的 XDS110 (www.ti.com/tool/TMDSEMU110-U)。XDS200 支援單一 Pod 中廣泛的標準（IEEE1149.1、IEEE1149.7、SWD）。所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。

XDS200 透過 TI 20 接腳連接器（配備適用 TI 14 接腳、Arm Cortex® 10 接腳和 Arm 20 接腳的多重轉接器）連接到目標電路板，並透過 USB2.0 高速 (...)

TI.com 無法提供
偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

TI.com 無法提供
偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

TI.com 無法提供
偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

從：Lauterbach GmbH
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AM335X — Linux Processor SDK for AM335x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-AM335X — Linux-RT Processor SDK for AM335x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-AM335X — TI-RTOS Processor SDK for AM335x and AMIC110 devices (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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軟體開發套件 (SDK)

TIBLUETOOTHSTACK-SDK — TI 雙模式 Bluetooth® 堆疊

TI 的雙模式 Bluetooth 堆疊支援 Bluetooth + Bluetooth 低功耗，並包含實作 Bluetooth 4.0/4.1/4.2 規格的單模式與雙模式產品。Bluetooth 堆疊已完全通過 Bluetooth 技術聯盟 (SIG) 認證並免權利金，提供簡易的命令行範例應用程式以加速開發，並且根據需求提供 MFI 功能。

堆疊可與以下裝置配合使用：

使用指南: PDF
使用指南: PDF | HTML
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驅動程式或資料庫

WIND-3P-VXWORKS-LINUX-OS — Wind River 處理器 VxWorks 和 Linux 作業系統

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
從：Wind River Systems
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驅動程式或資料庫

WIT-3P-SITARABSP — Witekio Sitara Android 和 Windows 作業系統

Witekio brings expertise on low (OS, driver, firmware) and high level software (application, connectivity, cloud) for TI's OMAP and Sitara AM335x, AM437x, and AM57x platforms. Witekio offers BSPs, drivers, application development/UI/custom drivers for Android, Linux and Windows embedded systems as (...)
從：Witekio
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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作業系統 (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
從：Green Hills Software
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作業系統 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
從：Mentor Graphics Corporation
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作業系統 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® 即時作業系統 (RTOS) 是一款功能完整且穩固的 RTOS，專為實現適用於汽車、醫療、運輸、軍事和工業嵌入式系統的新一代產品而設計。微核心設計與模組化架構，能讓客戶以低整體擁有成本打造高度最佳化且可靠的系統。
從：QNX Software Systems
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軟體程式設計工具

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)

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軟體程式設計工具

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash is a software tool for programming on-chip flash on TI microcontrollers and wireless connectivity devices and on-board flash for TI processors. UniFlash provides both graphical and command-line interfaces.

UniFlash can be run from the cloud on the TI Developer Zone or downloaded and used (...)

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模擬型號

AM335x Thermal Model

SPRM824.ZIP (10 KB) - Thermal Model
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模擬型號

AM335x ZCE IBIS Model (Rev. B)

SPRM556B.ZIP (21124 KB) - IBIS Model
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模擬型號

AM335x ZCE Rev. 2.0 BSDL Model (Rev. A)

SPRM548A.ZIP (8 KB) - BSDL Model
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模擬型號

AM335x ZCE Rev. 2.1 BSDL Model

SPRM606.ZIP (8 KB) - BSDL Model
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模擬型號

AM335x ZCZ IBIS Model (Rev. C)

SPRM552C.ZIP (21721 KB) - IBIS Model
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模擬型號

AM335x ZCZ Rev. 2.0 BSDL Model (Rev. A)

SPRM549A.ZIP (8 KB) - BSDL Model
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模擬型號

AM335x ZCZ Rev. 2.1 BSDL Model

SPRM607.ZIP (8 KB) - BSDL Model
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計算工具

AM335-PET-CALC — AM335x Power Estimation Tool

Power Estimation Tool (PET) provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be (...)

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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
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計算工具

POWEREST — 功率估計工具 (PET)

功耗估算工具 (PET) 讓使用者能深入瞭解特定 TI 處理器的功耗情況。本工具允許使用者選擇多種應用場景，不僅能掌握功耗數據，更能理解如何運用進階節能技術進一步降低整體功耗。
AM57x 與 AM437x 處理器專用 PET：

此可下載試算表提供使用者輸入應用所需裝置參數的機制。參數包含 IP 模組活動狀態/負載量、目標電源模式及電源管理使用情境。可設定多重運作條件並為每種狀態配置時間區段。電源估算數據已內嵌於試算表中，所有結果將直接在試算表內自動生成（無需上傳任何資料）。

AM57x 專用 PET：

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計算工具

SITARA-DDR-CONFIG-TOOL — Sitara 外部記憶體介面 (EMIF) 工具

Sitara™ EMIF 工具是一款軟體工具，提供配置 TI 處理器以存取外部 DDR 記憶體裝置的介面。該工具還最佳化延遲鎖定迴路 (DLL) 設定，以補償電路板佈線偏斜。結果輸出為 EMIF 配置暫存器，可導入以在處理器 SDK、Code Composer Studio 或自訂軟體中使用。  
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計算工具

SITARA-DDR-CONFIG-TOOL-AM65X-DRA80XM — AM65x/DRA80xM EMIF Tool Spreadsheet

The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)

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參考設計

TIDEP-0087 — 適用於電動車充電基礎設施的人機介面 (HMI) 參考設計

此處理器架構參考設計有助於加快上市時間，並協助客戶設計符合成本效益的電動車 (EV) 充電基礎設施或 EVSE 人機介面 (HMI) 解決方案。此參考設計展現二維 (2D) Qt 圖形使用者介面 (GUI)（通常用於 EVSE HMI），以及 TI 處理器的軟體轉譯圖形功能。AM335x 處理器提供可擴展性，具備多種處理速度、相容軟體以滿足從低階到高階應用的需求，並具備豐富的連接能力，可連接 EVSE HMI 所需的主要周邊設備，例如通用非同步接收器 / 發射器 (UART) 和 CAN。
Design guide: PDF
電路圖: PDF
參考設計

TIDEP-01013 — 具有 mmWave 感測器和 Sitara™ 處理器的手勢控制 HMI 參考設計

此參考設計透過 Processor SDK Linux 在 Sitara AM335x 處理器上運行，並結合 mmWave SDK 在 IWR6843ISK 上執行，以實現自然手勢識別與存在感測功能。

該設計展示手勢控制 HMI（人機介面）的功能，其中 mmWave 感測器負責偵測存在並分類自然手勢，然後傳送至 Sitara AM335x 處理器，該處理器再利用這些資訊來驅動在 Linux 環境下運行的 GUI 應用程式。此設計整合了強化型處理器 SOC和感測器，並建立嵌入式手勢控制 HMI。

Design guide: PDF
電路圖: PDF
參考設計

TIDEP-01005 — 適用於智慧空調的人機介面 (HMI) 參考設計

此處理器架構參考設計有助於加快上市時間，並協助客戶為智慧調溫器設計符合成本效益的人機介面 (HMI) 解決方案。Sitara ™ AM335x 系列處理器提供可擴充的替代方案，具備 300MHz 至 1GHz 的處理速度，圖形加速，可滿足低階至高階應用的軟體，以及與智慧恆溫器所需主要周邊設備的充足連線能力，例如通用非同步接收器 / 發射器 (UART)，SDIO，USB 等。

此智慧恆溫器 HMI 參考設計展現二維 (2-D) Qt 圖形使用者介面 (GUI)，以及 TI 處理器的硬體加速轉譯圖形功能。

Design guide: PDF
電路圖: PDF
參考設計

TIDEP-0102 — 適用於保護繼電器的人機介面 (HMI) 參考設計

此處理器架構參考設計有助於加快上市時間，並協助客戶為保護繼電器設計符合成本效益的人機介面 (HMI) 解決方案。此參考設計展現二維 (2D) Qt 圖形使用者介面 (GUI)（通常用於保護繼電器 HMI），以及 TI 處理器的軟體轉譯圖形功能。AM335x 處理器提供可擴展性，因為提供了一系列處理速度，並使用相同的軟體開發環境來滿足低階到高階應用需求，還提供充分的連接能力，以連接保護繼電器 HMI 所需的主要週邊設備，例如通用非同步接收器/發射器 (UART) 和 CAN。
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0044 — 太陽能逆變器閘極開發平台參考設計

Solar Inverter Gateways add communication functions to solar energy generation systems to enable system monitoring, real-time feedback, system updates, and more. The TIDEP0044 reference design describes the implementation of a solar inverter gateway using display, Ethernet, USB, and CAN on the (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0019 — BeagleBone Cape 與入門套件的變電所機架控制器 IEC 61850 示範

成本低廉的 IEC 61850 變電所機架控制器簡化實作，可在採用 Linux 目標層定義的 TI AM335X 平台上有效執行 Triangle MicroWorks IEC 61850 堆疊。您可在 AM335X 平台及 61850 堆疊展示上，建置許多不同的變電所自動化應用。
Design guide: PDF
電路圖: PDF
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NFBGA (ZCZ) 324 Ultra Librarian
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