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微控制器 (MCU) 與處理器
微處理器和 DSP
汽車駕駛輔助 SoC

TDA4VEN-Q1

現行

適用於視覺感知和分析、具有四 Arm® Cortex®-A53、4 TOPS AI、C7xDSP 和 GPU 的 SoC

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TDA4VEN-Q1

現行
產品規格表 立即訂購

產品詳細資料

CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, Yes
CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Graphics acceleration 1 3D Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, Yes
FCBGA (AMW) 594 324 mm² 18 x 18

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600 MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit (TDA4VEN)
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 400MPixels/s operation
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000 MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted for Automotive (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 planned
  • AEC - Q100 qualified

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65-mm pitch with VCA, 594-pin FCBGA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 32KB L1 DCache with SECDED ECC and 64KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600 MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit (TDA4VEN)
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 400MPixels/s operation
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000 MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted for Automotive (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 planned
  • AEC - Q100 qualified

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65-mm pitch with VCA, 594-pin FCBGA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

The TDA4VEN/TDA4AEN (aka, TDA4-Entry) processor family is an extension of the Jacinto™ 7 automotive-grade family of heterogeneous Arm® processors targeted at Advanced Driver Assistance System (ADAS) applications. With embedded Deep Learning (DL), Video, Vision Processing, and 3D Graphics acceleration, display interface and extensive automotive peripheral and networking options, TDA4VEN/TDA4AEN is built for a set of cost and power sensitive automotive applications such as NCAP front camera or entry-level park assistance systems. The cost optimized TDA4VEN/TDA4AEN provides an optimized performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

TDA4VEN/TDA4AEN contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include TI’s Dense Optical Flow (DOF) accelerator as well two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

TDA4VEN/TDA4AEN integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in TDA4VEN/TDA4AEN to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. TDA4VEN/TDA4AEN supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications. Integrated diagnostics and safety features support operations up to ASIL-B at SoC level, (ASIL-D systematic level).

The TDA4VEN/TDA4AEN (aka, TDA4-Entry) processor family is an extension of the Jacinto™ 7 automotive-grade family of heterogeneous Arm® processors targeted at Advanced Driver Assistance System (ADAS) applications. With embedded Deep Learning (DL), Video, Vision Processing, and 3D Graphics acceleration, display interface and extensive automotive peripheral and networking options, TDA4VEN/TDA4AEN is built for a set of cost and power sensitive automotive applications such as NCAP front camera or entry-level park assistance systems. The cost optimized TDA4VEN/TDA4AEN provides an optimized performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

TDA4VEN/TDA4AEN contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include TI’s Dense Optical Flow (DOF) accelerator as well two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

TDA4VEN/TDA4AEN integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in TDA4VEN/TDA4AEN to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. TDA4VEN/TDA4AEN supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications. Integrated diagnostics and safety features support operations up to ASIL-B at SoC level, (ASIL-D systematic level).
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet TDA4VEN, TDA4AEN Jacinto™ Processors datasheet (Rev. A) PDF | HTML 2024年 9月 30日
* Errata J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Errata (Rev. A) PDF | HTML 2025年 4月 15日
* User guide J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. C) PDF | HTML 2025年 11月 25日
Application note Memory allocation for TIDL usage PDF | HTML 2025年 11月 10日
Functional safety information J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 2025年 10月 1日
Functional safety information J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 2025年 9月 25日
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 2025年 6月 17日
Application note MCAN Debug Guide PDF | HTML 2025年 2月 18日
Application note Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 2025年 1月 28日
Application brief Custom DDR Memory Mapping for Vision Applications on Jacinto SoCs PDF | HTML 2024年 12月 16日
User guide J722S/TDA4VEN/TDA4AEN/AM67 Power Estimation Tool User’s Guide (Rev. A) 2024年 10月 3日
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 2024年 8月 5日
Application note Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 2024年 6月 20日
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 2024年 6月 4日
Product overview J722S/AM67x/TDA4VEN/TDA4AEN Processor Automotive Power Designs using TPS6522312-Q1 PMIC PDF | HTML 2024年 4月 18日
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 2024年 4月 4日
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 2023年 11月 16日
White paper 以高度整合處理器設計高效邊緣 AI 系統 (Rev. A) PDF | HTML 2023年 4月 19日
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 2023年 1月 9日
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 2022年 8月 15日
Application note Dual-TDA4x System Solution PDF | HTML 2022年 4月 29日
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 2022年 4月 5日
Technical article How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 2022年 3月 29日
Technical article How to simplify your embedded edge AI application development PDF | HTML 2022年 1月 28日
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 2022年 1月 10日
Application note TDA4 Flashing Techniques PDF | HTML 2021年 7月 8日
White paper Security Enablers on Jacinto™ 7 Processors 2021年 1月 4日
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 2020年 10月 22日
Application note OSPI Tuning Procedure PDF | HTML 2020年 7月 8日

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開發板

J722SXH01EVM — TDA4VEN、TDA4AEN 與 AM67 評估模組

J722SXH01EVM 入門套件評估模組是以我們的 J722S、TDA4VEN、TDA4AEN 以及 AM67 視覺與顯示處理器為建置基礎，其中包括可擴充的 Arm® Cortex®-A53 效能、支援最高 600MP/s 的影像訊號處理器、最高每秒 4 兆次操作的 AI 加速器，以及如三重高解析度顯示支援、高效能 3D-GPU、4K 視訊加速及其它廣泛的周邊設備等嵌入式功能。J722SXH01EVM 適用於欲開發汽車或工業應用的客戶，包括汽車前置攝影機系統、汽車環景顯示與停車輔助系統、工業 HMI、機器人教導器等。

J722SXH01EVM 包含可支援最多 3 個螢幕的多個顯示連接器、最多 (...)

使用指南: PDF | HTML
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開發板

ALTOS-3P-V2 — 以 TDA4 處理器為基礎的 Altos 四晶片串級成像雷達

Altos Radar 是全球領導級的汽車應用成像雷達開發商。 

 

Altos V2 是以 TI AWR2243 MMIC 和 TDA4 處理器為基礎的四晶片串級成像雷達設計。其採用自訂 12TX 和 16TX 天線陣列設計，具備完整的訊號處理管線、在 TI TDA4 處理器上的嵌入式實作，以及適用於先進駕駛輔助系統 (ADAS) 的世界級點雲輸出。

 

Altos V2 是體驗四晶片串級成像雷達真正功能的絕佳起點。此外，Altos Radar 還可根據要求提供完整的工具鏈，以收集原始資料、進行點雲離線模擬和顯示、調整參數、建立物件清單等。Altos (...)

從：Altos Radar Inc.
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偵錯探測器

TMDSEMU110-U — XDS110 JTAG 偵錯探測器

德州儀器 XDS110 是一種全新的偵錯探測器 (模擬器) 類別，適用於 TI 嵌入式處理器。XDS110 取代 XDS100 系列，可在單一 Pod 中支援更廣泛的標準 (IEEE1149.1、IEEE1149.7、SWD)。同時，所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。  對於針腳上的核心追蹤，則需要 XDS560v2 PRO TRACE。

德州儀器 XDS110 透過 TI 20 針腳連接器（具有用於 TI 14 針腳和 Arm 10 針腳和 Arm 20 針腳的多轉接器）連接到目標電路板，並透過 USB2.0 (...)

使用指南: PDF
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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件，可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案，適用於從早期的矽前 (pre-silicon) 開發，到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能，以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器，開發人員也可透過單一偵錯介面，同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

從：Lauterbach GmbH
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偵錯探測器

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

從：TASKING Germany GmbH
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-J722S — Processor SDK Linux for J722S

The J722S processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VEN-Q1 and TDA4AEN-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)
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軟體開發套件 (SDK)

PROCESSOR-SDK-QNX-J722S — Processor SDK QNX for J722S

The J722S processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VEN-Q1 and TDA4AEN-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)
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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-J722S — Processor SDK RTOS for J722S

The J722S processor software development kit (SDK) real-time operating system (RTOS) can be used together with either processor SDK Linux® or processor SDK QNX® to form a multiprocessor software development platform for TDA4VEN-Q1 and TDA4AEN-Q1 system-on-a-chip (SoCs) within our Jacinto™ platform.

(...)
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韌體

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM 韌體

SecIC-HSM 旨在滿足 MCU/SoC 晶片所需的網路安全要求。HSM 韌體可應用於汽車、新能源、光伏、機器人、醫療保健與航空等領域。提供的網路安全功能包括安全開機、安全通訊 (SecOC)、安全診斷、安全儲存、安全更新、安全偵錯和金鑰管理。SecIC-HSM 的優點：一站式網路安全解決方案，具備跨晶片系列的全方位軟體相容性，擁有業界領先的性能，已在近 30 家 OEM 的量產車型中成功部署，累計出貨超過 300 萬套。
從：Shanghai Uni-Sentry Intelligent Technology Co., LTD
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韌體

USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC 演算法韌體

Uni-Sentry 的安全解決方案採用 PQC 演算法，能夠抵抗量子電腦對傳統加密演算法所造成的解密威脅。PQC 韌體與硬體安全模組 (HSM) 進行協同優化，利用硬體加速與安全性強化，以提升加密演算法的執行效率與安全性。 


Uni-Sentry 持續監控全球量子運算的發展，並更新其演算法組合。當前的 PQC 產品功能包括：

  • SP 800-208：LMS 和 XMSS
  • FIPS 203 (ML-KEM)：CRYSTALS-KYBER
  • FIPS 204 (ML-DSA)：CRYSTALS-Dilithium
  • FIPS 205 (SLH-DSA)： SPHINCS+ 

技術亮點 

  • 量子抗性認證：與 (...)
從：Shanghai Uni-Sentry Intelligent Technology Co., LTD
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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IDE、配置、編譯器或偵錯程式

DDR-CONFIG-J722S — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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作業系統 (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
從：Green Hills Software
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作業系統 (OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
從：Green Hills Software
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作業系統 (OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS 預先認證的安全 RTOS

SAFERTOS® 是專為嵌入式處理器設計的獨特即時作業系統。經 TÜV SÜD 預先認證，符合 IEC 61508 SIL3 與 ISO 26262 ASILD 標準。SAFERTOS® 是由 WHIS 專家團隊專為安全而打造，適用於全球重要安全應用。WHIS 與德州儀器的合作已經超過十年。在此期間，WHIS 已將 SAFERTOS® 移植至各種 TI 處理器，支援所有熱門核心，並可依要求提供其他架構。SAFERTOS® 專為您的特定處理器/編譯器組合量身打造，隨附完整的原始程式碼與設計保證包，可完全一目了然整個設計生命週期。許多 WHIS 客戶開始使用 FreeRTOS (...)
從：WITTENSTEIN High Integrity Systems
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模擬型號

J722S BSDL Model

SPRM854.ZIP (12 KB) - BSDL Model
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模擬型號

J722S IBIS Model

SPRM855.ZIP (4140 KB) - IBIS Model
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模擬型號

J722S Thermal Model

SPRM856.ZIP (0 KB) - Thermal Model
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Gerber 檔案

J722S/AM67x/TDA4VEN/TDA4AEN Evaluation Module Design Files (Rev. C)

SPRR495C.ZIP (556217 KB)
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (AMW) 594 Ultra Librarian
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  • 鉛塗層/球物料
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  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
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