AM2612

現行

基於 Arm® Cortex®-R5F 的 500MHz 雙核心 MCU,具備即時控制、安全與保全功能

產品詳細資料

CPU Arm Cortex-R5F Frequency (MHz) 500 ADC type 3 12-bit SAR Total processing (MIPS) 0.001 Features Automation, CAN, CAN FD, EnDat 2.2, EtherCAT, EtherNet/IP, Ethernet, External memory interface, FSI, Hardware encrpytion (AES/DES/SHA/MD5), I2C, IO-Link, Integrated industrial protocols, OSPI, Profinet, Robotics, SD/SDIO, SPI, UART UART 6 CAN (#) 2 (CAN-FD) PWM (Ch) 20 TI functional safety category Functional Safety-Compliant Number of ADC channels 21 SPI 2, 4 USB USB 2.0 Operating temperature range (°C) -40 to 125 Rating Catalog Communication interface CAN, CAN-FD, FSI, I2C, OSPI, SD/SDIO, SPI, UART Operating system BareMetal (No OS), FreeRTOS, ThreadX, Zephyr RTOS Hardware accelerators Trigonometric math accelerator Edge AI enabled Yes Number of GPIOs 140 Security Cryptographic acceleration, Device lifecycle management, Secure boot, Secure debug, Secure provisioning
CPU Arm Cortex-R5F Frequency (MHz) 500 ADC type 3 12-bit SAR Total processing (MIPS) 0.001 Features Automation, CAN, CAN FD, EnDat 2.2, EtherCAT, EtherNet/IP, Ethernet, External memory interface, FSI, Hardware encrpytion (AES/DES/SHA/MD5), I2C, IO-Link, Integrated industrial protocols, OSPI, Profinet, Robotics, SD/SDIO, SPI, UART UART 6 CAN (#) 2 (CAN-FD) PWM (Ch) 20 TI functional safety category Functional Safety-Compliant Number of ADC channels 21 SPI 2, 4 USB USB 2.0 Operating temperature range (°C) -40 to 125 Rating Catalog Communication interface CAN, CAN-FD, FSI, I2C, OSPI, SD/SDIO, SPI, UART Operating system BareMetal (No OS), FreeRTOS, ThreadX, Zephyr RTOS Hardware accelerators Trigonometric math accelerator Edge AI enabled Yes Number of GPIOs 140 Security Cryptographic acceleration, Device lifecycle management, Secure boot, Secure debug, Secure provisioning
NFBGA (ZCZ) 324 225 mm² 15 x 15 NFBGA (ZFG) 304 175.5625 mm² 13.25 x 13.25

Processor Cores:

  • Single and Dual Arm Cortex R5F CPU with each core running up to 500MHz
    • 16KB I-Cache with 64-bit ECC per CPU core
    • 16KB D-cache with 32-bit ECC per CPU core
    • 256KB Tightly Coupled Memory (TCM) with 32-bit ECC per core
    • Lockstep or Dual-core operation supported
  • Trigonometric Math Unit (TMU) for accelerating trigonometric functions
    • Up to 2x, one per R5F MCU core

Memory:

  • 1.5MB of On-Chip Shared RAM (OCSRAM):
    • 3 banks × 512KB
    • ECC error protection for full 1.5MB OCSRAM
    • Remote L2 Cache (RL2) for external memory, software programmable up to 256KB per CPU core

  • 2x Octal Serial Peripheral Interface (OSPI) up to 133MHz SDR and DDR
    • 1x with eXecute In Place (XIP) support
    • RAM expansion/Flash over the Air (FOTA)

  • General-Purpose Memory Controller (GPMC)
    • 16-bit parallel data bus with 22-bit address bus and 4 chip selects
    • Up to 4MB addressable memory space
    • Integrated Error Location Module (ELM) support for error checking

System on Chip (SoC) Services and Architecture:

  • 1x EDMA to support data movement functions
  • Device Boot supported from the following interfaces:
    • UART (Primary/Backup)
    • OSPI NOR and NAND Flash (50MHz SDR and 25MHz DDR) (Primary)

    • USB Peripheral boot
  • Interprocessor communication modules
    • SPINLOCK module for synchronizing processes running on multiple cores
    • MAILBOX functionality implemented through CTRLMMR registers
  • Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers
  • Timer Modules:
    • 2x Windowed Watchdog Timer (WWDT)
    • 4x Real Time Interrupt (RTI) timer

USB 2.0

  • Port configurable as USB host, USB device, or USB Dual-Role device
  • USB 2.0 Host mode
    • High-Speed (HS, 480Mbps)
    • Full-Speed (FS, 12Mbps)
    • Low-Speed (LS, 1.5Mbps)
  • USB 2.0 Device mode
    • High-Speed (HS, 480Mbps)
    • Full-Speed (FS, 12Mbps)

Industrial Connectivity:

  • 2x Programmable Real-time Unit – Industrial Communication Subsystem (PRU-ICSS)
    • Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1) per PRU-ICSS for 4 cores total
      • Deterministic hardware
      • Dynamic firmware
    • 20-channel enhanced input (eGPI) per PRU
    • 20-channel enhanced output (eGPO) per PRU
    • Embedded Peripherals and Memory
      • 1x UART, 1x ECAP, 1x MDIO, 1x IEP
      • 1x 32KB Shared General Purpose RAM
      • 2x 8KB Shared Data RAM
      • 1x 12KB IRAM per PRU
      • ScratchPad (SPAD), MAC/CRC
    • Digital encoder and sigma-delta control loops
    • The PRU-ICSS enables advanced industrial protocols including:
      • EtherCAT, Ethernet/IP™
      • PROFINET, IO-Link
    • Dedicated Interrupt Controller (INTC)
    • Dynamic CONTROLSS XBAR Integration

High Speed Interfaces

  • Integrated 3-port Gigabit Ethernet Switch (CPSW) supporting up to two external ports
    • Selectable MII (10/100), RMII (10/100), or RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • 512x ALE engine based packet classifiers
    • Priority flow control with up to 2KB packet size
    • Four CPU hardware interrupt pacing
    • IP/ UDP/ TCP checksum offload in hardware
    • Time Sensitive Network (TSN) Support
    • Cut-thru switching and Interexpress Traffic (IET) support

General Connectivity:

  • 6x Universal Asynchronous RX-TX (UART)
  • 4x Serial Peripheral Interface (SPI) controllers
  • 3x Local Interconnect Network (LIN) ports
  • 3x Inter-Integrated Circuit (I2C) ports
  • 2x Modular Controller Area Network (MCAN) modules with CAN-FD support
  • 1x Fast Serial Interface Transmitter (FSITX)
  • 1x Fast Serial Interface Receiver (FSIRX)
  • Up to 141x General Purpose I/O (GPIO) pins

Sensing and Actuation:

  • Real-time Control Subsystem (CONTROLSS)
  • Flexible Input/Output Crossbars (XBAR)
  • 3x 12-bit Analog to Digital Converters (ADC) with 3 MSPS maximum sampling rate
    • Each ADC module with
      • 7x Single ended channels OR
      • 3x Differential channels
    • Highly configurable ADC digital logic
      • With selectable internal or external reference
      • 4x Post-Processing blocks for each ADC module
  • 9x Analog Comparators with internal 12-bit DAC reference (CMPSSA)
  • 1x 12 bit Digital to Analog Converter (DAC)
  • 10x Enhanced High Resolution Pulse Width Modulation (eHRPWM) modules
    • Single or Dual PWM channels
    • Advanced PWM Configurations
    • Enhanced HRPWM time resolution
  • 8x Enhanced Capture (ECAP) modules
  • 2x Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2x Sigma-Delta Filter Modules (SDFM)

Data Storage

  • 1 × 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface

Security:

  • Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
  • Targeted for ISO 21434 compliance
  • Secure boot support
    • Device Take Over Protection
    • Hardware enforced root-of-trust
    • Authenticated boot
    • SW Anti-rollback protection
  • Debug security
    • Secure device debug only after proper authentication
    • Ability to disable device debug functionality
  • Device ID and Key Management
    • Support for OTP Memory (FUSEROM)
      • Store root keys and other security fields
    • Separate EFUSE controllers and FUSE ROMs
    • Unique Device Public Identifiers
  • Memory Protection Units (MPU)
    • Dedicated Arm MPU per Cortex-R5F core
    • System MPU - present at various interfaces in the SoC (MPU or Firewall)
    • 8 to 16 Programmable Regions
      • Enable/Privilege ID
      • Start/End Address
      • Read/Write/Cachable
      • Secure/Non-Secure
  • Cryptographic acceleration
    • Cryptographic cores with DMA Support
    • AES - 128/192/256-bit key sizes
    • SHA2 - 256/384/512-bit support
    • DRBG with pseudo and true random number generator

Functional Safety:

  • Enables design of systems with functional safety requirements
    • Error Signaling Module (ESM)
    • ECC or parity on calculation critical memories
    • Built-In Self-Test (BIST) on-chip RAM
    • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation to be made available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL-3
    • Hardware integrity up to SIL-3
    • Safety-related certification
      • IEC 61508 certified
  • Functional Safety-Compliant [Automotive]
    • Developed for functional safety applications
    • Documentation to be made available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL-D
    • Hardware integrity up to ASIL-D
    • Safety-related certification
      • ISO 26262 certified

Technology / Package:

  • AEC-Q100 qualified for automotive applications
  • ZCZ Package
    • 324-pin NFBGAs
    • 15.00mm × 15.00mm
    • 0.8mm pitch
  • ZFG Package
    • 304-pin NFBGA
    • 13.25mm × 13.25mm
    • 0.65mm pitch
  • ZEJ Package
    • 256-pin NFBGA
    • 13.00mm × 13.00mm
    • 0.8mm pitch
  • ZNC Package
    • 293-pin NFBGA
    • 10.00mm × 10.00mm
    • 0.5mm pitch

Processor Cores:

  • Single and Dual Arm Cortex R5F CPU with each core running up to 500MHz
    • 16KB I-Cache with 64-bit ECC per CPU core
    • 16KB D-cache with 32-bit ECC per CPU core
    • 256KB Tightly Coupled Memory (TCM) with 32-bit ECC per core
    • Lockstep or Dual-core operation supported
  • Trigonometric Math Unit (TMU) for accelerating trigonometric functions
    • Up to 2x, one per R5F MCU core

Memory:

  • 1.5MB of On-Chip Shared RAM (OCSRAM):
    • 3 banks × 512KB
    • ECC error protection for full 1.5MB OCSRAM
    • Remote L2 Cache (RL2) for external memory, software programmable up to 256KB per CPU core

  • 2x Octal Serial Peripheral Interface (OSPI) up to 133MHz SDR and DDR
    • 1x with eXecute In Place (XIP) support
    • RAM expansion/Flash over the Air (FOTA)

  • General-Purpose Memory Controller (GPMC)
    • 16-bit parallel data bus with 22-bit address bus and 4 chip selects
    • Up to 4MB addressable memory space
    • Integrated Error Location Module (ELM) support for error checking

System on Chip (SoC) Services and Architecture:

  • 1x EDMA to support data movement functions
  • Device Boot supported from the following interfaces:
    • UART (Primary/Backup)
    • OSPI NOR and NAND Flash (50MHz SDR and 25MHz DDR) (Primary)

    • USB Peripheral boot
  • Interprocessor communication modules
    • SPINLOCK module for synchronizing processes running on multiple cores
    • MAILBOX functionality implemented through CTRLMMR registers
  • Central Platform Time Sync (CPTS) support with time-sync and compare-event interrupt routers
  • Timer Modules:
    • 2x Windowed Watchdog Timer (WWDT)
    • 4x Real Time Interrupt (RTI) timer

USB 2.0

  • Port configurable as USB host, USB device, or USB Dual-Role device
  • USB 2.0 Host mode
    • High-Speed (HS, 480Mbps)
    • Full-Speed (FS, 12Mbps)
    • Low-Speed (LS, 1.5Mbps)
  • USB 2.0 Device mode
    • High-Speed (HS, 480Mbps)
    • Full-Speed (FS, 12Mbps)

Industrial Connectivity:

  • 2x Programmable Real-time Unit – Industrial Communication Subsystem (PRU-ICSS)
    • Dual core Programmable Realtime Unit Subsystem (PRU0 / PRU1) per PRU-ICSS for 4 cores total
      • Deterministic hardware
      • Dynamic firmware
    • 20-channel enhanced input (eGPI) per PRU
    • 20-channel enhanced output (eGPO) per PRU
    • Embedded Peripherals and Memory
      • 1x UART, 1x ECAP, 1x MDIO, 1x IEP
      • 1x 32KB Shared General Purpose RAM
      • 2x 8KB Shared Data RAM
      • 1x 12KB IRAM per PRU
      • ScratchPad (SPAD), MAC/CRC
    • Digital encoder and sigma-delta control loops
    • The PRU-ICSS enables advanced industrial protocols including:
      • EtherCAT, Ethernet/IP™
      • PROFINET, IO-Link
    • Dedicated Interrupt Controller (INTC)
    • Dynamic CONTROLSS XBAR Integration

High Speed Interfaces

  • Integrated 3-port Gigabit Ethernet Switch (CPSW) supporting up to two external ports
    • Selectable MII (10/100), RMII (10/100), or RGMII (10/100/1000)
    • IEEE 1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Clause 45 MDIO PHY management
    • 512x ALE engine based packet classifiers
    • Priority flow control with up to 2KB packet size
    • Four CPU hardware interrupt pacing
    • IP/ UDP/ TCP checksum offload in hardware
    • Time Sensitive Network (TSN) Support
    • Cut-thru switching and Interexpress Traffic (IET) support

General Connectivity:

  • 6x Universal Asynchronous RX-TX (UART)
  • 4x Serial Peripheral Interface (SPI) controllers
  • 3x Local Interconnect Network (LIN) ports
  • 3x Inter-Integrated Circuit (I2C) ports
  • 2x Modular Controller Area Network (MCAN) modules with CAN-FD support
  • 1x Fast Serial Interface Transmitter (FSITX)
  • 1x Fast Serial Interface Receiver (FSIRX)
  • Up to 141x General Purpose I/O (GPIO) pins

Sensing and Actuation:

  • Real-time Control Subsystem (CONTROLSS)
  • Flexible Input/Output Crossbars (XBAR)
  • 3x 12-bit Analog to Digital Converters (ADC) with 3 MSPS maximum sampling rate
    • Each ADC module with
      • 7x Single ended channels OR
      • 3x Differential channels
    • Highly configurable ADC digital logic
      • With selectable internal or external reference
      • 4x Post-Processing blocks for each ADC module
  • 9x Analog Comparators with internal 12-bit DAC reference (CMPSSA)
  • 1x 12 bit Digital to Analog Converter (DAC)
  • 10x Enhanced High Resolution Pulse Width Modulation (eHRPWM) modules
    • Single or Dual PWM channels
    • Advanced PWM Configurations
    • Enhanced HRPWM time resolution
  • 8x Enhanced Capture (ECAP) modules
  • 2x Enhanced Quadrature Encoder Pulse (EQEP) modules
  • 2x Sigma-Delta Filter Modules (SDFM)

Data Storage

  • 1 × 4-bit Multi-Media Card/Secure Digital (MMC/SD) interface

Security:

  • Hardware Security Module (HSM) with support for Auto SHE 1.1/EVITA
  • Targeted for ISO 21434 compliance
  • Secure boot support
    • Device Take Over Protection
    • Hardware enforced root-of-trust
    • Authenticated boot
    • SW Anti-rollback protection
  • Debug security
    • Secure device debug only after proper authentication
    • Ability to disable device debug functionality
  • Device ID and Key Management
    • Support for OTP Memory (FUSEROM)
      • Store root keys and other security fields
    • Separate EFUSE controllers and FUSE ROMs
    • Unique Device Public Identifiers
  • Memory Protection Units (MPU)
    • Dedicated Arm MPU per Cortex-R5F core
    • System MPU - present at various interfaces in the SoC (MPU or Firewall)
    • 8 to 16 Programmable Regions
      • Enable/Privilege ID
      • Start/End Address
      • Read/Write/Cachable
      • Secure/Non-Secure
  • Cryptographic acceleration
    • Cryptographic cores with DMA Support
    • AES - 128/192/256-bit key sizes
    • SHA2 - 256/384/512-bit support
    • DRBG with pseudo and true random number generator

Functional Safety:

  • Enables design of systems with functional safety requirements
    • Error Signaling Module (ESM)
    • ECC or parity on calculation critical memories
    • Built-In Self-Test (BIST) on-chip RAM
    • Runtime internal diagnostic modules including voltage, temperature, and clock monitoring, windowed watchdog timers, CRC engines for memory integrity checks
  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation to be made available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL-3
    • Hardware integrity up to SIL-3
    • Safety-related certification
      • IEC 61508 certified
  • Functional Safety-Compliant [Automotive]
    • Developed for functional safety applications
    • Documentation to be made available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL-D
    • Hardware integrity up to ASIL-D
    • Safety-related certification
      • ISO 26262 certified

Technology / Package:

  • AEC-Q100 qualified for automotive applications
  • ZCZ Package
    • 324-pin NFBGAs
    • 15.00mm × 15.00mm
    • 0.8mm pitch
  • ZFG Package
    • 304-pin NFBGA
    • 13.25mm × 13.25mm
    • 0.65mm pitch
  • ZEJ Package
    • 256-pin NFBGA
    • 13.00mm × 13.00mm
    • 0.8mm pitch
  • ZNC Package
    • 293-pin NFBGA
    • 10.00mm × 10.00mm
    • 0.5mm pitch

The AM261x Sitara Arm Microcontrollers are part of Sitara AM26x real-time MCU families designed to meet the complex real-time processing needs of next generation industrial and automotive embedded products. With scalable Arm Cortex R5F performance and an extensive set of peripherals, AM261x device is designed for a broad range of applications while offering safety features and optimized peripherals for real time control.

Key features and benefits:

  • Peripherals supporting system level connectivity such as Gigabit Ethernet, USB, OSPI/QSPI, CAN, UARTs, SPI and GPIOs.
  • Granular firewalls managed by Hardware Security Manager (HSM) enable developers to implement stringent security minded system design requirements.
  • Up to two R5F cores in cluster with 256KB of shared Tightly Coupled Memory (TCM) per core along with 1.5MB of shared SRAM, greatly reducing the need for external memory.

The AM261x Sitara Arm Microcontrollers are part of Sitara AM26x real-time MCU families designed to meet the complex real-time processing needs of next generation industrial and automotive embedded products. With scalable Arm Cortex R5F performance and an extensive set of peripherals, AM261x device is designed for a broad range of applications while offering safety features and optimized peripherals for real time control.

Key features and benefits:

  • Peripherals supporting system level connectivity such as Gigabit Ethernet, USB, OSPI/QSPI, CAN, UARTs, SPI and GPIOs.
  • Granular firewalls managed by Hardware Security Manager (HSM) enable developers to implement stringent security minded system design requirements.
  • Up to two R5F cores in cluster with 256KB of shared Tightly Coupled Memory (TCM) per core along with 1.5MB of shared SRAM, greatly reducing the need for external memory.

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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet AM261x Sitara™ Microcontrollers datasheet (Rev. C) PDF | HTML 2025年 7月 9日
* Errata AM261x Errata Document (Rev. A) PDF | HTML 2025年 4月 29日
* User guide AM261x Sitara Microcontrollers Technical Reference Manual (Rev. B) PDF | HTML 2025年 7月 1日
* User guide AM261x Sitara Microcontrollers Register Addendum (Rev. A) 2025年 4月 25日
Application note AM26 Ethercat SubDevice with TwinCat PDF | HTML 2025年 12月 10日
White paper Integrating EVCC, DCDC, and Host Architecture: TI Automotive MCUs for Next-Generation EV Charging (Rev. A) PDF | HTML 2025年 11月 13日
Application note Implementing USB True Host Detection on AM261x PDF | HTML 2025年 9月 30日
Application note AM261x Power Estimation Tool PDF | HTML 2025年 7月 11日
Functional safety information AM261 TÜV SÜD Functional Safety Certificate 2025年 7月 10日
Functional safety information AM261 TÜV SÜD Functional Safety Certificate Report 2025年 7月 10日
Product overview AM26xx Family TIFS-SDK Product Brief PDF | HTML 2025年 5月 29日
Application note AM26x Custom PCB System Getting Started Guide (Rev. A) PDF | HTML 2025年 5月 13日
White paper AM261x 和 AM263Px 使用的工业通信协议 PDF | HTML 2025年 5月 12日
User guide AM26x Hardware Design Guidelines (Rev. D) PDF | HTML 2025年 5月 2日
Application note How to Synchronize the Timing Between Chips With Programmable Real-Time Unit PDF | HTML 2025年 3月 10日
White paper Leveraging USB Capabilities on the AM261x Microcontrollers PDF | HTML 2025年 1月 28日
Application note Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 2025年 1月 28日
Application note AM26x Family Migration Overview (Rev. A) PDF | HTML 2024年 11月 15日
Application brief Achieving Faster Secure Boot Time on AM26x Devices PDF | HTML 2024年 11月 13日
User guide AM261x OSPI, QSPI Flash Selection Guide PDF | HTML 2024年 9月 19日

設計與開發

電源供應解決方案

為 AM2612 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

開發板

AM261-SOM-EVM — AM261x 控制系統模組 (SOM) 評估模組

AM261-SOM-EVM 是德州儀器 Sitara™ AM261x 系列微控制器 (MCU) 的評估與開發電路板。該系統模組設計採用三個 120 針腳高速高密度連接器,非常適合初期評估與快速原型開發。使用 AM261-SOM-EVM 進行評估時,需搭配 XDS110ISOEVM(需另行購買或與 AM261-SOM-EVM 成套購買)。
使用指南: PDF | HTML
TI.com 無法提供
開發板

DP83826-EVM-AM2 — 適用於工業乙太網路 PHY 附加電路板的 AM2x 評估模組

DP83826-EVM-AM2 是一款工業乙太網路 PHY 附加電路板,可搭配 AM2x 系列 Sitara™ 高性能微控制器評估模組使用。此附加電路板適合使用 AM2x EVM 進行初始乙太網路評估與原型設計。DP83826-EVM-AM2 配備了有 MII 介面與強化模式的 TI DP83826 低延遲 10/100Mbps PHY,以及標準 RJ45 乙太網路連網連接器。TMDSCNCD263P 和 AM263Px MCU PLUS SDK 目前均支援 DP83826-EVM-AM2。
使用指南: PDF | HTML
TI.com 無法提供
開發板

DP83TG720-EVM-AM2 — 適用於汽車乙太網路 PHY 附加電路板的 AM2x 評估模組

DP83TG720-EVM-AM2 是一款汽車乙太網路 PHY 附加電路板,可搭配 AM2x 系列 Sitara™ 高性能微控制器評估模組使用。此附加電路板適合使用 AM2x EVM 進行初始乙太網路評估與原型設計。DP83TG720-EVM-AM2 配備具有 RGMII & SGMII 的 TI DP82TG720S-Q1 1000BASE-T1 車用乙太網路 PHY,以及 MATEnet 連接器。TMDSCNCD263P 和 AM263Px MCU PLUS SDK 目前均支援 DP83TG720-EVM-AM2。

使用指南: PDF | HTML
TI.com 無法提供
開發板

LP-AM261 — AM261x Arm® 架構 MCU 通用型 LaunchPad™ 開發套件

AM261x LaunchPad™ 開發套件是一款適用於德州儀器™ Sitara™ AM261x 系列微控制器 (MCU) 的簡單又價格便宜之硬體評估模組 (EVM)。此 EVM 透過適用於編程與偵錯的板載模擬,以及可做為簡易使用者介面的使用者控制按鈕與 LED,提供了可輕鬆使用 AM261x MCU 著手開發的方式。
使用指南: PDF | HTML
TI.com 無法提供
開發板

TIPA-050074 — 適用於安全相關應用、使用 TPS653860-Q1 的 AM261x 電源供應設計

本電源設計可用作將 TPS65386x-Q1 電源管理 IC (PMIC) 整合至為功能安全 (FuSa) AM261x Sitara™ 微處理器 (MCU) 供電的安全相關車用系統之指南。

偵錯探測器

TMDSEMU110-U — XDS110 JTAG 偵錯探測器

德州儀器 XDS110 是一種全新的偵錯探測器 (模擬器) 類別,適用於 TI 嵌入式處理器。XDS110 取代 XDS100 系列,可在單一 Pod 中支援更廣泛的標準 (IEEE1149.1、IEEE1149.7、SWD)。同時,所有 XDS 偵錯探針在所有配備嵌入式追蹤緩衝器 (ETB) 的 Arm® 與 DSP 處理器中均支援核心與系統追蹤。  對於針腳上的核心追蹤,則需要 XDS560v2 PRO TRACE

德州儀器 XDS110 透過 TI 20 針腳連接器(具有用於 TI 14 針腳和 Arm 10 針腳和 Arm 20 針腳的多轉接器)連接到目標電路板,並透過 USB2.0 (...)

使用指南: PDF
TI.com 無法提供
偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現,支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意,序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板,並透過 USB2.0 高速 (480Mbps) (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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偵錯探測器

LB-3P-TRACE32-ARM — 適用於 Arm® 架構微控制器和處理器的 Lauterbach TRACE32® 偵錯和追蹤系統

Lauterbach 的 TRACE32® 工具是一套先進的軟硬體元件,可讓開發人員分析、最佳化及認證各種 Arm® 架構微控制器和處理器。全球知名的嵌入式系統和 SoC 偵錯和追蹤解決方案是完美的解決方案,適用於從早期的矽前 (pre-silicon) 開發,到產品認證和現場故障排除等所有開發階段。Lauterbach 工具的直覺模組化設計為工程師提供現今最高的可用性能,以及可隨需求變化而調整和成長的系統。藉由 TRACE32® 偵錯器,開發人員也可透過單一偵錯介面,同時偵錯和控制 SoC 中的任何 C28x/C29x/C6x/C7x DSP 核心及所有其他 Arm (...)

硬體程式設計工具

SOFTM-3P-FLASHRUNNER-2-0 — SMH Technologies FlashRunner 2.0 8 通道及 FlashRunner 2.0 16 通道程式工具

FlashRunner 2.0 是一款通用的系統內編程 (ISP) 解決方案,提供 4 種配置:提供 4、8、12 與 16 通道,最多可並行編程 16 個目標 (搭配解多工器工具可達 32 個目標)。全新圖形使用者介面(Workbench)可縮減整體配置工作,只要客戶按幾下滑鼠就能建立工作專案,並偵測目標裝置與客戶韌體之間的不相符情況,以及電源供應器設定。
若要檢視支援的 TI 裝置,請參閱 https://smh-tech.com/category/texas-instruments/。

硬體程式設計工具

SOFTM-3P-FLASHRUNNER-HS — SMH Technologies FlashRunner 高速編程工具

FlashRunner HS 是一種多端編程系統。典型的編程系統功能由中央控制單元與最多 8 個透過 USB Type-C 線連接的周邊主動模組共同分擔。全新圖形使用者介面(Workbench)可縮減整體配置工作,只要客戶按幾下滑鼠就能建立工作專案,並偵測目標裝置與客戶韌體之間的不相符情況,以及電源供應器設定。


若要檢視支援的 TI 裝置,請參閱 https://smh-tech.com/category/texas-instruments/

硬體程式設計工具

SOFTM-3P-FLASHRUNNER-NXG — SMH Technologies FlashRunner LAN 2.0 下一代編程工具

FlashRunner LAN2.0 NeXt Generation 是一款通用的系統內編程解決方案(ISP),提供 1 至 4 個平行通道。由於簡單的遠程會話,可以啟用更多的通道(從 2 到 4)。FlashRunner LAN2.0 NXG 設計為整合在固定裝置中,因此極為精巧緊湊。全新圖形使用者介面(Workbench)可縮減整體配置工作,只要客戶按幾下滑鼠就能建立工作專案,並偵測目標裝置與客戶韌體之間的不相符情況,以及電源供應器設定。
若要檢視支援的 TI 裝置,請參閱 https://smh-tech.com/category/texas-instruments/。

軟體開發套件 (SDK)

AM261X-MCAL-SDK Microcontroller Abstraction Layer (MCAL) and Complex Device Drivers (CDD) for AM261X

The AM261x microcontroller (MCU) plus software development kit (SDK) is a unified software platform for embedded processors providing easy setup and fast out-of-the-box access to examples, benchmarks and demonstrations. This software accelerates application development schedules by eliminating (...)

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軟體開發套件 (SDK)

AM261X-TIFS-SDK AM261x foundational security software

The AM261x microcontroller (MCU) plus software development kit (SDK) is a unified software platform for embedded processors providing easy setup and fast out-of-the-box access to examples, benchmarks and demonstrations. This software accelerates application development schedules by eliminating (...)

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軟體開發套件 (SDK)

INDUSTRIAL-COMMUNICATIONS-SDK-AM261X Industrial Communications SDK for AM261x

This software development kit (SDK) includes real-time industrial communication protocols (EtherCAT, EtherNet/IP, PROFINET, IO-Link, etc.) on TI processors. It also has PRU-ICSS firmware, drivers, communication stack libraries, and application examples, along with documentation.

What's new:

  • (...)
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瀏覽 下載選項
軟體開發套件 (SDK)

MCU-PLUS-SDK-AM261X MCU+ SDK for AM261x - RTOS, No-RTOS

The AM261x microcontroller (MCU) plus software development kit (SDK) is a unified software platform for embedded processors providing easy setup and fast out-of-the-box access to examples, benchmarks and demonstrations. This software accelerates application development schedules by eliminating (...)

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瀏覽 下載選項
軟體開發套件 (SDK)

MOTOR-CONTROL-SDK-AM261X Motor Control SDK for AM261x

The AM261x microcontroller (MCU) plus software development kit (SDK) is a unified software platform for embedded processors providing easy setup and fast out-of-the-box access to examples, benchmarks and demonstrations. This software accelerates application development schedules by eliminating (...)

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應用軟體及架構

AM261X-RESTRICTED-SAFETY AM261x restricted functional safety content

AM261x restricted functional safety content
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IDE、配置、編譯器或偵錯程式

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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啟動 下載選項
IDE、配置、編譯器或偵錯程式

SYSCONFIG Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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啟動 下載選項
線上培訓

AM26X-ACADEMY AM26x Academy

AM26x Academy features easy-to-use training modules ranging from the basics of getting started to advanced development topics.
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支援軟體

MATHW-3P-AM26X-EC — 德州儀器 AM26x MCU 嵌入式編碼器支援封裝

TI 為各種 AM26x 裝置和評估電路板提供基於模型設計的工作流程。

適用於 AM26x controlCARD 和 LaunchPad 電路板的 Embedded Coder® 支援套件可讓您使用 Simulink® 模型,在 AM26x 裝置上自動创建、載入及运行演算法。  模型在 Simulink 中設計,使用 Embedded Coder 產生程式碼,並在專為即時控制應用設計的 AM263x、AM263Px、AM261x 硬體平台上運行可執行文件,無需使用手動編程。運用業界實證的基於模型設計技術,驗證演算法在模擬期間是否能正常運作,然後使用自動產生程式碼,在 AM26X (...)
模擬型號

AM2612 BSDL Model (Rev. A)

SPRM875A.ZIP (17 KB) - BSDL Model
模擬型號

AM2612 IBIS Model (Rev. A)

SPRM874A.ZIP (6383 KB) - IBIS Model
模擬型號

AM2612 Thermal Model (Rev. A)

SPRM873A.ZIP (5 KB) - Thermal Model
計算工具

AM261X-PET-CALC AM261x Power Estimation Tool

Power Estimation Tool for AM261x Family of Devices. This tool can be used to provide a general estimate of the expected device power consumption for common applications.
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參考設計

TIDA-010973 — 適用於多協定應用的 100Mbps 工業乙太網路通訊模組參考設計

此參考設計可加速多協定 100Mbps 工業乙太網路節點的開發。此設計能讓工程師在搭載整合式工業通訊子系統(ICSS)的 AM261x 上快速建立並部署 EtherCAT®、PROFINET®、EtherNet/IP 和 Modbus® 傳輸控制協定(TCP)的原型。此方法可減少硬體自旋、簡化時脈與功耗,並提供具決定性且時間同步的工廠自動化效能。
Design guide: PDF
參考設計

TIDA-010979 — 具有工業通訊參考設計的 48V 1kW 機器人關節馬達控制

此參考設計採用 TI Sitara™ MCU- AM261x 裝置處理工業乙太網路連線馬達驅動。此設計使用直徑 70mm 的印刷電路板 (PCB) 以驅動人形機器人關節(48V,1kW Eyoubot 馬達)。此設計展示了精巧的外形和簡化的整合平台。此平台包括一個使用三個 DRV7167 半橋 GaN-FET 的高功率密度功率級、一個使用 AM2612 500MHz R5F 核心 MCU 和 AMC0106 功能隔離的 ΔΣ 調變器的準確即時控制級,以及一個透過工業乙太網路運作的高頻寬通訊。此設計通過所有的功能測試。正在進行系統測試。軟體及完整設計指南即將推出。
Design guide: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZCZ) 324 Ultra Librarian
NFBGA (ZFG) 304 Ultra Librarian

訂購與品質

內含資訊:
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊:
  • 晶圓廠位置
  • 組裝地點

建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。

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