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微控制器 (MCU) 與處理器
微處理器和 DSP
多媒體與工業網路 SoC

AM6526

現行

具 gigabit PRU-ICSS 的雙路 Arm® Cortex®-A53 和雙路 Arm Cortex-R5F Sitara™ 處理器

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產品規格表
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AM6526

現行
產品規格表 立即訂購

產品詳細資料

CPU 2 Arm Cortex-A53 Frequency (MHz) 1100 Coprocessors 2 Arm Cortex-R5F Display type MIPI DPI, OLDI Protocols EtherCAT, Ethernet, ICSS, Profibus, Profinet, TSN PCIe 2 PCIe Gen 3 Hardware accelerators CPU only Features Networking Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
CPU 2 Arm Cortex-A53 Frequency (MHz) 1100 Coprocessors 2 Arm Cortex-R5F Display type MIPI DPI, OLDI Protocols EtherCAT, Ethernet, ICSS, Profibus, Profinet, TSN PCIe 2 PCIe Gen 3 Hardware accelerators CPU only Features Networking Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection TI functional safety category Functional Safety-Compliant Rating Catalog Power supply solution TPS6594-Q1 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
FCCSP (ACD) 784 529 mm² 23 x 23

Processor cores:

  • Dual- or quad-core Arm Cortex-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm Cortex-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm Cortex-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core

    Industrial subsystem:

  • Three gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Up to two 10/100/1000 Ethernet ports per PRU_ICSSG
    • Supports two SGMII ports (2)
    • Compatibility with 10/100Mb PRU-ICSS
    • 24× PWMs per PRU_ICSSG
      • Cycle-by-cycle control
      • Enhanced trip control
    • 18× Sigma-delta filters per PRU_ICSSG
      • Short circuit logic
      • Over-current logic
    • 6× Multi-protocol position encoder interfaces per PRU_ICSSG

    Memory subsystem:

  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR4 memory types up to DDR-1600
    • 32-bit data bus and 7-bit SECDED bus
    • 8 GB of total addressable space
  • General-Purpose Memory Controller (GPMC)

    Functional Safety:

  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware Integrity up to SIL 2
    • Safety-related certification
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm Cortex-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC

    Security:

  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software-controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security software

    SoC services:

  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)

    Multimedia:

  • Display subsystem
    • Two fully input-mapped overlay managers associated with two display outputs
    • One port MIPI DPI parallel interface
    • One port OLDI
  • PowerVR SGX544-MP1 3D Graphics Processing Unit (GPU)
  • One Camera Serial Interface-2 (MIPI CSI-2)
  • One port video capture: BT.656/1120 (no embedded sync)

    High-speed interfaces:

  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express ( PCIe) revision 3.1 subsystems (2)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (2)
    • One enhanced SuperSpeed Gen1 port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    General connectivity:

  • 6× Inter-Integrated Circuit ( I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins

    Control interfaces:

  • 6× Enhanced High-Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules

    Automotive interfaces:

  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (MCASP) modules

    Media and data storage:

  • 2× Multimedia Card™/ Secure Digital ( MMC™/ SD) interfaces

    Simplified power management:

  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients

    Analog/system integration:

  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change

    System-on-Chip (SoC) architecture:

  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

Processor cores:

  • Dual- or quad-core Arm Cortex-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm Cortex-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm Cortex-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core

    Industrial subsystem:

  • Three gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Up to two 10/100/1000 Ethernet ports per PRU_ICSSG
    • Supports two SGMII ports (2)
    • Compatibility with 10/100Mb PRU-ICSS
    • 24× PWMs per PRU_ICSSG
      • Cycle-by-cycle control
      • Enhanced trip control
    • 18× Sigma-delta filters per PRU_ICSSG
      • Short circuit logic
      • Over-current logic
    • 6× Multi-protocol position encoder interfaces per PRU_ICSSG

    Memory subsystem:

  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR4 memory types up to DDR-1600
    • 32-bit data bus and 7-bit SECDED bus
    • 8 GB of total addressable space
  • General-Purpose Memory Controller (GPMC)

    Functional Safety:

  • Functional Safety-Compliant [Industrial]
    • Developed for functional safety applications
    • Documentation available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3
    • Hardware Integrity up to SIL 2
    • Safety-related certification
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm Cortex-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC

    Security:

  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software-controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security software

    SoC services:

  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)

    Multimedia:

  • Display subsystem
    • Two fully input-mapped overlay managers associated with two display outputs
    • One port MIPI DPI parallel interface
    • One port OLDI
  • PowerVR SGX544-MP1 3D Graphics Processing Unit (GPU)
  • One Camera Serial Interface-2 (MIPI CSI-2)
  • One port video capture: BT.656/1120 (no embedded sync)

    High-speed interfaces:

  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express ( PCIe) revision 3.1 subsystems (2)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (2)
    • One enhanced SuperSpeed Gen1 port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    General connectivity:

  • 6× Inter-Integrated Circuit ( I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins

    Control interfaces:

  • 6× Enhanced High-Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules

    Automotive interfaces:

  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (MCASP) modules

    Media and data storage:

  • 2× Multimedia Card™/ Secure Digital ( MMC™/ SD) interfaces

    Simplified power management:

  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients

    Analog/system integration:

  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change

    System-on-Chip (SoC) architecture:

  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

AM654x and AM652x Sitara™ processors are Arm applications processors built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Arm Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm Cortex-A53 RISC CPUs with Arm Neon™ extension, and the dual Arm Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.

AM654x and AM652x Sitara™ processors are Arm applications processors built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm Cortex-A53 cores with a dual Arm Cortex-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Arm Cortex-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm Cortex-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm Cortex-A53 RISC CPUs with Arm Neon™ extension, and the dual Arm Cortex-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.
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技術文件

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重要文件 類型 標題 格式選項 日期
* Data sheet AM654x, AM652x Sitara™ Processors Silicon Revision 2.1 datasheet (Rev. C) PDF | HTML 2023年 9月 15日
* Errata AM65x Processors Silicon Revision 2.1/2.0/1.0 (Rev. I) PDF | HTML 2023年 5月 4日
* User guide AM65x/DRA80xM Processors Technical Reference Manual (Rev. E) 2019年 12月 18日
Application note Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. H) PDF | HTML 2025年 10月 17日
User guide TPS65941319-Q1 PMIC User Guide for Sitara AM65 Processors (Rev. A) PDF | HTML 2025年 6月 25日
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 2024年 5月 14日
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 2023年 11月 15日
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 2023年 7月 31日
Application note Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 2023年 5月 24日
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
Application note Hardware Design Guide for AM65x Devices (Rev. A) PDF | HTML 2022年 12月 22日
Application note PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022年 10月 11日
White paper 運用適合工業 4.0 Sitara™ 伺服驅動器的處理器與微控制器 (Rev. C) PDF | HTML 2022年 1月 12日
Application note AM65x/DRA80x Schematic Checklist (Rev. A) PDF | HTML 2021年 7月 26日
White paper EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 2020年 7月 28日
Application note AM65x/DRA80xM EMIF Tools (Rev. B) 2020年 3月 4日
E-book E-book: An engineer’s guide to industrial robot designs 2020年 2月 12日
Application note AM65xx Time Synchronization Architecture PDF | HTML 2019年 10月 14日
Application note Enabling Android Automotive on Your TI Development Board PDF | HTML 2019年 7月 12日
Application note AM65x DDR ECC Initialization and Testing 2019年 3月 8日
Application note AM65x/DRA80xM DDR Board Design and Layout Guidelines (Rev. A) 2019年 3月 7日
White paper Virtualization for embedded industrial systems (Rev. B) 2019年 3月 7日
Application note Integrating a WiLink8 Module with the AM65x EVM 2019年 1月 29日
Application note PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) 2019年 1月 18日
Application note PRU Read Latencies (Rev. A) 2018年 12月 21日
Application note PRU-ICSS Getting Starting Guide on Linux (Rev. A) 2018年 12月 10日
White paper Ensuring real-time predictability (Rev. B) 2018年 12月 4日
Application note AM65xx System Performance 2018年 11月 30日
Functional safety information The state of functional safety in Industry 4.0 2018年 11月 27日
Application note PRU-ICSS / PRU_ICSSG Migration Guide 2018年 11月 5日
White paper Secure Boot on embedded Sitara™ processors (Rev. A) 2018年 10月 13日
White paper Designing industrial controls for Industry 4.0 with Sitara™ AM6x processors 2018年 10月 11日
User guide AM654x/DRA80xM BGA Escape Routing Stackup 2018年 8月 29日
White paper Designing Embedded Systems for High Reliability With Sitara AM6x Processors 2018年 8月 28日

設計與開發

電源供應解決方案

為 AM6526 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

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開發板

TMDSLCD1EVM — 1280x800 LCD 顯示器配件組

1280x800 LCD 顯示器配件組是 AM65x IDK (TMDX654IDKEVM) 的附加配件，可增添觸控與顯示功能，以評估 HMI、工業 PC 和其它需要顯示器的應用實例。1280x800 LCD 顯示器配件套件與 AM65x EVM (TMDX654GPEVM) 搭售，也可單獨訂購（作為替代方案）。LCD 螢幕是 10.1" 顯示器，具備 WXGA 解析度 (1280x800) 且支援 10 點電容式觸控。

TI.com 無法提供
開發板

TMDX654IDKEVM — AM65x 工業開發套件 (IDK)

AM65x 工業開發套件 (IDK) 是一款開發平台，可評估 Sitara ™ AM65x 處理器的工業通訊與控制功能，適用於工廠自動化，驅動器，機器人，電網基礎架構等應用。AM65x 處理器包含三個 PRU-ICSS（工業通訊可編程即時單元）子系統，可用於 Profinet、EtherCAT、EtherNet/IP 等 GB 工業乙太網路通訊協定。

使用指南: PDF | HTML
TI.com 無法提供
開發板

MISTR-3P-SOM-AM65X — Mistral Solutions AM65x 系統模組 (SOM)

The AM65x SOM from Mistral is an easy to use, compact, light-weight system on module (SOM) providing very high processing power for industrial applications. This module is based on Texas Instruments Sitara™ AM6548 SoC and is ideal for complex processing, connectivity and control required for (...)

從：Mistral Solutions Pvt. Ltd
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開發板

PHYTC-3P-PHYCORE-AM65X — 模組上的 PHYTEC phyCORE-AM65x 系統

phyCORE®-AM65x 模組為 phyCORE® 系列帶來安全開機，多協定 GB 工業通訊，繪圖，功能安全特性和時效性網路 (TSN)。phyCORE®-AM65x SOM 相當適合工業通訊系統，工廠自動化，邊緣運算，電網基礎架構，以及需要高可靠性的應用。運用四核心 Arm® Cortex®-A53 核心執行您的應用程式、6 個工業 PRU 介面用於時間敏感通訊協定以及獨立的雙 Cortex®-R5F 核心用於功能安全支援。

PHYTEC 是能讓客戶快速且輕易的將複雜產品導入市場的領先業界系統模組 (...)

從：PHYTEC
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開發板

TQ-3P-SITARASOMS — 適用於 TI Arm 架構處理器和微控制器的 TQ Group 系統模組

TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)
從：TQ-Group
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開發板

TQ-3P-SOM-TQMA65XX — 適用 AM6528 Arm 處理器的 TQ-Group TQMa65xx 系統模組

以德州儀器 ARM® Cortex®-A53 技術為基礎的嵌入式模組 TQMa65xx。整合式圖形控制器支援具顯示與觸控的應用程序。共有四種處理器機型可供各種應用使用，例如需快速可靠資料處理的網路、工業自動化和控制系統。利用整合在 CPU中的可編程即時單元 (PRU) 及具備 TSN 支援的最高 6-Gigabit 乙太網路介面執行即時網路。兩個 ARM® Cortex®-R5F 控制器支援 CPU 安全與保全。

從：TQ-Group
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開發板

ZLG-3P-M65XX — 適用於 AM65xx ARM Cortex-A53 1.1GHz 處理器的 ZLG M65xx 系統模組

M65xx 系列核心電路板採用主頻高達 1.1GHz 的 TI AM65xx 系列雙核心/四核心 Cortex®-A53 處理器和兩個主頻 400MHz 的 Cortex®-R5F 核心，可選配 1GB 或 2GB DDR3L 記憶體和可選配 DDR ECC 功能，eMMC 記憶體有 4GB 或 8GB 兩種版本，資源豐富，介面齊全，效能強勁，可靠性高。

從：Guangzhou ZHIYUAN Electronics Co.,Ltd.
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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

MCU-PLUS-SDK-AM65X — MCU+ SDK for AM65x – RTOS

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-AM65X — Linux processor SDK for AM65x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-AM65X — Linux-RT processor SDK for AM65x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and (...)

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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-AM65X — RTOS Processor SDK for AM65x

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and (...)

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驅動程式或資料庫

WIND-3P-VXWORKS-LINUX-OS — Wind River 處理器 VxWorks 和 Linux 作業系統

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
從：Wind River Systems
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IDE、配置、編譯器或偵錯程式

C2000_CLA_SAFETI_CQKIT_RV — C2000™ and CLA safety compiler qualification kit (leverages compiler release validations)

The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • is free of charge for TI customers
  • does (...)
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

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作業系統 (OS)

GHS-3P-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
從：Green Hills Software
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作業系統 (OS)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
從：Green Hills Software
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軟體程式設計工具

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash is a software tool for programming on-chip flash on TI microcontrollers and wireless connectivity devices and on-board flash for TI processors. UniFlash provides both graphical and command-line interfaces.

UniFlash can be run from the cloud on the TI Developer Zone or downloaded and used (...)

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模擬型號

AM654x/DRA80xM BSDL Model

SPRM724.ZIP (12 KB) - BSDL Model
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模擬型號

AM654x/DRA80xM IBIS File

SPRM737.ZIP (19753 KB) - IBIS Model
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模擬型號

AM654x/DRA80xM Thermal Models

SPRM718.ZIP (2 KB) - Thermal Model
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
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計算工具

SITARA-DDR-CONFIG-TOOL — Sitara 外部記憶體介面 (EMIF) 工具

Sitara™ EMIF 工具是一款軟體工具，提供配置 TI 處理器以存取外部 DDR 記憶體裝置的介面。該工具還最佳化延遲鎖定迴路 (DLL) 設定，以補償電路板佈線偏斜。結果輸出為 EMIF 配置暫存器，可導入以在處理器 SDK、Code Composer Studio 或自訂軟體中使用。  
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FCCSP (ACD) 784 Ultra Librarian
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