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微控制器 (MCU) 與處理器
微處理器和 DSP
多媒體與工業網路 SoC

AM4372

現行

Sitara 處理器：Arm Cortex-A9

立即訂購
產品規格表

AM4372

現行
產品規格表 立即訂購

產品詳細資料

CPU 1 Arm Cortex-A9 Frequency (MHz) 600, 800 Display type 1 LCD Protocols Ethernet Hardware accelerators CPU only, Security Accelerator Features General purpose Operating system Linux, RTOS Security Cryptographic acceleration, Hardware-enforced isolation, Secure boot, Secure debug Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
CPU 1 Arm Cortex-A9 Frequency (MHz) 600, 800 Display type 1 LCD Protocols Ethernet Hardware accelerators CPU only, Security Accelerator Features General purpose Operating system Linux, RTOS Security Cryptographic acceleration, Hardware-enforced isolation, Secure boot, Secure debug Rating Catalog Power supply solution TPS65216, TPS65218D0 Operating temperature range (°C) -40 to 105 Edge AI enabled Yes
NFBGA (ZDN) 491 289 mm² (17 mm × 17 mm)
  • Highlights
    • Sitara™ ARM® Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 1000 MHz
      • NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
      • 32KB of Both L1 Instruction and Data Cache
      • 256KB of L2 Cache or L3 RAM
    • 32-Bit LPDDR2, DDR3, and DDR3L Support
    • General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC
    • SGX530 Graphics Engine
    • Display Subsystem
    • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Real-Time Clock (RTC)
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • 10, 100, and 1000 Ethernet Switch Supporting up to Two Ports
    • Serial Interfaces:
      • Two Controller Area Network (CAN) Ports
      • Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire
    • Security
      • Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)
      • Secure Boot (Avaliable Only on AM437x High-Security [AM437xHS] Devices)
    • Two 12-Bit Successive Approximation Register (SAR) ADCs
    • Up to Three 32-Bit Enhanced Capture (eCAP) Modules
    • Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules
  • MPU Subsystem
    • ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 1000 MHz
    • 32KB of Both L1 Instruction and Data Cache
    • 256KB of L2 Cache (Option to Configure as L3 RAM)
    • 256KB of On-Chip Boot ROM
    • 64KB of On-Chip RAM
    • Secure Control Module (SCM) (Avaliable Only on AM437xHS Devices)
    • Emulation and Debug
      • JTAG
      • Embedded Trace Buffer
    • Interrupt Controller
  • On-Chip Memory (Shared L3 RAM)
    • 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
    • Up to 512KB of Total Internal RAM
      (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
  • External Memory Interfaces (EMIFs)
    • DDR Controllers:
      • LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
      • DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)
      • 32-Bit Data Bus
      • 2GB of Total Addressable Space
      • Supports One x32, Two x16, or Four x8 Memory Device Configurations
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
  • Error Locator Module (ELM)
    • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
    • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and More
    • Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores Each
      • Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz
      • 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)
      • 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal
    • 12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller Module (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One eCAP Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
    • Industrial Communication is Supported by Two PRU-ICSS Subsystems
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], and LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP])
      • Three Switchable Power Domains (MPU Subsystem, SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO
    • Independent Power-On-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (RTC_WAKEUP) for External Wake Events
    • Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or Cortex-A9 for Event Notification
    • Programmable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs
      (10, 100, and 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, and RGMII and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v2 Precision Time Protocol (PTP)
    • Up to Two CAN Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins Per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Five Master and Slave McSPIs
      • McSPI0–McSPI2 Support up to Four Chip Selects
      • McSPI3 and McSPI4 Support up to Two Chip Selects
      • Up to 48 MHz
    • One Quad-SPI
      • Supports eXecute In Place (XIP) from Serial NOR FLASH
    • One Dallas 1-Wire® and HDQ Serial Interface
    • Up to Three MMC, SD, and SDIO Ports
      • 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes
      • 1.8- or 3.3-V Operation on All Ports
      • Up to 48-MHz Clock
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3 and SD and SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Six Banks of General-Purpose I/O (GPIO)
      • 32 GPIOs per Bank (Multiplexed With Other Functional Pins)
      • GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs
    • Twelve 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Public Watchdog Timer
    • One Free-Running, High-Resolution 32-kHz Counter (synctimer32K)
    • One Secure Watchdog Timer (Avaliable Only on AM437xHS Devices)
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20M Poly/sec
      • Universal Scalable Shader Engine is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • Display Subsystem
      • Display Modes
        • Programmable Pixel Memory Formats (Palletized: 1-, 2-, 4-, and 8-Bits Per Pixel; RGB 16- and 24-Bits Per Pixel; and YUV 4:2:2)
        • 256- × 24-Bit Entries Palette in RGB
        • Up to 2048 × 2048 Resolution
      • Display Support
        • Four Types of Displays Are Supported: Passive and Active Colors; Passive and Active Monochromes
        • 4- and 8-Bit Monochrome Passive Panel Interface Support (15 Grayscale Levels Supported Using Dithering Block)
        • RGB 8-Bit Color Passive Panel Interface Support (3,375 Colors Supported for Color Panel Using Dithering Block)
        • RGB 12-, 16-, 18-, and 24-Bit Active Panel Interface Support (Replicated or Dithered Encoded Pixel Values)
        • Remote Frame Buffer (Embedded in the LCD Panel) Support Through the RFBI Module
        • Partial Refresh of the Remote Frame Buffer Through the RFBI Module
        • Partial Display
        • Multiple Cycles Output Format on 8-, 9-, 12-, and 16-Bit Interface (TDM)
      • Signal Processing
        • Overlay and Windowing Support for One Graphics Layer (RGB or CLUT) and Two Video Layers (YUV 4:2:2, RGB16, and RGB24)
        • RGB 24-Bit Support on the Display Interface, Optionally Dithered to RGB 18‑Bit Pixel Output Plus 6-Bit Frame Rate Control (Spatial and Temporal)
        • Transparency Color Key (Source and Destination)
        • Synchronized Buffer Update
        • Gamma Curve Support
        • Multiple-Buffer Support
        • Cropping Support
        • Color Phase Rotation
    • Two 12-Bit SAR ADCs (ADC0, ADC1)
      • 867K Samples Per Second
      • Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • ADC0 Can Be Configured to Operate as a 4‑, 5-, or 8-Wire Resistive Touch Screen Controller (TSC)
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Six Enhanced eHRPWM Modules
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit eQEP Modules
  • Device Identification
    • Factory Programmable Electrical Fuse Farm (FuseFarm)
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
      • Security Keys (Avaliable Only on AM437xHS Devices)
      • Feature Identification
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug
    • Supports Real-Time Trace Pins (for Cortex-A9)
    • 64-KB Embedded Trace Buffer (ETB)
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels
    • EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, and Slave Peripherals)
  • InterProcessor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Camera
    • Dual Port 8- and 10-Bit BT656 Interface
    • Dual Port 8- and 10-Bit Including External Syncs
    • Single Port 12-Bit
    • YUV422/RGB422 and BT656 Input Format
    • RAW Format
    • Pixel Clock Rate up to 75 MHz
  • Package
    • 491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing
  • Highlights
    • Sitara™ ARM® Cortex®-A9 32-Bit RISC Processor With Processing Speed up to 1000 MHz
      • NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
      • 32KB of Both L1 Instruction and Data Cache
      • 256KB of L2 Cache or L3 RAM
    • 32-Bit LPDDR2, DDR3, and DDR3L Support
    • General-Purpose Memory Support (NAND, NOR, SRAM) Supporting up to 16-Bit ECC
    • SGX530 Graphics Engine
    • Display Subsystem
    • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Real-Time Clock (RTC)
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • 10, 100, and 1000 Ethernet Switch Supporting up to Two Ports
    • Serial Interfaces:
      • Two Controller Area Network (CAN) Ports
      • Six UARTs, Two McASPs, Five McSPIs, Three I2C Ports, One QSPI, and One HDQ or 1-Wire
    • Security
      • Crypto Hardware Accelerators (AES, SHA, RNG, DES, and 3DES)
      • Secure Boot (Avaliable Only on AM437x High-Security [AM437xHS] Devices)
    • Two 12-Bit Successive Approximation Register (SAR) ADCs
    • Up to Three 32-Bit Enhanced Capture (eCAP) Modules
    • Up to Three Enhanced Quadrature Encoder Pulse (eQEP) Modules
    • Up to Six Enhanced High-Resolution PWM (eHRPWM) Modules
  • MPU Subsystem
    • ARM Cortex-A9 32-Bit RISC Microprocessor With Processing Speed up to 1000 MHz
    • 32KB of Both L1 Instruction and Data Cache
    • 256KB of L2 Cache (Option to Configure as L3 RAM)
    • 256KB of On-Chip Boot ROM
    • 64KB of On-Chip RAM
    • Secure Control Module (SCM) (Avaliable Only on AM437xHS Devices)
    • Emulation and Debug
      • JTAG
      • Embedded Trace Buffer
    • Interrupt Controller
  • On-Chip Memory (Shared L3 RAM)
    • 256KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
    • Accessible to All Masters
    • Supports Retention for Fast Wakeup
    • Up to 512KB of Total Internal RAM
      (256KB of ARM Memory Configured as L3 RAM + 256KB of OCMC RAM)
  • External Memory Interfaces (EMIFs)
    • DDR Controllers:
      • LPDDR2: 266-MHz Clock (LPDDR2-533 Data Rate)
      • DDR3 and DDR3L: 400-MHz Clock (DDR-800 Data Rate)
      • 32-Bit Data Bus
      • 2GB of Total Addressable Space
      • Supports One x32, Two x16, or Four x8 Memory Device Configurations
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
  • Error Locator Module (ELM)
    • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
    • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
    • Supports Protocols such as EtherCAT®, PROFIBUS®, PROFINET®, and EtherNet/IP™, EnDat 2.2, and More
    • Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores Each
      • Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200 MHz
      • 12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM With Single-Error Detection (Parity)
      • 8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM With Single-Error Detection (Parity)
      • Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
      • Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch on External Signal
    • 12KB (PRU-ICSS1 Only) of Shared RAM With Single-Error Detection (Parity)
    • Three 120-Byte Register Banks Accessible by Each PRU
    • Interrupt Controller Module (INTC) for Handling System Input Events
    • Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
    • Peripherals Inside the PRU-ICSS
      • One UART Port With Flow Control Pins, Supports up to 12 Mbps
      • One eCAP Module
      • Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
      • One MDIO Port
    • Industrial Communication is Supported by Two PRU-ICSS Subsystems
  • Power, Reset, and Clock Management (PRCM) Module
    • Controls the Entry and Exit of Deep-Sleep Modes
    • Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
    • Clocks
      • Integrated High-Frequency Oscillator Used to Generate a Reference Clock (19.2, 24, 25, and 26 MHz) for Various System and Peripheral Clocks
      • Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
      • Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB, and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], and LCD Pixel Clock)
    • Power
      • Two Nonswitchable Power Domains (RTC and Wake-Up Logic [WAKE-UP])
      • Three Switchable Power Domains (MPU Subsystem, SGX530 [GFX], Peripherals and Infrastructure [PER])
      • Dynamic Voltage Frequency Scaling (DVFS)
  • Real-Time Clock (RTC)
    • Real-Time Date (Day, Month, Year, and Day of Week) and Time (Hours, Minutes, and Seconds) Information
    • Internal 32.768-kHz Oscillator, RTC Logic, and 1.1-V Internal LDO
    • Independent Power-On-Reset (RTC_PWRONRSTn) Input
    • Dedicated Input Pin (RTC_WAKEUP) for External Wake Events
    • Programmable Alarm Can Generate Internal Interrupts to the PRCM for Wakeup or Cortex-A9 for Event Notification
    • Programmable Alarm Can Be Used With External Output (RTC_PMIC_EN) to Enable the Power-Management IC to Restore Non-RTC Power Domains
  • Peripherals
    • Up to Two USB 2.0 High-Speed Dual-Role (Host or Device) Ports With Integrated PHY
    • Up to Two Industrial Gigabit Ethernet MACs
      (10, 100, and 1000 Mbps)
      • Integrated Switch
      • Each MAC Supports MII, RMII, and RGMII and MDIO Interfaces
      • Ethernet MACs and Switch Can Operate Independent of Other Functions
      • IEEE 1588v2 Precision Time Protocol (PTP)
    • Up to Two CAN Ports
      • Supports CAN Version 2 Parts A and B
    • Up to Two Multichannel Audio Serial Ports (McASPs)
      • Transmit and Receive Clocks up to 50 MHz
      • Up to Four Serial Data Pins Per McASP Port With Independent TX and RX Clocks
      • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
      • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
      • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Up to Six UARTs
      • All UARTs Support IrDA and CIR Modes
      • All UARTs Support RTS and CTS Flow Control
      • UART1 Supports Full Modem Control
    • Up to Five Master and Slave McSPIs
      • McSPI0–McSPI2 Support up to Four Chip Selects
      • McSPI3 and McSPI4 Support up to Two Chip Selects
      • Up to 48 MHz
    • One Quad-SPI
      • Supports eXecute In Place (XIP) from Serial NOR FLASH
    • One Dallas 1-Wire® and HDQ Serial Interface
    • Up to Three MMC, SD, and SDIO Ports
      • 1-, 4-, and 8-Bit MMC, SD, and SDIO Modes
      • 1.8- or 3.3-V Operation on All Ports
      • Up to 48-MHz Clock
      • Supports Card Detect and Write Protect
      • Complies With MMC4.3 and SD and SDIO 2.0 Specifications
    • Up to Three I2C Master and Slave Interfaces
      • Standard Mode (up to 100 kHz)
      • Fast Mode (up to 400 kHz)
    • Up to Six Banks of General-Purpose I/O (GPIO)
      • 32 GPIOs per Bank (Multiplexed With Other Functional Pins)
      • GPIOs Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
    • Up to Three External DMA Event Inputs That Can Also be Used as Interrupt Inputs
    • Twelve 32-Bit General-Purpose Timers
      • DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
      • DMTIMER4–DMTIMER7 are Pinned Out
    • One Public Watchdog Timer
    • One Free-Running, High-Resolution 32-kHz Counter (synctimer32K)
    • One Secure Watchdog Timer (Avaliable Only on AM437xHS Devices)
    • SGX530 3D Graphics Engine
      • Tile-Based Architecture Delivering up to 20M Poly/sec
      • Universal Scalable Shader Engine is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
      • Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
      • Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0
      • Fine-Grained Task Switching, Load Balancing, and Power Management
      • Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
      • Programmable High-Quality Image Anti-Aliasing
      • Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
    • Display Subsystem
      • Display Modes
        • Programmable Pixel Memory Formats (Palletized: 1-, 2-, 4-, and 8-Bits Per Pixel; RGB 16- and 24-Bits Per Pixel; and YUV 4:2:2)
        • 256- × 24-Bit Entries Palette in RGB
        • Up to 2048 × 2048 Resolution
      • Display Support
        • Four Types of Displays Are Supported: Passive and Active Colors; Passive and Active Monochromes
        • 4- and 8-Bit Monochrome Passive Panel Interface Support (15 Grayscale Levels Supported Using Dithering Block)
        • RGB 8-Bit Color Passive Panel Interface Support (3,375 Colors Supported for Color Panel Using Dithering Block)
        • RGB 12-, 16-, 18-, and 24-Bit Active Panel Interface Support (Replicated or Dithered Encoded Pixel Values)
        • Remote Frame Buffer (Embedded in the LCD Panel) Support Through the RFBI Module
        • Partial Refresh of the Remote Frame Buffer Through the RFBI Module
        • Partial Display
        • Multiple Cycles Output Format on 8-, 9-, 12-, and 16-Bit Interface (TDM)
      • Signal Processing
        • Overlay and Windowing Support for One Graphics Layer (RGB or CLUT) and Two Video Layers (YUV 4:2:2, RGB16, and RGB24)
        • RGB 24-Bit Support on the Display Interface, Optionally Dithered to RGB 18‑Bit Pixel Output Plus 6-Bit Frame Rate Control (Spatial and Temporal)
        • Transparency Color Key (Source and Destination)
        • Synchronized Buffer Update
        • Gamma Curve Support
        • Multiple-Buffer Support
        • Cropping Support
        • Color Phase Rotation
    • Two 12-Bit SAR ADCs (ADC0, ADC1)
      • 867K Samples Per Second
      • Input Can Be Selected from Any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
      • ADC0 Can Be Configured to Operate as a 4‑, 5-, or 8-Wire Resistive Touch Screen Controller (TSC)
    • Up to Three 32-Bit eCAP Modules
      • Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
    • Up to Six Enhanced eHRPWM Modules
      • Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
      • Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
    • Up to Three 32-Bit eQEP Modules
  • Device Identification
    • Factory Programmable Electrical Fuse Farm (FuseFarm)
      • Production ID
      • Device Part Number (Unique JTAG ID)
      • Device Revision (Readable by Host ARM)
      • Security Keys (Avaliable Only on AM437xHS Devices)
      • Feature Identification
  • Debug Interface Support
    • JTAG and cJTAG for ARM (Cortex-A9 and PRCM) and PRU-ICSS Debug
    • Supports Real-Time Trace Pins (for Cortex-A9)
    • 64-KB Embedded Trace Buffer (ETB)
    • Supports Device Boundary Scan
    • Supports IEEE 1500
  • DMA
    • On-Chip Enhanced DMA Controller (EDMA) Has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels
    • EDMA is Used for:
      • Transfers to and from On-Chip Memories
      • Transfers to and from External Storage (EMIF, GPMC, and Slave Peripherals)
  • InterProcessor Communication (IPC)
    • Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between the Cortex-A9, PRCM, and PRU-ICSS
  • Boot Modes
    • Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
  • Camera
    • Dual Port 8- and 10-Bit BT656 Interface
    • Dual Port 8- and 10-Bit Including External Syncs
    • Single Port 12-Bit
    • YUV422/RGB422 and BT656 Input Format
    • RAW Format
    • Pixel Clock Rate up to 75 MHz
  • Package
    • 491-Pin BGA Package (17-mm × 17-mm) (ZDN Suffix), 0.65-mm Ball Pitch With Via Channel Array Technology to Enable Low-Cost Routing

The TI AM437x high-performance processors are based on the ARM Cortex-A9 core.

The processors are enhanced with 3D graphics acceleration for rich graphical user interfaces, as well as a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux® is available free of charge from TI. Other HLOSs are available from TI’s Design Network and ecosystem partners.

These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2.

The processors contain the subsystems shown in the Functional Block Diagram, and a brief description of each follows.

The processor subsystem is based on the ARM Cortex-A9 core, and the PowerVR SGX™ graphics accelerator subsystem provides 3D graphics acceleration to support display and advanced user interfaces.

The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC.

High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.

One on-chip analog to digital converter (ADC0) can couple with the display subsystem to provide an integrated touch-screen solution. The other ADC (ADC1) can combine with the pulse width module to create a closed-loop motor control solution.

The RTC provides a clock reference on a separate power domain. The clock reference enables a battery-backed clock reference.

The camera interface offers configuration for a single- or dual-camera parallel port.

Cryptographic acceleration is available in all devices. All other supported security features, including support for Secure boot, debug security and support for Trusted execution environment is available on HS (High-Security) devices. For more information about HS devices, contact your TI sales representative.

The TI AM437x high-performance processors are based on the ARM Cortex-A9 core.

The processors are enhanced with 3D graphics acceleration for rich graphical user interfaces, as well as a coprocessor for deterministic, real-time processing including industrial communication protocols, such as EtherCAT, PROFIBUS, EnDat, and others. The devices support high-level operating systems (HLOS). Linux® is available free of charge from TI. Other HLOSs are available from TI’s Design Network and ecosystem partners.

These devices offer an upgrade to systems based on lower performance ARM cores and provide updated peripherals, including memory options such as QSPI-NOR and LPDDR2.

The processors contain the subsystems shown in the Functional Block Diagram, and a brief description of each follows.

The processor subsystem is based on the ARM Cortex-A9 core, and the PowerVR SGX™ graphics accelerator subsystem provides 3D graphics acceleration to support display and advanced user interfaces.

The programmable real-time unit subsystem and industrial communication subsystem (PRU-ICSS) is separate from the ARM core and allows independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol in parallel. Additionally, the programmable nature of the PRU-ICSS, along with their access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast real-time responses, specialized data handling operations, custom peripheral interfaces, and in off-loading tasks from the other processor cores of the SoC.

High-performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.

One on-chip analog to digital converter (ADC0) can couple with the display subsystem to provide an integrated touch-screen solution. The other ADC (ADC1) can combine with the pulse width module to create a closed-loop motor control solution.

The RTC provides a clock reference on a separate power domain. The clock reference enables a battery-backed clock reference.

The camera interface offers configuration for a single- or dual-camera parallel port.

Cryptographic acceleration is available in all devices. All other supported security features, including support for Secure boot, debug security and support for Trusted execution environment is available on HS (High-Security) devices. For more information about HS devices, contact your TI sales representative.
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特別說明

AM437xS 安全啟動裝置的進階安全防護可應要求提供。要申請安全文件，請造訪此頁面。要獲得安全軟體，請使用此申請表。

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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 AM437x Sitara™ Processors datasheet (Rev. E) PDF | HTML 2018/3/21
* 勘誤表 AM437x Sitara Processors Silicon Errata (Silicon Revisions 1.1, 1.2) (Rev. D) PDF | HTML 2021/6/3
應用說明 HSR/PRP Solutions on Sitara Processors for Grid Substation Communication (Rev. A) PDF | HTML 2026/1/30
應用說明 Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 2025/11/24
白皮書 Securing Arm-Based Application Processors (Rev. F) PDF | HTML 2025/2/26
應用說明 Basic Ethernet Interface Debug With Linux PDF | HTML 2024/10/11
白皮書 Time Sensitive Networking for Industrial Automation (Rev. C) PDF | HTML 2023/7/31
應用說明 Intra Drive Communication Using 8b-10b Line Code With Programmable Real Time Uni PDF | HTML 2023/5/24
應用說明 PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022/10/11
應用說明 nfBGA Packaging (Rev. C) PDF | HTML 2021/5/17
應用說明 Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A) 2021/5/7
更多文件說明 From Start to Finish: A Product Development Roadmap for Sitara™ Processors 2020/12/16
更多文件說明 Building your application with security in mind (Rev. E) 2020/10/28
應用說明 AM437x Schematic Checklist (Rev. A) PDF | HTML 2020/9/25
白皮書 EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) 2020/7/28
使用指南 Powering the AM335x, AM437x, and AM438x with TPS65218D0 (Rev. B) 2020/2/27
使用指南 AM437x and AMIC120 ARM® Cortex™-A9 Processors Technical Reference Manual (Rev. I) 2019/12/23
應用說明 Programmable Logic Controllers — Security Threats and Solutions PDF | HTML 2019/9/13
應用說明 Calculating Useful Lifetimes of Embedded Processors (Rev. B) PDF | HTML 2019/5/7
應用說明 AM43xx EMIF Tools (Rev. A) 2019/4/18
使用指南 Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216 PDF | HTML 2019/4/11
Application brief Flexible Timing Configuration with IO-Link Master Frame Handler 2019/3/26
應用說明 PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) 2019/1/18
應用說明 McASP Design Guide - Tips, Tricks, and Practical Examples 2019/1/10
應用說明 PRU Read Latencies (Rev. A) 2018/12/21
應用說明 PRU-ICSS Getting Starting Guide on Linux (Rev. A) PDF | HTML 2018/12/10
應用說明 PRU-ICSS EtherCAT Slave Troubleshooting Guide 2018/11/7
應用說明 PRU-ICSS / PRU_ICSSG Migration Guide PDF | HTML 2018/11/5
使用指南 How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018/9/24
白皮書 Achieving increased functionality and efficiency in vacuum robots 2017/12/21
使用指南 Discrete Power Solution for AM437x (Rev. A) 2017/12/1
應用說明 Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017/8/14
應用說明 AM43xx Power Estimation Tool 2017/8/7
Product overview AM43x Security Product Bulletin (Rev. A) 2017/5/26
應用說明 Sitara AM437x DDR-Less System How-To Instructions and Benchmarks (Rev. A) 2017/2/21
白皮書 Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A) 2016/8/11
應用說明 Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015/8/13

設計與開發

電源供應解決方案

為 AM4372 尋找可用的電源供應解決方案。TI 提供適用於 TI 與非 TI 之系統單晶片 (SoC)、處理器、微控制器、感測器或現場可編程邏輯閘陣列 (FPGA) 的電源供應解決方案。

檢視解決方案
開發板

TMDSEVM437X — AM437x 評估模組

AM437x 評估模組 (EVM) TMDXEVM437X 可讓開發人員立即開始評估 AM437x 處理器系列 (AM4372、AM4376、AM4377、AM4378)，並著手建置應用程式，以及加速開發 HMI、工業和網路應用。TMDSEVM437X 開發平台是以 Arm Cortex-A9 處理器為基礎，並與多個選項整合，例如 Gigabit 乙太網路、DDR3、2 個攝影機模組，以及 7" 電容式觸控螢幕 LCD 等。

使用指南: PDF
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開發板

TMDXSK437X — AM437x 入門套件

AM437x 入門套件提供穩定且經濟實惠的平台，可快速開始評估 Sitara™ Arm® Cortex®-A9 AM437x 處理器（AM4376、AM4378），並加速開發 HMI、工業及網路應用。這是以 ARM Cortex-A9 處理器為基礎的低成本開發平台，並整合多個選項，如雙 GB 乙太網路、DDR3L、攝影機和電容式觸控螢幕 LCD 等。

AM437x 入門套件能以高達 1GHz 的速度，透過可立即生產的硬體與軟體平台加速設計。這款「最佳價值」電路板可協助快速評估處理器功能與隨附 TI 元件，無需在設計硬體時進行臆測，讓資深和資淺的設計師都能專注在如先進繪圖與連線等產品差異化特質。

使用指南: PDF
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開發板

TPS65218EVM-100 — TPS65218 評估模組

TPS65218EVM 是一個已完成組裝的平台，用於評估 TPS65218 電源管理裝置的性能。

使用指南: PDF | HTML
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開發板

BYTES-3P-SITARASOMS — 工作位元組 Sitara SOM

bytes at work develops industrial computing products and services. They offer SOMs based on Sitara Arm® processors.

Learn more about bytes at work at http://www.bytesatwork.io/en. 


從：bytes at work AG
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開發板

COMPU-3P-SITARASOMS — Compulab Sitara SOM

CompuLab is a leading manufacturer of computer-on-module boards and miniature PC systems. CompuLab's products excel with an advanced set of features, outstanding level of integration, high reliability and affordable prices. Annual manufacturing rate of over 100,000 boards and systems positions (...)
從：CompuLab
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開發板

MISTR-3P-POM-AM437X — Mistral 解決方案 AM437x PoM 和應用電路板

The Mistral Solutions AM437x PoM is a low-cost, small form factor, high performance, easy-to-use Product on Module (PoM) built around the TI Sitara AM437x processor. With extensive integration such as quad core PRU-ICSS, 3D acceleration core, dual camera, QSPI-NOR, up to 512KB on-chip memory, dual (...)
從：Mistral Solutions Pvt. Ltd
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開發板

MYIR-3P-SITARASOMS — MYIR Sitara SOM

MYIR offers a series of development kits and system-on-modules based on TI's AM335x Arm® Cortex®-A8 processors to meet customers' different requirements. MYIR also offers a compact single board computer Rico board based on TI's newest AM437x Arm Cortex-A9 solution. MYIR also offers custom (...)
從：MYIR Tech Limited
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開發板

SVT-3P-SITARA-SOMS — 用於 AM437x CPU 的 SVTronics 系統模組

SOM437x is a system-on-module for TI's Sitara™ AM437x processors. It has the AM437x device, DDR3, PMIC (TPS65218), eMMC/NAND FLASH, Gigabit PHY on board and uses a 2.0mm DIP connector. Except for the DDR3 and power pins, all other CPU pins have been connected to the DIP connector. Standard (...)
從：SVTRONICS INC
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開發板

VAR-3P-SITARASOMS — Variscite Sitara SOM

Variscite designs and produces a variety of system on modules and single board computers based TI's Sitara™, OMAP™ and DaVinci™ processors, covering a wide range of products, segments and markets. Variscite provides its customers with a complete development kit supporting Windows (...)
從：Variscite
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軟體開發套件 (SDK)

PROCESSOR-SDK-AM437X — 適用於 AM437x Sitara 處理器的處理器 SDK - 支援 Linux 和 TI-RTOS

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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IDE、配置、編譯器或偵錯程式

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

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作業系統 (OS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
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作業系統 (OS)

MG-3P-NUCLEUS-RTOS — Mentor Graphics Nucleus RTOS

Software driven power management is crucial for battery operated or low power budget embedded systems. Embedded developers can now take advantage of the latest power saving features in popular TI devices with the built-in Power Management Framework in the Nucleus RTOS. Developers specify (...)
從：Mentor Graphics Corporation
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作業系統 (OS)

QNX-3P-NEUTRINO-RTOS — QNX Neutrino RTOS

QNX Neutrino® 即時作業系統 (RTOS) 是一款功能完整且穩固的 RTOS，專為實現適用於汽車、醫療、運輸、軍事和工業嵌入式系統的新一代產品而設計。微核心設計與模組化架構，能讓客戶以低整體擁有成本打造高度最佳化且可靠的系統。
從：QNX
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驅動程式或資料庫

WIND-3P-VXWORKS-LINUX-OS — Wind River 處理器 VxWorks 和 Linux 作業系統

Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)

從：Wind River Systems
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驅動程式或資料庫

WIT-3P-SITARABSP — Witekio Sitara Android 和 Windows 作業系統

Witekio brings expertise on low (OS, driver, firmware) and high level software (application, connectivity, cloud) for TI's OMAP and Sitara AM335x, AM437x, and AM57x platforms. Witekio offers BSPs, drivers, application development/UI/custom drivers for Android, Linux and Windows embedded systems as (...)
從：Witekio
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軟體程式設計工具

SITARA-DDR-CONFIG-TOOL-AM335X — AM335x and AMIC110 EMIF Tools

Sitara™ EMIF 工具是一款軟體工具，提供配置 TI 處理器以存取外部 DDR 記憶體裝置的介面。該工具還最佳化延遲鎖定迴路 (DLL) 設定，以補償電路板佈線偏斜。結果輸出為 EMIF 配置暫存器，可導入以在處理器 SDK、Code Composer Studio 或自訂軟體中使用。  

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軟體程式設計工具

UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash 是 TI 龐大 CCStudio™ 開發生態系統的一部分，是一款用於在 TI 微控制器與無線連線裝置上對晶片內快閃記憶體進行燒錄，以及在 TI 處理器上對板載快閃記憶體進行燒錄的軟體工具。UniFlash 提供圖形化介面與命令行介面，並可在桌面上或雲端中執行。

UniFlash 可從 CCStudio™ 開發人員區上的雲端執行，或在下載後於 Windows®、Linux® 和 macOS® 電腦中使用。

請注意，mmWave、AMx、K2G 和 J7 裝置不支援 macOS。AMx、K2G 和 J7 裝置僅於命令列上支援。

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模擬型號

AM437x BSDL Model (Rev. B)

SPRM635B.ZIP (11 KB) - BSDL 模型
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模擬型號

AM437x IBIS Model (Rev. A)

SPRM636A.ZIP (23511 KB) - IBIS 模型
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計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
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計算工具

POWEREST — 功率估計工具 (PET)

功耗估算工具 (PET) 讓使用者能深入瞭解特定 TI 處理器的功耗情況。本工具允許使用者選擇多種應用場景，不僅能掌握功耗數據，更能理解如何運用進階節能技術進一步降低整體功耗。

AM57x 與 AM437x 處理器專用 PET：

此可下載試算表提供使用者輸入應用所需裝置參數的機制。參數包含 IP 模組活動狀態/負載量、目標電源模式及電源管理使用情境。可設定多重運作條件並為每種狀態配置時間區段。電源估算數據已內嵌於試算表中，所有結果將直接在試算表內自動生成（無需上傳任何資料）。

AM57x 專用 PET：

(...)

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計算工具

SITARA-DDR-CONFIG-TOOL-AM65X-DRA80XM — AM65x/DRA80xM EMIF 工具試算表

Sitara™ EMIF 工具是一款軟體工具，提供配置 TI 處理器以存取外部 DDR 記憶體裝置的介面。該工具還最佳化延遲鎖定迴路 (DLL) 設定，以補償電路板佈線偏斜。結果輸出為 EMIF 配置暫存器，可導入以在處理器 SDK、Code Composer Studio 或自訂軟體中使用。  

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參考設計

TIDA-00750 — 採用 3D 飛時測距 (ToF) 針對需求控制通風進行人數統計的參考設計

採用 3D 飛時測距 (ToF) 參考設計針對需求控制通風進行人數統計，是一款子系統解決方案，使用 TI 的 3D ToF 影像感測器與追蹤和偵測演算法，以高解析度和準確度計算指定區域中的乘員人數。感測器技術以標準的 CMOS 開發而來，讓系統能以更低的系統成本實現極高的整合度。由於 ToF 影像感測器會以三維方式處理視覺資料，因此感測器能偵測人體的確切形狀，並以前所未有的精密度追蹤人員的動作和位置，包括微妙的動作變化。因此，與傳統監控攝影機和視訊分析相比，ToF 攝影機可能會更有效地執行即時人數統計和人數追蹤功能。
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
NFBGA (ZDN) 491 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

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