SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
For each line to be fetched, the DMA engine address generator:
The meaning of the address bits is as follows:
The address extension bits are defined by the programmable parameter DSS0_VID_BA_EXT_0/DSS0_VID_BA_EXT_1 and DSS0_VID_BA_UV_EXT_0/DSS0_VID_BA_UV_EXT_1 registers, optionally used to extend the BA memory addressing to 48-bit addressed external memory space (that is, to extend DISPC address space into 4GB+ space).
The DDR scan pixel addresses are generated by the DMA engine in order to read data from the system memory. The base address defines the start address of the first pixel, and then the address is incremented based on the number of pixels per line, offset between two consecutive lines and number of lines. The DSS0_VID_ROW_INC register allow the access to a frame using 1D bursts (but as a two-dimensional block) by adding a fixed address offset at the end of a line. The ROW_INC can also be used to skip lines from the input frame.
The byte address of each pixel in the frame buffer located in the system memory is determined by:
Pixel address = base_address + x × (bpp/8) + y × (width × (bpp/8) + increment), where:
Since the base address is aligned on pixel size boundary the horizontal resolution is one pixel. In case of YUV422 formats, the resolution is 4 bytes (2 pixels). In case of RGB24 packed format the resolution is 4 pixels. In case of Y frame buffer (YUV-NV12 format) the resolution is one byte. The vertical resolution is one line.
In case of YUV422 format, the number of pixels per line shall be a multiple of 2 pixels and the size of a pixel shall be considered as 2 bytes. In case of YUV420-NV12 or YUV420-NV21 format, the Y buffer shall be considered as an 8-bit frame buffer, and the CbCr shall be considered as a 16-bit frame buffer. The pixel size is 1 byte and 2 bytes, respectively for Y and CbCr.
For YUV420-NV12 or YUV420-NV21 format, the pixel values are defined in two separate buffers (Y and UV buffers). The first buffer consists of Y values (8 bits for each Y sample). The second buffer consists of CbCr values (16 bits for each pair of CbCr samples). The base address of the Y and UV buffers are as defined earlier in this section.
In case of interlaced mode, DSS0_VID_BA_0 and DSS0_VID_BA_UV_0 registers define the base address of the even field, and DSS0_VID_BA_1 and DSS0_VID_BA_UV_1 registers define the base address of the odd field.
The number of bytes to skip between pixels and between lines are defined using DSS0_VID_PIXEL_INC and DSS0_VID_ROW_INC registers, respectively. They define the values to be used for the Y buffer. For the CbCr buffer, the DSS0_VID_ROW_INC_UV register define the values.
Table 12-425 summarizes the register settings for a simple access of a picture in the system memory.
Video Pipeline Registers | Value |
---|---|
DSS0_VID_BA_0(1) and DSS0_VID_BA_1(2) | The physical base address (PBA) of image in the memory for all formats and Y buffer. |
DSS0_VID_BA_EXT_0 and DSS0_VID_BA_EXT_1 | Address extension bits of PBA for all formats and Y buffer. |
DSS0_VID_BA_UV_0(1) and DSS0_VID_BA_UV_1(2) | The physical base address (PBA) of UV buffers image in the memory. |
DSS0_VID_BA_UV_EXT_0 and DSS0_VID_BA_UV_EXT_1 | Address extension bits of PBA for UV buffers. |
DSS0_VID_PIXEL_INC | 1 or other in pixel incremental value. |
DSS0_VID_ROW_INC | 1 or other in row incremental value. Used for Y buffer. |
DSS0_VID_ROW_INC_UV | 1 or other in row incremental value. Used for UV buffer. |
An interconnect request (128 bits) corresponds to one or several pixels, depending on the bits per pixel. Therefore, the DMA engine determines the appropriate burst sequence to optimize the fetching of each new line. The DMA engine must prevent a single burst from crossing two lines. The DMA engine supports only 1D burst. 1D burst is used, if the fetch data is linear in memory. The size of the burst can be one of the following values: 1x128-bit, 2x128-bit, 4x128-bit, or 8x128-bit. Because the burst size must be aligned to the burst boundary, in case of misalignment, the DMA engine may issue one or more smaller burst requests.