SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:2 | addr | r/w | 0x0 |
This field contains the upper 30 bits of the 32-bit interrupt vector address (the address must be 32-bit aligned) of an interrupt to be used if an uncorrectable double-bit error (DED) is detected in any of the interrupt vector addresses. If there is a DED, both the IRQ Vector Address (Base Address + 0x18) and FIQ Vector Address (Base Address + 0x1C) registers (along with the VECADDR output) will be populated with the value in this field instead of their normal vector. See section Section 7.9.7.3.7, Priority Interrupt / Nested Interrupts. Safety on how to handle interrupts when there has been a DED
|
1:0 | reserved | r/o | 0x0 | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned. |