SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Some of the RTI features described in this section may not be supported on this family of devices. For more information, see RTI Not Supported Features.
Once the system enters debug mode, the behavior of the RTI depends on the RTI_RTIGCTRL[15] COS bit. If the bit is cleared and debug mode is active, all counters will stop operation. If the bit is set to one, all counters will be clocked normally and the RTI will work like in normal mode.
The DWD counter will not decrement in debug mode and will hold its current value, regardless of the RTI_RTIGCTRL[15] COS bit.
The user must not service the watchdog while in debug mode.