SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Table 5-20 shows configuration pins assignment to functions when boot mode is the I2C mode.
BOOTMODE Pins | Field | Value | Description |
---|---|---|---|
9 | Bus reset | 0 | Hung bus reset attempt after 1 ms |
1 | No hung bus reset attempted | ||
7 | Address | 0 | EEPROM's address is 0x50 |
1 | EEPROM's address is 0x51 |
The I2C bus is considered inactive if the data line is low and clock remains high for the specified timeout time. Recovery consists of driving the clock a stop condition is detected. A stop condition is a transition on the data line from 0 to 1 while the clock line is high. If the clock line is stuck low there is no way to take control of the bus.
Table 5-21 summarizes the I2C pin configuration done by ROM code for I2C boot device.
Device Pin | Module Signal | Pull Enable | Pull Direction | Driver Index | Rx En/Dis | Pinmux Sel | Pad Configuration Register |
---|---|---|---|---|---|---|---|
I2C0_SCL | I2C0_SCL | Disable | NA | 0 | Enable | 0 | PADCONFIG120 |
I2C0_SDA | I2C0_SDA | Disable | NA | 0 | Enable | 0 | PADCONFIG121 |