SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The peripheral receive mode is programmable (set the MCSPI_CH0CONF[13-12] TRM bit field to 0x0).
In peripheral transmit-and-receive mode, the MCSPI_TX0 register must be loaded before MCSPI is selected by an external MCSPI controller device.
After a channel is enabled, transmission and reception proceed with interrupt and DMA request events.
The MCSPI_TX0 register content is always loaded in the shift register whether it is updated or not. The event TX0_UNDERFLOW is activated accordingly and does not prevent transmission.
When the MCSPI word transfer completes (the MCSPI_CH0STAT[2] EOT bit is set to 1), the received data is transferred to the channel receive register.
To use MCSPI as a peripheral transmit-only device, the RX0_FULL and RX0_OVERFLOW interrupts and DMA read requests must be disabled due to the state of the MCSPI_RX0 register (see Section 12.1.3.4.7.2, Interrupt Events in Peripheral Mode).