The following features are not supported on
this family of devices:
- DDR3, DDR3L, DDR3U, and LPDDR4x
Devices
- Two independent 16-bit channels for
LPDDR4
- DIMMS
- Data bus obfuscation / data
encryption
- Fail-safe reset I/O to maintain reset
state during SoC power OFF
- Automatic periodic scrubbing of SDRAM
for ECC
- Coherence of transactions arriving
across the RT and NRT bus interfaces
- Maximum of 17 row bits are supported for LPDDR4. LPDDR4 with 18 row bits are not
supported
- LPDDR4 devices with byte mode die configurations
- The ECC engine of the DDR controller
- 1T command timing (only 2T timing is
supported)