Integrated in MAIN domain: Two high-speed differential
interfaces implemented with the
Serializer/Deserializer (SERDES) Multi-protocol Multi-link module with
the following main blocks:
- Quad lane PHY with common
module for peripheral and Tx clocking handling
- PIPE Rev 4.2 Interface
- Physical coding sub-block for data translation from/to the
parallel interface, as well as data encoding/decoding and symbol
alignment
- MUX module for device interfaces multiplexing into a single
SERDES lane (Tx and Rx)
- A wrapper for sending control and reporting status signals
from the SerDes and muxes