DIG_ON domain MMR Write Rules
- UnLock DIG_CORE (Wrt Kick0 and Wrt Kick1)
- Write all MMRs in the same address order has MMRs from low to high
- For example . Wrt Scratch Storage 0 through Scratch Storage 7
- HOST PROCESSOR poles until SYNCPEND.WR_PEND is 0
- Max completion is 60 uSeconds when GENRAL_CTL. 32K_OSC_DEP_EN is
set
- Max completion is 10 uSeconds when GENRAL_CTL. 32K_OSC_DEP_EN is
clr
- HOST PROCESSOR is not allowed to perform new write without waiting for
clearing of SYNCPEND.WR_PEND
After every new power up of the SOC
- Unlock RTC by writing correct pattern in Kick0 and Kick1
- Keep it UnLock
- HOST PROCESSOR can verify that 32Khz_osc_clk is toggling by reading
SYNCPEND. 32K_CLK_OBS
- Should not be required, since the 32Khz_osc_clk will always will be
active
- HOST PROCESSOR sets GENRAL_CTL.32K_OSC_DEP_EN
- Wait for 60 uSec
- Initialize ALL RTC MMRs in the DIG_ON domain in the same order as the
address map
- The RTCs MMRs do not have a reset state in general, only a few required MMRs
bits have one.
- HOST PROCESSOR must initialize all bits of the MMRs which reside in DIG_ON
domain
- Ie wrt <value>@0x00, <value>@0x04, <value>@0x08
….<value>@0x50
- HOST PROCESSOR poll SYNCPEND.WR_PEND until null
- This means all
DIG_ON domain MMRs have been written to
RTC is now in an operational state and fully configured.
32768 MHz time adjustment
- HOST PROCESSOR UnLock RTC(required for writes to DIG_ON domain)
- HOST PROCESSOR can readSUB_S_CNT(1st), S_CNT_LSW(2nd), S_CNT_MSW(3rd)
- HOST PROCESSOR can write new time by writing to SUB_S_CNT(1st),
S_CNT_LSW(2nd), S_CNT_MSW(3rd)
- HOST PROCESSOR ReLock RTC(writing 0x0000_0000 to KICK1)
- HOST PROCESSOR poll SYNCPEND.WR_PEND until null
32768 MHz time drift adjustment
- HOST PROCESSOR UnLocks RTC(required for writes to DIG_ON domain)
- HOST PROCESSOR can readSUB_S_CNT(1st), S_CNT_LSW(2nd), S_CNT_MSW(3rd)
- SW determines drift rate
- HOST PROCESSOR updates or enables drift adjustment by HOST PROCESSOR write
new COMP_LSB and COMP_MSB
- HOST PROCESSOR ReLock RTC(writing 0x0000_0000 to KICK1)
- HOST PROCESSOR poll SYNCPEND.WR_PEND until null