The PDMA1 - UART module supports the following
features:
- Implements CPPI 5.0 compliant third-party Unified
Transfer Controller (UTC)
- Provides
1 memory write access
unit(s)
- Each unit supports write bursts up to 64 bytes
(on selected channel types)
- Write Unit 0
- Provides
a 32-bit wide VBUSP write-only
initiator
interface for peripheral
accesses
- Provides 1 memory read access unit(s)
- Supports 1 outstanding read per interface
(VBUSP)
- Supports read burst up to 64 bytes (on selected
channel types)
- Read Unit 0
- Provides
a 32-bit wide VBUSP
read-only
initiator
interface for peripheral
accesses
- Supports up to 7 simultaneous destination (Tx)
channels
- Supports negative credit monitoring on Tx
channels
- Supports up to 7 simultaneous source (Rx)
channels
- Supports Static Transfer Requests Only
- Supports X-Y, MCAN, and AASRC transter modes (as
per configuration)
- Provides per-channel buffering:
- Provides 8 128-bit word deep data FIFO for each
destination channel
- Provides 8 128-bit word deep data FIFO for each
source channel
- Provides 128-bit wide PSI-L compliant data
interface
to and from
DMSS
endpoints and remote peripherals