SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Descriptors are so named because their primary function is to describe other data structures.
The PKTDMA architecture provides for 2 basic types of descriptors whose characteristics are shown in PKTDMA Descriptor Types and Attributes.
Descriptor Type | Includes Valid Packet Info | Provided # of Slots to Link In External Data | Provides Local Protocol Specific Storage | Provides Slot to Link Additional Descriptors Within Same Packet | Description |
---|---|---|---|---|---|
Host Packet Descriptor | ✓ | 1 | ✓ | ✓ | Used to describe packet and SOP buffer in applications that require Host OS compatible data structures (i.e. applications where the descriptors and buffers cannot be managed independently but must instead be pre-linked by the Host software). These applications inherently require a separate descriptor for each buffer. |
Host Buffer Descriptor | 1 | ✓ | Used to describe non-SOP buffers in applications that require Host OS compatible data structures |
As the above table shows, the Host Packet Descriptor provides packet level information that is useful to both the ports and the Host in order to properly process the packet. These descriptors are referred to as Packet Descriptors and will always appear as the first descriptor within a packet.
The PKTDMA allows descriptors to be allocated on 16-byte address boundaries. This is intended to allow for better memory utilization by allowing on-chip descriptors which are not a power of 2 in length to be packed into arrays with little wasted memory space.
Even though descriptors and buffers may be allocated on any 16-byte alignment, careful consideration of the alignment effects should be made based on the storage location and any cache related affects that may exist. If data structures are placed in off-chip SDRAM the burst size and alignment restrictions of the memory devices must be considered in order to avoid performance issues related to continually fetching mis-aligned blocks. In this case, the memory efficiency can be reduced to 50% because 2 memory bank lines are read for every line sized data fetch. Similarly, placing more than one descriptor or buffer object within a single cache line can cause the adjacent object to become corrupted during cache line writeback operations.
Software/application specific control information may be added to the end of any of the packet descriptor types using as many extra words as necessary but the above alignment rules still apply.
The Block Copy DMA architecture provides a single descriptor type whose characteristics are shown in Block Copy DMA Descriptor Types and Attributes.
Descriptor Type | Includes Valid Packet Info | Provided # of Slots to Link In External Data | Provides Local Protocol Specific Storage | Provides Slot to Link Additional Descriptors Within Same Packet | Description |
---|---|---|---|---|---|
Transfer Request Packet Descriptor | 0 | Used to feed transfer request sequences to the BCDMA |