SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Whenever an interrupt input goes high, if that interrupt is mapped as an FIQ (Group N Interrupt Map Register (Base Address + 0x200 + N*0x20 + 0x18)) and is enabled (Group N Interrupt Enabled Set Register (Base Address + 0x200 + N*0x20 + 0x08)), and its priority is not masked (4.1.12 FIQ Priority Mask Register (Base Address + 0x2C)), and it is not masked because of nested interrupt priority masking (2.2.5 Priority Interrupt / Nested Interrupts), then it will cause an FIQ to assert.