Setup DMA channel 1 with the starting address from which the pre-determined CRC
values are stored. Setup the destination address
to the MCRC64_0_CRC_REGL1. Put the source
address at post increment addressing mode and put
the destination address at constant addressing
mode. Use hardware DMA request for channel 1 to
trigger a frame transfer.
Setup DMA channel 2 with the source address from which the contents of memory
to be verified. Setup the destination address to
the MCRC64_0_PSA_SIGREGL1. Program the
element transfer count to 128 and the frame
transfer count to 2048. Program the read and write
element size to 64 bits. Put the source address at
post increment addressing mode and put the
destination address at constant address mode. Use
hardware DMA request for channel 2 to trigger an
entire block transfer.