SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The DIG_CORE block is on the CORE power domain which will power OFF/ON when the SOC powers OFF/ON. It contains, CORE IF logic, Shadow MMRs and MMR Sync logic.
The MMR Sync logic has 2 modes of operation
Refresh/Sync after Core Reset Deassertion
After every Core Reset event, the MMR Sync logic we refresh ALL Shadow MMRs by copying the contents of ON MMRs into the Shadow MMRs.
Core Reset DeAssertion
The internal state machine Reads All MMRs in linear order
The internal state machine Sets SYNCPEND.RD_DONE bit when the copy from the ON domain is completed. The host processor needs to wait for this status bit assertion before it reads the other MMRs
Sync after HOST PROCESSOR Updates Shadow MMRs
host processor UNLOCK
host processor Wrts to MMRs
The ON domain MMRs will get updated after a finite delay
The internal state machine sets SYNCPEND.WR_DONE bit. This needs to get cleared before the next HOST PROCESSOR Updates Shadow MMRs