SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The procedure in Table 12-277 configures the transmit frame synchronization generator of the MCASP module.
The frame synchronization signal is always rising-edge active and always has a single-bit width.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Select 384-slot size block. | MCASP_AFSXCTL[15-7] XMOD | 0x180 |
Select internally-generated transmit frame sync. | MCASP_AFSXCTL[1] FSXM | 0x1 |