SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The VIM can have up to 1024 interrupt inputs, build-time configurable by multiples of 32 (num_interrupts parameter). Each interrupt can be either a level or a pulse (both active high).
Level interrupts are synchronized to the VIM clock. This synchronized value is captured in to a flop.
Pulse interrupts use rising edge detection. Each input has its own edge detection circuit. It is recommended that if pulses are pipelined between the source and the VIM, that the pipe stage replicates the pipe flop and ORs the output in order to protect against transient errors in the pipeline flop. Once an edge has been detected, the raw status is set.
There is no minimum pulse width, as true edge detection is used. The input signal should, however, be glitch free.