SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The debug/state registers are supplied to give software applications additional information about the PDMA than they would need in regular operation, but which may be useful in debug situations. The registers appear on the PSI-L bus, near the static TR registers. For transmit, they are defined as in Table 11-85.
Name | PSIL Addr | Field | Description |
---|---|---|---|
Y | 0x402 | 15:0 | This field holds the current Y count. In X-Y FIFO mode, this is the number of X sized samples yet to write to the peripheral for the DMA event being serviced. In MCAN mode, this field holds the next write offset to use when writing to the CAN TX buffer. |
InEvent | 0x403 | 31 | When set, the PDMA is in the middle of processing a FIFO event. |
Flush | 0x403 | 30 | When set, the PDMA is processing in a flushing state, where it runs without waiting for DMA requests and without writing data to the peripheral. It is only operating its internal state machine to allow internal data pipes to drain properly. |
Pause | 0x403 | 29 | When set, the PDMA waiting in a paused state. This bit will clear when data starts flowing again from the UDMA-P. |
Data | 0x403 | 28 | When set, there is a non-zero amount of data still waiting to be written to the peripheral. |
XData | 0x403 | 27 | When set, there is enough data still waiting to be written to the peripheral to start servicing a peripheral DMA event. |
State | 0x403 | 23:20 | This code reflects the current state of the PDMA channel, and is specific to the current implementation. |
EventCnt | 0x403 | 19:16 | This field holds the number of backlogged DMA events yet to be serviced. |