SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
This section identifies the requirements for initializing the surrounding modules when the MCASP module is used for the first time after a device reset. This initialization of surrounding modules is based on the integration and environment of the MCASP (for more information, see Module Integration, and MCASP Environment ).
Table 12-274 describes the global initialization of surrounding modules.
Surrounding Modules | Comments |
---|---|
LPSC3 | Module reset must be enabled. For more information about the module configuration, see Reset. |
PLLCTRL0 | PLLCTRL0 configuration must be done to enable the clocks to the MCASP modules, see Clocking. |
PLL4 | PLL4 configuration must be done to enable the clocks to the MCASP modules, see Clocking. |
PLL2 | PLL2 configuration must be done to enable the clocks to the MCASP modules, see Clocking. |
ATL | ATL configuration must be done to enable the clocks to the MCASP modules, see Audio Tracking Logic (ATL). |
COMPUTE_CLUSTER0 | Device INTCs must be configured to enable the interrupt request generation. For information about enabling COMPUTE_CLUSTER0 interrupts, see Interrupts. |
MAIN2MCU_LVL_INTRTR0 | Device INTCs must be configured to enable the interrupt request generation. For information about enabling MAIN2MCU_LVL_INTRTR0 interrupts, see Interrupts. |
R5FSS0_CORE0/1 | Device INTCs must be configured to enable the interrupt request generation. For information about enabling R5FSS0_CORE0/1 interrupts, see Interrupts. |
PDMA0_MCASP_G0 | PDMA0_MCASP_G0 controllers configuration must be done to enable the module PDMA0_MCASP_G0 channel request, see PDMA Controller. |
Interconnects | For information about the CBASS0 interconnects configuration, see System Interconnect. |
NAVSS configuration (UMDA channel set-up) must be done in order to move data from/to MCASP via the PDMA Controller. For more information, see Navigator Subsystem (NAVSS).
The COMPUTE_CLUSTER0, MAIN2MCU_LVL_INTRTR0, R5FSS0_CORE0/1, and the PDMA0_MCASP_G0 configurations are required when the interrupt and DMA-based communication modes are used. Further initialization of the selected interrupt and DMA controllers of the host CPU must be done for full functionality of the MCASP DMA and interrupt lines.