SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The 24-bit RGB input source data (either non-dithered or dithered to 24-bit) coming from the DSS DISPC video port is expected to have the components mapping shown in Table 12-440. The DSS0_VP_DSS_OLDI_CFG[8] MSB register bit must be set for 24-bit input.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
R[7:0] | G[7:0] | B[7:0] |
Both 18-bit and 24-bit LVDS output mappings are supported with this 24-bit input format. For 18-bit LVDS output mapping however, the 6 MSB bits of each component are mapped to the output as shown in Table 12-441. OLDITX does not support dithering to reduce 24-bit RGB input to 18-bit RGB LVDS output. If dithering is required, then DSS DISPC must perform the dithering and send the data to OLDITX as an 18-bit panel data as shown in Section 12.9.1.4.2.4.2, OLDITX 18-bit RGB Input.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
R[5:0] | Unused | G[5:0] | Unused | B[5:0] | Unused |