SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The video pipelines support various types of memory formats, as listed in Table 12-427.
For BITMAP formats the nibble mode (pixels in each byte are packed in reverse order) can be enabled by setting the DSS0_VID_ATTRIBUTES[10] NIBBLEMODE register bit to 0x1.
The pixel data format can be selected by loading the corresponding value from Table 12-427 in the DSS0_VID_ATTRIBUTES [6-1] FORMAT register field.
FORMAT Register Field Value | Pixel Format(4) | Component Bit Depth | |
---|---|---|---|
Alpha | Alpha-X | ||
0x00 | 0x20 | ARGB16-4444 | 4 |
0x01 | 0x21 | ABGR16-4444 | 4 |
0x02 | 0x22 | RGBA16-4444 | 4 |
0x03 | NA | RGB16-565 | 5(R,B), 6(G) |
0x04 | NA | BGR16-565 | 5(R,B), 6(G) |
0x05 | 0x25 | ARGB16-1555 | 1(A), 5(R,G,B) |
0x06 | 0x26 | ABGR16-1555 | 1(A), 5(R,G,B) |
0x07 | 0x27 | ARGB32-8888 | 8 |
0x08 | 0x28 | ABGR32-8888 | 8 |
0x09 | 0x29 | RGBA32-8888 | 8 |
0x0A | 0x2A | BGRA32-8888 | 8 |
0x0B | NA | RGB24-888 | 8 |
0x0C | NA | BGR24-888 | 8 |
0x0E | 0x2E | ARGB32-2101010 | 2(A),10(R,G,B) |
0x0F | 0x2F | ABGR32-2101010 | 2(A),10(R,G,B) |
0x10 | 0x30 | ARGB64-16161616 | 16 |
0x11 | 0x31 | RGBA64-16161616 | 16 |
0x12 | NA | BITMAP1 | 1 |
0x13 | NA | BITMPA2 | 2 |
0x14 | NA | BITMAP4 | 4 |
0x15 | NA | BITMAP8 | 8 |
0x16 | NA | RGB565A8 (1) | 5(R,B), 6(G), separate 8(A) |
0x17 | NA | BGR565A8 (1) | 5(R,B), 6(G), separate 8(A) |
Packed | Planar | Pixel Format | Component Bit Depth |
0x3E | NA | YUV422-YUV2 | 8/10/12 (3) |
0x3F | NA | YUV422-UYVY | 8/10/12 (3) |
NA | 0x3D | YUV420-NV12 | 8/10/12 (3) |
NA | See (2) | YUV420-NV21 | 8/10/12 |
Figure 12-468 shows the pixel data memory organization for the bitmap pixel formats.
Figure 12-469 and Figure 12-470 show the pixel data memory organization for the RGB 16-bit pixel formats.
Figure 12-471 shows the pixel data memory organization for the RGB 24-bit pixel formats.
Figure 12-472 and Figure 12-473 show the pixel data memory organization for the RGB 32-bit pixel formats.
Figure 12-474 shows the pixel data memory organization for the RGB 64-bit pixel formats.
Figure 12-475 and Figure 12-476 show the pixel data memory organization for the YUV 8-bit pixel formats, together with some specific register settings.
Figure 12-477 shows the pixel data memory organization for the YUV 10-bit pixel formats, together with some specific register settings.
Figure 12-478 and Figure 12-479 show the pixel data memory organization for the YUV 12-bit pixel formats, together with some specific register settings.
Figure 12-480 through Figure 12-482 show the pixel data memory organization for the YUV 10-bit/12-bit unpacked pixel formats in 16-bit container, together with some specific register settings.