SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
OLDITX receives one pixel clock, OLDI_FWD_P_CLK. The pixel clock rate is 1/7 of serial clock rate in single-link mode and 2/7 of serial clock rate in dual-link mode.
OLDITX receives one serial clock (OLDI_PLL_CLK) to perform 7-to-1 serialization. OLDI_PLL_CLK is 3.5x or 7x OLDI_FWD_P_CLK frequency, where 25MHz < OLDI_FWD_P_CLK (freq) < 170MHz.
For more details on OLDITX clocks, see DSS Integration.