SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
By default, the ACLKX and AHCLKX clocks are generated only from the MCASP internal clock source.
The procedure in Table 12-278 configures the transmit clock generator of the MCASP module.
Step | Register/Bit Field/Programming Model | Value |
---|---|---|
Set the divisor for the internally generated high frequency clock– AHCLKX. | MCASP_AHCLKXCTL[11-0] HCLKXDIV | 0x- |
Set he divisor for the internally generated transmission clock– ACLKX. | MCASP_ACLKXCTL[4-0] CLKXDIV | 0x- |
Configure the transmit clock failure detect logic. | See Section 12.5.2.4.15.6.1, Clock Failure Check Startup. |