SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The memory that holds the interrupt vector for each interrupt is protected by SECDED ECC. Single-bit errors are corrected and written back. Double-bit errors are not corrected. If a double-bit error occurs while trying to load a vector, then the DED Vector Address (Base Address + 0x30) is used instead for the coreN_IRQADDRV, IRQ Vector Address (Base Address + 0x18), and FIQ Vector Address (Base Address + 0x1C). The DED Vector Address should point to an ISR that handles the fact that there was an uncorrectable error in the interrupt handling. Some possible remediating actions would be to:
It is up to the user and the application to determine the appropriate action.
An interrupt that has an uncorrectable vector error and thus uses the DED Vector, will still have the priority of the original interrupt (i.e. for masking purposes). This makes it possible for a higher priority interrupt to supercede the handling of the error.
Control and reporting are done by an external ECC aggregator through sVbus ports.