SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
This section describes the DPHY_RX application fields from an environment point of view (external connections).
Table 12-302 describes the external signals of the DPHY_RX.
Device Level Signal | I/O | Description |
---|---|---|
DPHY_RXi(1) | ||
CSIi(1)_RXN0 | I | Lane 0 Receive Differential Data (Negative) |
CSIi(1)_RXP0 | I | Lane 0 Receive Differential Data (Positive) |
CSIi(1)_RXN1 | I | Lane 1 Receive Differential Data (Negative) |
CSIi(1)_RXP1 | I | Lane 1 Receive Differential Data (Positive) |
CSIi(1)_RXN2 | I | Lane 2 Receive Differential Data (Negative) |
CSIi(1)_RXP2 | I | Lane 2 Receive Differential Data (Positive) |
CSIi(1)_RXN3 | I | Lane 3 Receive Differential Data (Negative) |
CSIi(1)_RXP3 | I | Lane 3 Receive Differential Data (Positive) |
CSIi(1)_RXCLKN | I | Lane 3 Receive Differential Clock (Negative) |
CSIi(1)_RXCLKP | I | Lane 3 Receive Differential Clock (Positive) |
CSIi(1)_RXRCALIB | A | Pin for external calibration resistor. An external resistor must be connected between this pin and package ground. Refer to the device-specific Datasheet for a recommended resistor value. |
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.