SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
At initialization, the following tasks should be performed:
Note that the Interrupt Q Vector Register (Base Address + 0x2000 + Q*0x4) for each interrupt that will be enabled must be written before the interrupt is enabled, even if software is not going to use the vector. Whenever an interrupt is prioritized, the RAM location for the interrupt is read, and if that location is un-initialized, an ECC error will be reported. If the vectors aren’t being used, then the RAM can be initialized by writing 0x0 to every location.