MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_0 |
GICSS0_spi_IN_108 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_0 |
WKUP_R5FSS0_CORE0_intr_IN_240 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_240 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_0 |
C7X256V0_CLEC_gic_spi_IN_108 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_0 |
C7X256V1_CLEC_gic_spi_IN_108 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_0 |
TIFS0_nvic_IN_50 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_0 |
HSM0_nvic_IN_50 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_1 |
GICSS0_spi_IN_108 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_1 |
WKUP_R5FSS0_CORE0_intr_IN_240 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_1 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_240 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_1 |
C7X256V0_CLEC_gic_spi_IN_108 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_1 |
C7X256V1_CLEC_gic_spi_IN_108 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_1 |
TIFS0_nvic_IN_50 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_1 |
HSM0_nvic_IN_50 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_2 |
GICSS0_spi_IN_108 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_2 |
WKUP_R5FSS0_CORE0_intr_IN_240 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_2 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_240 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_2 |
C7X256V0_CLEC_gic_spi_IN_108 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_2 |
C7X256V1_CLEC_gic_spi_IN_108 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_2 |
TIFS0_nvic_IN_50 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_2 |
HSM0_nvic_IN_50 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_3 |
GICSS0_spi_IN_108 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_3 |
WKUP_R5FSS0_CORE0_intr_IN_240 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_3 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_240 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_3 |
C7X256V0_CLEC_gic_spi_IN_108 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_3 |
C7X256V1_CLEC_gic_spi_IN_108 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_3 |
TIFS0_nvic_IN_50 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_0 |
MAILBOX0_MAILBOX_CLUSTER_0_mailbox_cluster_pend_3 |
HSM0_nvic_IN_50 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_0 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_0 |
GICSS0_spi_IN_109 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_0 |
WKUP_R5FSS0_CORE0_intr_IN_241 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_241 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_0 |
C7X256V0_CLEC_gic_spi_IN_109 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_0 |
C7X256V1_CLEC_gic_spi_IN_109 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_0 |
TIFS0_nvic_IN_55 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_0 |
HSM0_nvic_IN_55 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_1 |
GICSS0_spi_IN_109 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_1 |
WKUP_R5FSS0_CORE0_intr_IN_241 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_1 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_241 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_1 |
C7X256V0_CLEC_gic_spi_IN_109 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_1 |
C7X256V1_CLEC_gic_spi_IN_109 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_1 |
TIFS0_nvic_IN_55 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_1 |
HSM0_nvic_IN_55 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_2 |
GICSS0_spi_IN_109 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_2 |
WKUP_R5FSS0_CORE0_intr_IN_241 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_2 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_241 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_2 |
C7X256V0_CLEC_gic_spi_IN_109 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_2 |
C7X256V1_CLEC_gic_spi_IN_109 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_2 |
TIFS0_nvic_IN_55 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_2 |
HSM0_nvic_IN_55 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_3 |
GICSS0_spi_IN_109 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_3 |
WKUP_R5FSS0_CORE0_intr_IN_241 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_3 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_241 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_3 |
C7X256V0_CLEC_gic_spi_IN_109 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_3 |
C7X256V1_CLEC_gic_spi_IN_109 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_3 |
TIFS0_nvic_IN_55 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_1 |
MAILBOX0_MAILBOX_CLUSTER_1_mailbox_cluster_pend_3 |
HSM0_nvic_IN_55 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_1 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
GICSS0_spi_IN_140 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
R5FSS0_CORE0_intr_IN_115 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
WKUP_R5FSS0_CORE0_intr_IN_242 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_242 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
C7X256V0_CLEC_gic_spi_IN_140 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
C7X256V0_CLEC_soc_events_in_IN_6 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
C7X256V1_CLEC_gic_spi_IN_140 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
C7X256V1_CLEC_soc_events_in_IN_6 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
TIFS0_nvic_IN_56 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_0 |
HSM0_nvic_IN_56 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
GICSS0_spi_IN_140 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
R5FSS0_CORE0_intr_IN_115 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
WKUP_R5FSS0_CORE0_intr_IN_242 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_242 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
C7X256V0_CLEC_gic_spi_IN_140 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
C7X256V0_CLEC_soc_events_in_IN_6 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
C7X256V1_CLEC_gic_spi_IN_140 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
C7X256V1_CLEC_soc_events_in_IN_6 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
TIFS0_nvic_IN_56 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_1 |
HSM0_nvic_IN_56 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
GICSS0_spi_IN_140 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
R5FSS0_CORE0_intr_IN_115 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
WKUP_R5FSS0_CORE0_intr_IN_242 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_242 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
C7X256V0_CLEC_gic_spi_IN_140 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
C7X256V0_CLEC_soc_events_in_IN_6 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
C7X256V1_CLEC_gic_spi_IN_140 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
C7X256V1_CLEC_soc_events_in_IN_6 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
TIFS0_nvic_IN_56 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_2 |
HSM0_nvic_IN_56 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
GICSS0_spi_IN_140 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
R5FSS0_CORE0_intr_IN_115 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
WKUP_R5FSS0_CORE0_intr_IN_242 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_242 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
C7X256V0_CLEC_gic_spi_IN_140 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
C7X256V0_CLEC_soc_events_in_IN_6 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
C7X256V1_CLEC_gic_spi_IN_140 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
C7X256V1_CLEC_soc_events_in_IN_6 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
TIFS0_nvic_IN_56 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_2 |
MAILBOX0_MAILBOX_CLUSTER_2_mailbox_cluster_pend_3 |
HSM0_nvic_IN_56 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_2 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
GICSS0_spi_IN_141 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
R5FSS0_CORE0_intr_IN_116 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
WKUP_R5FSS0_CORE0_intr_IN_243 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_243 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
C7X256V0_CLEC_gic_spi_IN_141 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
C7X256V0_CLEC_soc_events_in_IN_7 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
C7X256V1_CLEC_gic_spi_IN_141 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
C7X256V1_CLEC_soc_events_in_IN_7 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
TIFS0_nvic_IN_57 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_0 |
HSM0_nvic_IN_57 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
GICSS0_spi_IN_141 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
R5FSS0_CORE0_intr_IN_116 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
WKUP_R5FSS0_CORE0_intr_IN_243 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_243 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
C7X256V0_CLEC_gic_spi_IN_141 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
C7X256V0_CLEC_soc_events_in_IN_7 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
C7X256V1_CLEC_gic_spi_IN_141 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
C7X256V1_CLEC_soc_events_in_IN_7 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
TIFS0_nvic_IN_57 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_1 |
HSM0_nvic_IN_57 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
GICSS0_spi_IN_141 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
R5FSS0_CORE0_intr_IN_116 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
WKUP_R5FSS0_CORE0_intr_IN_243 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_243 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
C7X256V0_CLEC_gic_spi_IN_141 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
C7X256V0_CLEC_soc_events_in_IN_7 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
C7X256V1_CLEC_gic_spi_IN_141 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
C7X256V1_CLEC_soc_events_in_IN_7 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
TIFS0_nvic_IN_57 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_2 |
HSM0_nvic_IN_57 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
GICSS0_spi_IN_141 |
GICSS0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
R5FSS0_CORE0_intr_IN_116 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
WKUP_R5FSS0_CORE0_intr_IN_243 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_243 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
C7X256V0_CLEC_gic_spi_IN_141 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
C7X256V0_CLEC_soc_events_in_IN_7 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
C7X256V1_CLEC_gic_spi_IN_141 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
C7X256V1_CLEC_soc_events_in_IN_7 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
TIFS0_nvic_IN_57 |
TIFS0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_3 |
MAILBOX0_MAILBOX_CLUSTER_3_mailbox_cluster_pend_3 |
HSM0_nvic_IN_57 |
HSM0 |
MAILBOX0_MAILBOX_CLUSTER_3 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_0 |
R5FSS0_CORE0_intr_IN_240 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_0 |
WKUP_R5FSS0_CORE0_intr_IN_115 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_0 |
C7X256V0_CLEC_soc_events_in_IN_8 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_0 |
C7X256V1_CLEC_soc_events_in_IN_8 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_1 |
R5FSS0_CORE0_intr_IN_240 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_1 |
WKUP_R5FSS0_CORE0_intr_IN_115 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_1 |
C7X256V0_CLEC_soc_events_in_IN_8 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_1 |
C7X256V1_CLEC_soc_events_in_IN_8 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_2 |
R5FSS0_CORE0_intr_IN_240 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_2 |
WKUP_R5FSS0_CORE0_intr_IN_115 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_2 |
C7X256V0_CLEC_soc_events_in_IN_8 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_2 |
C7X256V1_CLEC_soc_events_in_IN_8 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_3 |
R5FSS0_CORE0_intr_IN_240 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_3 |
WKUP_R5FSS0_CORE0_intr_IN_115 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_3 |
C7X256V0_CLEC_soc_events_in_IN_8 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_4 |
MAILBOX0_MAILBOX_CLUSTER_4_mailbox_cluster_pend_3 |
C7X256V1_CLEC_soc_events_in_IN_8 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_4 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_0 |
R5FSS0_CORE0_intr_IN_241 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_0 |
WKUP_R5FSS0_CORE0_intr_IN_116 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_0 |
C7X256V0_CLEC_soc_events_in_IN_9 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_0 |
C7X256V1_CLEC_soc_events_in_IN_9 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_1 |
R5FSS0_CORE0_intr_IN_241 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_1 |
WKUP_R5FSS0_CORE0_intr_IN_116 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_1 |
C7X256V0_CLEC_soc_events_in_IN_9 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_1 |
C7X256V1_CLEC_soc_events_in_IN_9 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_2 |
R5FSS0_CORE0_intr_IN_241 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_2 |
WKUP_R5FSS0_CORE0_intr_IN_116 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_2 |
C7X256V0_CLEC_soc_events_in_IN_9 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_2 |
C7X256V1_CLEC_soc_events_in_IN_9 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_3 |
R5FSS0_CORE0_intr_IN_241 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_3 |
WKUP_R5FSS0_CORE0_intr_IN_116 |
WKUP_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_3 |
C7X256V0_CLEC_soc_events_in_IN_9 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_5 |
MAILBOX0_MAILBOX_CLUSTER_5_mailbox_cluster_pend_3 |
C7X256V1_CLEC_soc_events_in_IN_9 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_5 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_0 |
R5FSS0_CORE0_intr_IN_242 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_115 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_0 |
C7X256V0_CLEC_soc_events_in_IN_10 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_0 |
C7X256V1_CLEC_soc_events_in_IN_10 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_1 |
R5FSS0_CORE0_intr_IN_242 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_1 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_115 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_1 |
C7X256V0_CLEC_soc_events_in_IN_10 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_1 |
C7X256V1_CLEC_soc_events_in_IN_10 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_2 |
R5FSS0_CORE0_intr_IN_242 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_2 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_115 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_2 |
C7X256V0_CLEC_soc_events_in_IN_10 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_2 |
C7X256V1_CLEC_soc_events_in_IN_10 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_3 |
R5FSS0_CORE0_intr_IN_242 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_3 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_115 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_3 |
C7X256V0_CLEC_soc_events_in_IN_10 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_6 |
MAILBOX0_MAILBOX_CLUSTER_6_mailbox_cluster_pend_3 |
C7X256V1_CLEC_soc_events_in_IN_10 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_6 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_0 |
R5FSS0_CORE0_intr_IN_243 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_0 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_116 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_0 |
C7X256V0_CLEC_soc_events_in_IN_11 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_0 |
C7X256V1_CLEC_soc_events_in_IN_11 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_1 |
R5FSS0_CORE0_intr_IN_243 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_1 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_116 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_1 |
C7X256V0_CLEC_soc_events_in_IN_11 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_1 |
C7X256V1_CLEC_soc_events_in_IN_11 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_2 |
R5FSS0_CORE0_intr_IN_243 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_2 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_116 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_2 |
C7X256V0_CLEC_soc_events_in_IN_11 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_2 |
C7X256V1_CLEC_soc_events_in_IN_11 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_3 |
R5FSS0_CORE0_intr_IN_243 |
R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_3 |
MCU_R5FSS0_CORE0_cpu0_intr_IN_116 |
MCU_R5FSS0_CORE0 |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_3 |
C7X256V0_CLEC_soc_events_in_IN_11 |
C7X256V0_CLEC |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |
MAILBOX0_MAILBOX_CLUSTER_7 |
MAILBOX0_MAILBOX_CLUSTER_7_mailbox_cluster_pend_3 |
C7X256V1_CLEC_soc_events_in_IN_11 |
C7X256V1_CLEC |
MAILBOX0_MAILBOX_CLUSTER_7 interrupt request |
level |