When not using the [SP 800-90A] AES-256 DRBG, the startup sequence is relatively straightforward and the engine will generate data automatically to keep the output register and buffer RAM filled:
- Make sure the engine is idle by writing zeroes to the
register twice.
- Write all configuration values in the
and
registers, write zeroes to the
and
registers.
- Enable all FROs in the
register (note that this can only be done after clearing the
register).
- Start the actual engine by setting the [10] ENABLE_TRNG register bit. Set all required _MASK
interrupt mask bits in the
register.
- Optionally, when buffer RAM is configured: Set a data available interrupt
threshold using the [31] LOAD_THRESH and [30-24] BLOCKS_THRESH fields of the
register. This allows delaying the data available interrupt until the indicated
number of 128-bit words are available in the buffer RAM.
- Wait until a data word is available in the
through
registers (using the interrupt and/or the [0]
READY status register bit).
- If secure reading is enabled (with
[15-12] READ_TIMEOUT register field value non-zero), enable the reading by using
the [15-0] OPEN_READ_GATE field or [12] OPEN_READ_GATE2 bit in the
register.
- Read the random data from the
through
registers, then acknowledge the read by writing a '1' to the [0]
READY_ACK register bit.
- If more data is needed, go back to steps 5 or 6 above.