SPRUJB6B November 2024 – May 2025 AM2612
| Register Name | Address Offset |
SW Access |
Description | Register Map |
|---|---|---|---|---|
| PKE_RESET_CTRL | 0x0 |
R/W |
Reset control for Command FIFO and flush control for MAU Core. This register is not self-clearing. |
[19:0] RESERVED [20] pkeFlush input to PKE(active high). When set, this bit will assert the mauFlush input to MAU Core, resets command FIFO, issues reset to MCG. Flush sequence will complete some cycles after this bit is cleared. PKE will remain in flush state as long as this bit is asserted. [31:21] RESERVED |
| PKE_IFC_ISR | 0x18 | R/W |
Interrupt Status Register. Writing a 1 to any bit in this register clears the associated interrupt. Cleared on pkeFlush. |
Empty and !(mauState==BUSY) & !(mcgState==BUSY))
READY/ERROR/PANIC.
if FIFO Write Error is asserted in PKE_STATUS register.
fifoEmpty gets asserted when pkeFlush is issued to the core triggering this interrupt. To disable interrupt just after pkeFlush, user can mask the corresponding bit in PKE_IFC_ICR register |
| PKE_RESET_CTRL | 0x0 |
R/W |
Reset control for Command FIFO and flush control for MAU Core. This register is not self-clearing. |
[19:0] RESERVED [20] pkeFlush input to PKE(active high). When set, this bit will assert the mauFlush input to MAU Core, resets command FIFO, issues reset to MCG. Flush sequence will complete some cycles after this bit is cleared. PKE will remain in flush state as long as this bit is asserted. [31:21] RESERVED |
| PKE_IFC_ISR | 0x18 | R/W |
Interrupt Status Register. Writing a 1 to any bit in this register clears the associated interrupt. Cleared on pkeFlush. |
Empty and !(mauState==BUSY) & !(mcgState==BUSY))
READY/ERROR/PANIC.
if FIFO Write Error is asserted in PKE_STATUS register.
fifoEmpty gets asserted when pkeFlush is issued to the core triggering this interrupt. To disable interrupt just after pkeFlush, user can mask the corresponding bit in PKE_IFC_ICR register |
|
before initializing the pkeFlush sequence and set it after pkeFlush sequence gets completed. Otherwise, this bit must be cleared to clear the interrupt after issuing pkeFlush.
This interrupt is re-asserted when cleared if MAU Core Status is ERROR/PANIC in PKE_STATUS register.
[6]mcgError. Asserted when MCG status indicates ERROR/PANIC. This interrupt is re-asserted when cleared if MCG status is MCG_ERROR/PANIC in PKE_STATUS register [7] ramInitAndFlushOnResetToI dleInt. Asserted when SRAM initialization (when enabled) or FLUSH sequence after reset are completed. The PKE core will go into IDLE state when SRAM initialization (when enabled) and FLUSH sequence after resset finish. [31:8] RESERVED |
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| PKE_IFC_ICR | 0x1C | R/W | Interrupt Control Register. Writing a 1 to any bit in this register enables the associated interrupt. | See PKE_IFC_ISR |
| PKE_STATUS | 0x20 | R |
Reports the status of the Command FIFO, Mau Core, and Mau Command Generator. |
[3:0] Command FIFO Status This reflects the command FIFO status. Cleared on pkeFlush. 0b0000 – FIFO_EMPTY 0b0001 – FIFO_NOT_EMPTY 0b0011 – FIFO_FULL 0b01xx – FIFO_ERROR |
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[7:4] MAU Core Status State 0x0 : MAU_READY 0x1: MAU_BUSY 0x2: MAU_ERROR 0x8: MAU_PANIC Cleared when MAU Core Status is error and pkeFlush is issued. [15:8] Mau Command Generator Unit Status This reflects the command generator unit status. Cleared when MCG Status is error and pkeFlush is issued. 0x0: MCG_IDLE 0x1: MCG_BUSY 0x4: MCG_ERROR 0x8: MCG_PANIC [23:16]: MAU Error Cause Optional field. Refer to the MAU section for more details. Will be cleared on pkeFlush. [27:24]: MCG Error Cause Optional field. MCG currently does not advertise error cause. Will be cleared on pkeFlush. [29:28] Reserved [31:30]: MAU compare result. Reflects the status of compare result when compare command is completed by MAU core only when the MAU command is issued by AHB. Will be cleared on pkeFlush. |
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| PKE_SCRATCH | 0x30 | R/W | Scratch register for testing connectivity | [31:0] mauIfcScratch On reset, this value is 0x7654_3210. |
| MAU_MIN_LEN | 0x34 | R | Specifies the minimum length of commands |
[31:0] This constant register always gives the value of the constant MAU_MIN_LEN. |
| MAU_MAX_LEN | 0x38 | R | Specifies the maximum length of commands |
[31:0] This constant register always gives the value of the constant MAU_MAX_LEN. |
| PKE_VERSION | 0x3C | R | Specifies the PKE version |
[31:0] This constant register always gives the version of PKE. |
| MCG_COMMANDS _ENABLED |
0x40- 0x4C |
R | Specifies the MCG commands enabled |
[127:0] This constant register gives the commands enabled for MCG in the current version. |
| PKE_PRNG_SEED | 0x50- 0x5C | WO |
Register to (re)seed PRNG |
[127:0] When written all 128 bits in this register will reseed PRNG inside PKE. The reseed happens when register at 0x5C is written. So, it is important to write 0x50, 0x54, 0x58 before writing 0x5C. Reseed completes in one cycle, so no status is returned. The register value at 0x50 forms the lowest word of 128 bits and register at 0x5C forms the highest word of 128 bits seed. Reseed vale is {pkePrngSeed(0x5C), pkePrngSeed(0x58), pkePrngSeed(0x54), pkePrngSeed(0x50)} |
| PKE_WORD_SIZE | 0x60 | RO | Specifies the datapath configuration of the PKE core (32x32, 64x64) |
[31:0] This constant register always gives the value of constant MAU_WORD 0x40: MAU_WORD=64 0x20: MAU_WORD=32 |
| PKE_CURVES_IN_ ROM |
0x64- 0x68 |
RO |
Specifies the curves that are supported in ROM |
[63:0] This constant register always gives the value of mcgCurvesSupported. [0]: ’b0 [1]: NIST secp192r1 [2]: NIST secp224r1 [3]: NIST secp256r1 |
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[4]: NIST secp384r1 [5]: NIST secp521r1 [6]: ’b0 [7]: NIST secp256k1 [8-16]: ’b0 [17]: Brainpool secp192r1 [18]: Brainpool secp224r1 [19]: Brainpool secp256r1 [20]: Brainpool secp320r1 [21]: Brainpool secp384r1 [22]: Brainpool secp512r1 [23]: ANSSI FRP256V1 [24]: SM2 [25-32]: ‘b0 [33]: ED25519 [34]: ED448 [35-63]:’b0 Also, refer to Table 1: Elliptic curves supported in ROM |
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| PKE_SPECIAL_PRI MES | 0x6C | RO | Specifies the curves with special primes which have special prime unit implemented |
[31:0] This constant register always gives the value of mcgPrimesSupported [0]: ‘b1 [1]: NIST secp192r1 [2]: NIST secp224r1 [3]: NIST secp256r1 [4]: NIST secp384r1 [5]: NIST secp521r1 [6]: Ed448 [7]: SM2 [8-31]: ‘b0 |
|
PKE_SRAM_ADDR _MIN |
0x70 | RO | Specifies the minimum SRAM address |
[31:0] This constant register gives the value of mauWcMemMinAddrConst |
| PKE_SRAM_ADDR _MAX | 0x74 | RO | Species the maximum SRAM address |
[31:0] This constant register gives the value of mauWcMemMaxAddrConst |
|
PKE_SRAM_ADDR _BASE – PKE_SRAM_ADDR _TOP |
0x2000 – 0x3FFC | R/W | Access the Working Context SRAM |
[31:0] Each word-aligned address accesses a word in the Working Context Memory. |